JPH01204292A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To attain high speed reading to correspond to a request in a reading side without using a special memory cell, which intends high speed operation in a writing side, by causing a reading port and a writing port to be pipe-line structure, in which the number of steps is respectively different. CONSTITUTION:When address information are given to the reading port or the writing port, a memory cell 14 to correspond to the address information is selected by a reading decoder 3 or a writing decoder 13 and the reading or writing of storing information is executed by a read amplifier or a write amplifier 15. Before and after the reading decoder 3 and read amplifier, the pipe-line structure of the latch of the plural steps is provided to hold data in the reading side based on a clock signal CLK. Then, before and after the writing decoder 13 and write amplifier 15, the pipe-line structure of the latch of the step number, which is different from the reading side, is provided to hold the data in the writing side based on the clock signal CLK. Thus, while the writing is executed with comparatively low speed operation to correspond to a speed in the writing side, the reading speed can be easily improved at a low cost.

Description

[Detailed Description of the Invention] [Table of Contents] (Overview Field of Application in Graduation Prior Art Problems to be Solved by the Invention Means for Solving Problems Examples of Actions (1) Basic Principles of the Present Invention Figure 5.6) (2)
Embodiment of the present invention (Figures 1 to 4) Effects of the invention [Summary] Regarding a semiconductor memory device in which a read port and a write port are pipelined, write operations can be easily realized at a low cost while performing a write operation at a relatively low speed. The purpose of the present invention is to provide a semiconductor memory device that has a read port used to read stored information and a write port used to write the information, and has address information to the read port or the write port. In a semiconductor memory device in which a memory cell corresponding to the address information is selected by a decoder, memory information is successively written through a read amplifier, and the information is written through a write amplifier, the read port is connected to a plurality of stages of pipes. In addition to forming the write port into a line structure, the write port has a pipeline structure in which the number of pipeline stages is different from that of the read port.

C. Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a read port and a write port are pipelined.

[Conventional technology]

Recently, the application fields of digital technology are wide-ranging.
There is a demand for processing large amounts of data at high speed.

By the way, semiconductor memory devices (hereinafter simply referred to as memories) are inseparable from digital technology, and there are cases where a memory is required to have only a high read speed.

For example, personal computers and workstations often output image information to convey processing results to users in an easy-to-understand manner.
The processing results written in the frame buffer (hereinafter referred to as a frame buffer) are output to a display device such as a CRT display. That is, the processing results are read out from the frame buffer in real time at a speed determined by the scanning frequency and number of pixels of the display device, and the readout speed tends to increase as the number of pixels increases. Further, the number of pixels of display devices tends to increase in order to improve display performance, that is, resolution, and when supporting such display devices, it is necessary to read out information from the frame buffer at a sufficient speed.

In addition, in the communications field, efforts are being made to increase communication speeds.
BACKGROUND OF THE INVENTION Information stored in memory is continuously output at high speed to a communication system.

[Conventional technology]

As a conventional semiconductor memory device that supports such high-speed reading, static RAM (
S-RAM), which achieves a cycle time of 2 to 3 ns.

Furthermore, a C-MOS-based S-RAM has achieved a cycle time of 25 ns, which is a fairly high level of achievement in terms of speeding up the cycle time.

[Problem to be solved by the invention]

However, since such conventional semiconductor memory devices simply increase the operating speed, they have the following problems.

In other words, in devices such as the above-mentioned frame buffer, where speeding up is required only for successive outputs, there is often plenty of time for writing, and this is due to the fact that the processing speed of the writing side, such as the CPU, can only be performed at a relatively low speed. . For example, even if the CPU clock is moderately 10 MHz, the write operation takes about 1 to 2 M Ilz (1 ms to 500 ns).

In this way, even though the writing side may be relatively slow, a high-speed memory is required just to accommodate the high-speed reading.

In this case, the ECL's 5-RAM described above is sufficiently fast, but it is difficult to achieve high integration, so many chips are required to configure the image memory, that is, the large-capacity frame buffer. It is necessary to combine them. In addition, because the power consumption is large in order to increase the speed, it is necessary to fully consider the cooling method, and - liquid cooling systems are used for boat fishing. Furthermore, since ECL itself is expensive, if a large number of 5-RAMs of ECL are used to realize a high-speed, large-capacity frame buffer, the cost will be large. For these reasons, it is difficult to miniaturize the device, and the device tends to become expensive.

In addition, in the case of C-MOS type 5-RAM, ECL's S
-Although most of the disadvantages of RAM have been overcome, the current state of the art may limit its use in terms of speed. That is, assuming that one frame is 6011z and a display of 800×400 pixels is assumed, the dot clock frequency corresponding to each pixel is 19.2MIIz, which is about 52ns. In this case, the cycle time mentioned above is 25 ns.
-MO3-based S-RAM can be used. However, with the demand for higher resolution, 1000 x 100
There is also a display device that can display 0 pixels, and in this case, it is necessary to realize a cycle time of 17 ns or less, which cannot be achieved with a 25 ns 5-RAM.

As described above, increasing the speed of memory requires advanced technology and increases cost.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device that performs a write operation at a relatively low speed while increasing the speed of a read operation that can be easily realized at low cost.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory 4+2 device according to the present invention has a read port used for reading the above information and a write port used for reading the information, and provides address information to the read port or m write port. A semiconductor memory device in which a memory cell corresponding to the address information is selected by a decoder, reads out stored information via a read amplifier, and receives the information via a write amplifier,
The read port has a pipeline structure with multiple stages, and the statement port has a pipeline structure with a number of pipeline stages different from that of the read port.

[For production]

In the present invention, the read port or the write port has a
When address information is given, the memory cell corresponding to the address information is selected by the read or read decoder, and the read amplifier or write amplifier reads or corrupts the memory information, and the read decoder and read Before and after the amplifier, there are multiple stages of latches (
A pipeline structure) is provided before and after the write decoder and the write amplifier, and launches (pipeline structure) with a different number of stages than the read side that hold data on the write side are provided based on a clock signal.

Therefore, while writing is performed at a relatively low speed corresponding to the writing speed, the reading speed can be easily increased at low cost.

〔Example〕

The present invention will be explained below based on the drawings, but first, the basic principle regarding the pipeline structure will be explained with reference to FIG. 5.6.

When a memory performs a single operation, such as reading continuously, the minimum time required for one read is called cycle time, and it is well known that it is an important factor that determines the responsiveness, or speed, of the memory. Are known.

Here, when considering the details of the cycle time tc, it can be considered as shown in the following equation (2).

tc=tr+trd+ts+td ・-・・-・■However, tr: Low decode time trd: Lead time tS: Sense time td: Output drive time In this way, data is read through various steps during the cycle time. However, by performing one step every clock cycle, the time required for reading can be reduced to only the lead time trd. For example, the cycle time tc of a certain RAM is 3
0 ns, and the breakdown is as shown in the following formula 〇, tc=tr+trd+ts+td=(7+,12+8+3)n S...-
...■The longest of each step is lead time Tr
d, it is possible to perform 12nST: reading by disassembling and processing each step. A method in which each step is decomposed in synchronization with a clock and processed at different timings is called a pipeline method.

An example of such a pipeline type semiconductor memory device is the one shown in FIG. In the figure, address data Adr is latched by a flip-flop F)1 in the first cycle of a clock (CLK), and decoded by a decoder 2 into word line data WL corresponding to the address data Ad. Word line data WL
is latched by FF3 in the second cycle of CLK, and the word line of memory 4 is selected. When a word line is selected, the bit line data BL is latched by the FF 5 in the third cycle of CLK, a predetermined memory cell is selected, and the data is input to the sense amplifier 6. The output of the sense amplifier 6 is latched by the FF 7 in the fourth cycle of CLK, and this becomes the output data Dr. If this is made into a timing chart, it will be as shown in FIG. 6, in which predetermined signals are sequentially latched in each clock cycle and output data Dr is obtained. Therefore, by determining the frequency of the clock signal CLK so that the longest one of the decomposed steps can be processed as described above, reading of the read data Dt is performed using the clock signal CLK.
Even if the configuration of the memory 4 is the same, the reading speed can be increased compared to the case where pipeline processing is not performed. In this case, four clock cycles are required from launching address data Adr to finalizing output data Dr, but in applications where successive outputs are performed at high speed, a slight delay is often not a problem.

Note that since writing is performed in the same manner, a description thereof will be omitted.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing the structure of an S-RAM that is used in an embodiment of the semiconductor memory device according to the present invention.

For convenience of explanation, this S-RAM will be explained first, and the same components as those of the aforementioned pipelined RAM will be given the same reference numerals, and the explanation thereof will be omitted.

In the same figure, 11 is S-RAM, and S-RA
MII is a so-called multiport memory. Address data Adw on the write side is input to FF12, and FF1
2 is the address data Ad according to the clock signal CLKw.
Latch w. The clock signal CLKw has a completely different timing from the clock signal CLKr on the reading side, and the clock signal CLKw is set according to the processing speed on the writing side, and the clock signal CLKr is set according to the request on the reading side such as a display device. . All of the address data Ad launched by the FF 12 is input to the decoder 13, and the decoder 13 decodes it into write-side word line data WLw according to the address data Ad-. That is, decoder I3 selects a row address within memory 14. On the other hand, the write data Dw is written to the write amplifier 15.
and the write amplifier 15 receives the address data Adw.
Select the bit line BLw on the write side based on . As a result, the write data Dw is written into a memory cell (not shown) corresponding to the address data Ad- in the memory 14.

As shown in FIG. 2, the memory cell of the memory 14 has a flip-flop 21, and the flip-flop 21 is constructed by two inverters 22 and 23 connected cross-wise. Write transfer gates 24 and 25 are connected to the flip-flop 21, and the flip-flop 21 is set when the data in the transfer gates 24 and 25, that is, the write word line WLW and the write bit lines BLW and BLw, respectively, become active. , holds predetermined data. Further, a read transfer gate 26 is connected to the flip-flop 21, and the transfer gate 26 includes transistors 26a and 26b. Transfer gate 26
When the word line WLR on the read side is active, the data of the flip-flop 21 is transferred to the bit line B L R
However, the bit line B L * is precharged in advance, and the data of the flip-flop 21 and the bit line WL. When both are active, transistor 26a and transistor 26b are turned on to discharge the precharge voltage of bit line BLR. In this case, the data in the flimp flop 21 can be transferred to the bit line BLR simply by discharging the precharge voltage, so it is expected that the read speed will be increased.

FIG. 3 shows a data processing circuit for calculating the read data Dr and other data (calculated data) Do of the S-RAMII. Output.

Further, the calculation data Do is data other than addresses,
For example, it is text data stored in a video RAM (V-RAM) or the like. The calculation data DO is input to the pipeline register 31, and although not shown in the figure, the pipeline register 31 receives the successive clock CLKr.
It has a flip-flop that transmits data in synchronization with the . In this case, four stages of flip-flops are connected in series for one bit of operation data DO, and this number of stages is equal to the number of pipeline stages of the read port of S-RAMII, that is, FFI, 3.5 and 7 stages. Match the numbers. When the operation data Do is input to the pipeline register 31, the flip-flops inside the pipeline register 31 sequentially transmit the operation data l)o to the next stage flip-flops according to the read clock CLKr, and finally the pipeline The register 31 outputs the calculated data Dod. That is, the operation data Dod is outputted with a delay of four clock cycles of the read clock CLKr than the operation data [)o.

In the above configuration, data is written to the S-RAM II as shown in FIG. That is, the address data Ad- is latched into the FF 12 of the S-RAM II at the rising edge of the write clock CLKw, and the write data [)w is input to the write amplifier 15 at the second clock cycle of the write clock CLKw. Therefore, the write data is written into the memory 14 with a delay of one clock after the address is specified. in this case,
The write clock CL%r may be set at a different timing from the read clock CLKr, and the write clock CL%r may be set to a timing different from that of the read clock CLKr, and the write clock CL%r may be set to a timing different from that of the read clock CLKr.
The timing can be set according to the processing speed. On the other hand, on the read side, the number of pipeline stages is four to speed up the read cycle, so that high-speed read can be performed in accordance with the demands of the display device, etc. in this case,
Each memory cell of S-RAMII has the same configuration, and the EC
It is not intended for particularly high-speed operation like L. Therefore, since S-RAM II can be easily realized, the read speed can be increased at low cost. Also,
When calculating read data Dr from S-RAMII and other calculation data DO, as shown in FIG. The timings of the read data Dr and the calculated data Dod can be completely matched. Therefore, calculation accuracy can be improved.

〔effect〕

According to the present invention, since the read port and the write port each have a pipeline structure with a different number of stages, writing can be performed at a speed corresponding to the processing speed on the writing side, and a special memory cell intended for high-speed operation can be used. It is possible to perform high-speed reading according to the demands of the reading side without using the .

Therefore, it is possible to obtain a semiconductor memory device which can be easily realized at low cost and has a high speed read operation.

[Brief explanation of the drawing]

1 to 4 are diagrams showing one embodiment of a semiconductor memory device according to the present invention, FIG. 1 is a configuration diagram showing the configuration of an S-RAM thereof, and FIG. 2 is a diagram showing a memory cell of the S-RAM. 3 is its overall configuration diagram, FIG. 4 is a timing chart showing the write operation of the S-RAM, and FIG. 5.6 is a diagram explaining the basic principle of pipelined RAM. FIG. 5 is a configuration diagram showing an example thereof, and FIG. 6 is a timing chart showing the read operation. 1.3.5.7.12...Flip-flop,
11...5-RAM. 14...Memory, 31...Pipeline register. Write data l) w Drunk r - Example 3 - Second circuit diagram showing memory cell of RAII
figure

Claims (1)

[Claims] It has a read port used for reading stored information and a write port used for writing the information, and when address information is given to the read port or the write port, the memory cell corresponding to the address information is selected by the decoder. In a semiconductor memory device that is selected and reads stored information through a read amplifier and writes the information through a write amplifier, the read port has a multi-stage pipeline structure, and the write port is a pipe of the read port. A semiconductor memory device characterized by having a pipeline structure having a number of stages different from the number of line stages.