JP2008269751A - Semiconductor memory device and electronic equipment having semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device holding a storage state even when a power supply is turned off, manufactured at a cost same as a volatile memory, and having a read or write speed same as the volatile memory. <P>SOLUTION: The semiconductor memory device includes a transistor for selecting a memory cell, and a latch circuit for maintaining a storage state of the memory cell. A diode is connected at a high-potential power supply side of an inverter circuit configuring the latch circuit, and a capacitive element is connected to the latch circuit. In the semiconductor memory device including the latch circuit, even when the power supply is turned off, the capacitive element connected to the latch circuit holds a potential, and the diode connected at the high-potential power supply side of the inverter circuit configuring the latch circuit can prevent leakage of a charge held by the capacitive element. As a result, it is possible to provide a non-volatile semiconductor memory device at a low cost. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a semiconductor memory device. In particular, the present invention relates to a nonvolatile semiconductor memory device.

Memory devices using semiconductor characteristics (hereinafter referred to as semiconductor memory devices) are incorporated into a plurality of electronic devices and have been commercialized in many ways. Semiconductor memory devices can be broadly classified into volatile memories and nonvolatile memories. Examples of the volatile memory include a register, an SRAM (Static Random Access Memory), and a DRAM (Dynamic Random Access Memory), and the nonvolatile memory includes a Flash EEPROM (flash memory).

Although the volatile memory is superior to the nonvolatile memory in reading and writing data, there is a drawback that the data is lost when the power is turned off. On the other hand, the non-volatile memory has an advantage that the data is not lost even when the power is turned off, but is significantly inferior to the reading / writing speed of the volatile memory. For this reason, research and development of non-volatile SRAM (also referred to as non-volatile static random access memory (SRAM)) that retains data even when the SRAM, which is a volatile memory, is turned off (patents) Reference 1 and Patent Reference 2).
Japanese Patent Application Laid-Open No. 2004-146048 JP 2004-207282 A

In order to make the volatile memory non-volatile, it is necessary to be able to maintain the storage state with the power turned off. A memory cell included in an SRAM which is a volatile memory includes a selection transistor and a latch circuit (also simply referred to as a latch) including two inverter circuits (also simply referred to as an inverter). While power is input, the latch in the SRAM holds a power supply potential (also referred to as H potential or high potential power supply) or a ground potential (also referred to as L potential or low potential power supply). However, when the power is turned off, the output of the inverter constituting the latch cannot maintain the output of the H potential or the L potential, and as a result, the storage state cannot be maintained in the SRAM which is a volatile memory. Therefore, in order to use a volatile memory having a latch such as an SRAM as a nonvolatile memory, a configuration in which a nonvolatile memory element such as a ferroelectric capacitor is provided in the memory cell is employed. A volatile memory having a nonvolatile memory element such as a ferroelectric capacitor in a memory cell has disadvantages such as high manufacturing cost and low writing speed.

Therefore, in view of the above problems, the present invention can maintain a memory state even when the power is turned off, can be manufactured at a cost similar to that of a volatile memory, and has a reading or writing speed comparable to that of a volatile memory. It is an object of the present invention to provide a semiconductor memory device.

One embodiment of the present invention includes a transistor for selecting a memory cell and a latch circuit for holding the memory state of the memory cell, and a diode is connected to the high potential power supply side of the inverter circuit constituting the latch circuit. The capacitor element is connected to the latch circuit. In a semiconductor memory device having a latch circuit, a capacitor connected to the latch circuit holds a potential even when the power is turned off, and a diode connected to the high potential power supply side of the inverter circuit constituting the latch circuit includes Leakage of charges held in the capacitor can be prevented. As a result, a nonvolatile semiconductor memory device can be provided at low cost.

According to another aspect of the semiconductor memory device of the present invention, the gate terminal has a first transistor and a second transistor connected to the read / write word line, a read / write bit signal line connected to the first transistor, and a second transistor. And a latch circuit for holding a storage state of data written from a read / write bit inversion signal line connected to the two transistors, a first inverter circuit constituting the latch circuit, The second inverter circuit is connected so that a power supply potential is supplied from a diode connected to a power supply line, and the output terminal of either the first inverter circuit or the second inverter circuit has A capacitor element is connected.

According to another aspect of the semiconductor memory device of the present invention, the gate terminal has a first transistor and a second transistor connected to the write word line, a read / write bit signal line connected to the first transistor, and a second transistor. A latch circuit for holding a storage state of data written from a read / write bit inversion signal line connected to the transistor of the first and second gates, wherein the gate terminal constitutes the latch circuit A memory cell including a third transistor connected to any one of the output terminals and a fourth transistor having a gate terminal connected to a read word line, and the first inverter circuit and the first transistor The inverter circuit 2 is connected so that a power supply potential is supplied from a diode connected to the power supply line. The first terminal of either the third transistor or the fourth transistor is connected to the ground line, and the other first terminal of the third transistor or the fourth transistor is connected to the read bit line. The second terminal of the third transistor is connected to the second terminal of the fourth transistor.

According to another aspect of the semiconductor memory device of the present invention, the gate terminal has a first transistor and a second transistor connected to the write word line, a read / write bit signal line connected to the first transistor, and a second transistor. The latch circuit for holding the storage state of the data written from the read / write bit inversion signal line connected to the transistor and the gate terminal are connected to the output terminal of the first inverter circuit constituting the latch circuit. The third transistor, the fifth transistor whose gate terminal is connected to the output terminal of the second inverter circuit constituting the latch circuit, and the first transistor whose gate terminal is connected to the first read word line. 4 and a sixth transistor having a gate terminal connected to the second read word line. The first inverter circuit and the second inverter circuit are connected so that a power supply potential is supplied from a diode connected to a power supply line, and either the third transistor or the fourth transistor is connected. One first terminal is connected to a ground line, and the other first terminal of the third transistor or the fourth transistor is connected to a first read bit line, and A second terminal and a second terminal of the fourth transistor are connected, and a first terminal of one of the fifth transistor and the sixth transistor is connected to the ground line, and the fifth terminal The other first terminal of the sixth transistor or the sixth transistor is connected to the second read bit line, and the fifth transistor Wherein the second terminal of the second terminal fifth transistor of motor is connected.

According to the present invention, a nonvolatile semiconductor memory device with improved writing speed and low manufacturing cost can be provided. In addition, since the semiconductor memory device of the present invention is non-volatile, the memory state can be maintained with the power turned off when data is not written or read, and power consumption is reduced. Can be planned.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.
(Embodiment 1)

In this embodiment, a structure of a nonvolatile semiconductor memory device is described with reference to a block diagram, a circuit diagram, and the like. Note that a semiconductor memory device in this specification refers to a memory device that retains a data storage state using semiconductor characteristics.

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device described in this embodiment. A semiconductor memory device 100 shown in FIG. 1 includes a decoder 101, a write / read circuit 102, and a memory cell array 103. The decoder 101 is connected to the first address signal line 104, the write enable signal line 105, and the read enable signal line 106. The decoder 101 is connected to a plurality of memory cells 107 via read / write word lines 108. The write / read circuit 102 is connected to a write enable signal line 105, a read enable signal line 106, a second address signal line 109, an input data signal line 110, and an output data signal line 111. The write / read circuit 102 is connected to a plurality of memory cells 107, a read / write bit signal line 112, and a read / write bit inversion signal line 113. Further, in the semiconductor memory device 100, a plurality of memory cells are supplied with a power supply potential (also referred to as an H potential or a high potential power supply, and expressed as “1” in the drawing). ) And a ground potential (also referred to as an L potential or a low potential power supply. Also referred to as “0” in the drawing) are provided with a first power supply control circuit 114a and a second power supply control circuit 114b. . The first power supply control circuit 114 a and the second power supply control circuit 114 b and the plurality of memory cells 107 include a power supply line 115 for inputting a power supply potential to the memory cell 107 and a ground line 116 for inputting a ground potential. Connected through.

Note that in this embodiment mode, a read / write word line refers to a word line for reading and writing data in a memory cell. The read / write bit line and the read / write bit inversion signal line refer to a bit line and a bit inversion signal line for reading and writing data in the memory cell.

In this specification, the number of bit lines is also referred to as the number of bits, and the number of word lines is also referred to as the number of lines.

In this embodiment, the first power supply control circuit 114a and the second power supply control circuit 114b are arranged in the semiconductor memory device 100, but any one of them may be used. As shown in FIG. 1, a configuration in which a power supply potential and a ground potential are supplied from both sides of the memory cell array 103 enables a desired potential to be supplied to a plurality of memory cells more reliably.

In FIG. 1, the memory cell 107 can hold a 1-bit value. The memory cell array 103 has as many memory cells 107 as (number of bits) × (number of lines).

The write / read circuit 102 writes data input from the input data signal line 110 from the outside of the semiconductor memory device 100 to each memory cell 107 of the memory cell array 103, and reads and outputs data from each memory cell 107 of the memory cell array 103. A process of transmitting data to the outside of the memory through the data signal line 111 is performed.

The decoder 101 outputs a signal to the read / write word line 108 according to the address input from the first address signal line from the outside of the semiconductor memory device 100.

The decoder 101 outputs a signal to the read / write word line 108 to control reading and writing of data in each memory cell 107. For example, at the time of writing, one of the read / write word lines 108 is in a high potential state (hereinafter referred to as “H potential”. Also referred to as “1” in the drawing), and at the time of reading, one of the read / write word lines 108 is. One becomes H potential. When the read / write word line 108 is not selected, the ground potential state (hereinafter referred to as “L potential” and also referred to as “0” in the figure) is obtained.

The read / write bit signal line 112 and the read / write bit inverted signal line 113 are read and write bit lines, respectively. At the time of reading, the value of the memory cell selected by the address is input to the read / write bit signal line 112 and the read / write bit inverted signal line 113, and at the time of writing, external data is read / written bit signal line 112 and read / write bit inverted signal line. 113 is input.

With such a semiconductor memory device 100, information corresponding to the number of bits and the number of lines can be stored.

Next, a circuit diagram of the memory cell 107 in FIG. 1 will be described with reference to FIG. As shown in FIG. 1, the memory cell 107 shown in FIG. 2A includes the read / write word line 108, the read / write bit signal line 112, the read / write bit inverted signal line 113, the power supply line 115, and the ground line 116. Connected. The memory cell 107 includes a first N-channel transistor 201a (also referred to as a first transistor), a second N-channel transistor 201b (also referred to as a second transistor), a latch circuit 202, a diode 203, and a first capacitor. An element 204a and a second capacitor 204b are included.

In FIG. 2A, the first N-channel transistor 201 a functions as a switch that switches whether to input the potential of the read / write bit signal line 112 to the latch circuit 202 based on the potential of the read / write word line 108. Have Further, the second N-channel transistor 201 b has a function as a switch for switching whether to input the potential of the read / write bit inversion signal line 113 to the latch circuit 202 based on the potential of the read / write word line 108. The diode 203 has a function of supplying a power supply potential from the power supply line 115 to the latch circuit 202 and preventing leakage of electric charge from the latch circuit. The first capacitor 204 a is connected to one node of the latch circuit (an output terminal of one inverter circuit) and the ground line 116 and has a function of holding the potential of one node of the latch circuit 202. The second capacitor 204b is connected to the other node of the latch circuit (the output terminal of the other inverter circuit) and the ground line 116, and has a function of holding the potential of the other node of the latch circuit 202.

FIG. 2B shows a circuit diagram equivalent to FIG. 2A in order to explain the operation of FIG. The latch circuit 202 includes a first inverter circuit 202a and a second inverter circuit 202b, and an input terminal and an output terminal are connected to each other. The first inverter circuit 202 a includes an N-channel transistor 251 and a P-channel transistor 252. A diode is connected to the first terminal of the P-channel transistor 252 so as to supply a power supply potential from the power supply line 115. A second terminal of the P-channel transistor 252 is connected to a first terminal of the N-channel transistor 251. A second terminal of the N-channel transistor 251 is connected to the ground line 116. A diode is connected to the first terminal of the P-channel transistor 254 so as to supply a power supply potential from the power supply line 115. A second terminal of the P-channel transistor 254 is connected to a first terminal of the N-channel transistor 253. A second terminal of the N-channel transistor 253 is connected to the ground line 116.

Note that a transistor is an element having at least three terminals including a gate, a drain, and a source. The transistor has a channel region between the drain region and the source region, and the drain region, the channel region, and the source region. A current can be passed through the. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this document (the specification, the claims, the drawings, and the like), a region functioning as a source and a drain may not be referred to as a source or a drain. In that case, as an example, they are referred to as a first terminal and a second terminal, respectively. The gate is expressed as a gate terminal. Note that in this document (the specification, the claims, the drawings, and the like), an N-channel transistor or a P-channel transistor will be described separately for the transistors included in the memory cell for description. However, when a transistor is simply used as a switch, either an N-channel transistor or a P-channel transistor may be used. In this case, it may be simply expressed as a transistor.

Note that in this embodiment, data “1” is written in the memory cell 107 in FIG. 1 when the potential of the node 281 that is the input terminal of the first inverter circuit 202a is the H potential and the second inverter This means that the potential of the node 282 which is an input terminal of the circuit 202b is an L potential. Data “0” is written when the potential of the node 281 that is the input terminal of the first inverter circuit 202a is L potential and the potential of the node 282 that is the input terminal of the second inverter circuit 202b is It means an H potential.

3A and 3B are circuit diagrams of the memory cell shown in FIG. 2B. In the case where data “1” is held, each wiring when the power is turned off and It is a figure which shows the state of a node and the on or off state of each transistor, and demonstrates operation | movement.

First, referring to FIG. 3A, the state of the potential of each wiring and node connected to the memory cell holding data “1” and the on / off state of each transistor will be described. In FIG. 3A, when data “1” is input to the node 281 or data “0” is input to the node 282, the on / off state of the transistors included in the inverter circuit is determined. The potential of the output terminal of the inverter circuit is determined from the potential (denoted as “1” in the figure) or the ground potential of the ground line 116 (denoted as “0” in the figure).

As shown in FIG. 3A, the memory cell holds data “1” while the power supply potential from the power supply line 115 is supplied.

Next, when the power is turned off in FIG. 3B, that is, when the power supply potential of the power supply line 115 becomes the ground potential, the potential of each wiring and node connected to the memory cell holding the data “1” And the on / off state of each transistor will be described. In FIG. 3B, the data “1” of the node 281 is configured such that the potential of the output terminal of the first inverter circuit 202a forms the first inverter circuit 202a when the power supply potential of the power supply line 115 becomes the ground potential. Since the on / off state of the transistor to be changed does not change, the data of the node 282 remains “0”. On the other hand, in FIG. 3B, the data “0” of the node 282 is generated when the power supply potential of the power supply line 115 becomes the ground potential although the on / off state of the transistors included in the first inverter circuit 202a does not change. The power supply potential from the power supply line is not supplied to the output terminal of the second inverter circuit 202b.

As described with reference to FIG. 3B, the case where the potential of the node 281 is held when the power supply potential is not supplied from the power supply line 115 will be described with reference to FIG. As shown in FIG. 5A, the potential of the node 281 is held in the first capacitor element 204a, and the gate terminal of the transistor constituting the first inverter circuit 202a and the P channel of the second inverter circuit 202b. Charge leakage can be prevented by the diode 203 connected to the transistor. Therefore, data can be retained even when the power is turned off, so that a nonvolatile semiconductor memory device can be obtained.

In addition, with reference to FIG. 4A, the state of the potential of each wiring and node connected to the memory cell holding data “0” and the on / off state of each transistor will be described. In FIG. 4A, when data “0” is input to the node 281 or data “1” is input to the node 282, the transistors included in the inverter circuit are turned on or off, whereby the power supply of the power supply line 115 is determined. The potential of the output terminal of the inverter circuit is determined from the potential or the ground potential of the ground line 116.

As shown in FIG. 4A, the memory cell holds data “0” while the power supply potential from the power supply line 115 is supplied.

Next, when the power is turned off in FIG. 4B, that is, when the power supply potential of the power supply line 115 becomes the ground potential, the potential of each wiring and node connected to the memory cell holding the data “0” And the on / off state of each transistor will be described. In FIG. 4B, the data “1” of the node 282 is configured such that the potential of the output terminal of the second inverter circuit 202b forms the second inverter circuit 202b when the power supply potential of the power supply line 115 becomes the ground potential. Since the on / off state of the transistor to be changed does not change, the data of the node 281 remains “0”. On the other hand, in FIG. 4B, the data “0” of the node 281 indicates that the power supply potential of the power supply line 115 becomes the ground potential although the on / off state of the transistors included in the first inverter circuit 202a does not change. The power supply potential from the power supply line is not supplied to the output terminal of the first inverter circuit 202a.

As described with reference to FIG. 4B, the fact that the potential of the node 282 is held when the power supply potential is not supplied from the power supply line 115 will be described with reference to FIG. As shown in FIG. 5B, the potential of the node 282 is held in the second capacitor element 204b, and the gate terminal of the transistor included in the second inverter circuit 202b and the P channel of the first inverter circuit 202a. Charge leakage can be prevented by the diode 203 connected to the transistor. Therefore, data can be retained even when the power is turned off, so that a nonvolatile semiconductor memory device can be obtained.

Note that although a structure in which the diode 203 is provided for each memory cell is described in this embodiment mode, the present invention is not limited to this. The diode may be provided for each power supply line. By adopting a structure in which a diode is provided for each power supply line, it is possible to reduce the size of the memory cell and to make each memory cell non-volatile.

With the diode and the capacitor included in the memory cell of the semiconductor memory device described in this embodiment, data can be held even when the power is turned off as described above. If the memory cell holds either data “1” or data “0”, when the power supply potential is supplied again from the power supply line, either the first capacitor 204 a or the second capacitor 204 b is used. Based on the retained charge, the memory cell can continue to retain data again. Therefore, the capacitor is not limited to the structure including both the first capacitor 204a and the second capacitor 204b, and as shown in FIG. 6A, the memory cell shown in FIG. Alternatively, only the first capacitor 204a may be provided to hold data. As shown in FIG. 6B, only the second capacitor 204b may be provided in the memory cell shown in FIG. 2A to hold data. By adopting a structure in which the capacitor provided with the memory cell is connected to only one node of the latch circuit, the memory cell can be reduced in size.

In the memory cell of the semiconductor memory device described in this embodiment, data can be retained without always supplying the power supply potential from the power supply line supplied to the latch circuit. Therefore, in the memory cell of the semiconductor memory device described in this embodiment, power supply can be reduced because data power can be supplied every certain period in order to hold data.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 2)

In this embodiment, a structure of a nonvolatile semiconductor memory device which is different from the above embodiment will be described with reference to a block diagram, a circuit diagram, and the like. In the semiconductor memory device described in this embodiment, in addition to the effects described in Embodiment 1, reading and writing of data from a memory cell are performed by using different wirings. The structure of the semiconductor memory device that can perform the above operation more reliably and at high speed will be described in detail.

FIG. 7 is a block diagram of a nonvolatile semiconductor memory device described in this embodiment. A semiconductor memory device 700 shown in FIG. 7 includes a decoder 701, a write / read circuit 702, and a memory cell array 703. The decoder 701 is connected to the first address signal line 704, the write enable signal line 705, and the read enable signal line 706. The decoder 101 is connected to a plurality of memory cells 707 through a write word line 708 and a read word line 721. The write / read circuit 702 is connected to a write enable signal line 705, a read enable signal line 706, a second address signal line 709, an input data signal line 710, and an output data signal line 711. The write / read circuit 702 is connected to the plurality of memory cells 707, the write bit signal line 712, the write bit inversion signal line 713, and the read bit line 722. In the semiconductor memory device 100, a plurality of memory cells include a power supply potential (also referred to as an H potential or a high potential power supply, also referred to as “1” in the drawing) and a ground potential (also referred to as an L potential or a low potential power supply). In addition, it has a first power supply control circuit 714a and a second power supply control circuit 714b for supplying "." The first power supply control circuit 714 a and the second power supply control circuit 714 b and the plurality of memory cells 707 include a power supply line 715 for inputting a power supply potential to the memory cell 707 and a ground line 716 for inputting a ground potential. Connected through.

Note that in this embodiment mode, a write word line refers to a word line for writing data in a memory cell. The read word line refers to a word line for reading data from a memory cell. The write bit line and the write bit inversion signal line are a bit line and a bit inversion signal line for writing data in the memory cell. The read bit line refers to a bit line for reading data from a memory cell.

Note that in this embodiment mode, the first power supply control circuit 714a and the second power supply control circuit 714b are arranged in the semiconductor memory device 700, but any one of them may be used. As shown in FIG. 7, a configuration in which a power supply potential and a ground potential are supplied from both sides of the memory cell array 703 enables a desired potential to be supplied to a plurality of memory cells more reliably.

Note that the semiconductor memory device shown in FIG. 7 is different from the semiconductor memory device shown in FIG. 1 in the above embodiment in that a write word line 708 is used as a wiring for reading and writing data from a memory cell. And the read word line 721, the write bit signal line 712, the write bit inversion signal line 713, and the read bit line 722 are used. By separately providing wirings for reading and writing data, a semiconductor memory device that can read data from memory cells more reliably and at high speed can be obtained.

In FIG. 7, the memory cell 707 can hold a 1-bit value. The memory cell array 703 has memory cells 707 corresponding to the number of (number of bits) × (number of lines).

The writing / reading circuit 702 writes data input from the input data signal line 710 from the outside of the semiconductor memory device 700 to each memory cell 707 of the memory cell array 703 and reads and outputs data from each memory cell 707 of the memory cell array 703. Processing for transmitting data to the outside of the memory is performed by the data signal line 711.

The decoder 701 outputs a signal to the write word line 708 or the read word line 721 according to the address input from the first address signal line from the outside of the semiconductor memory device 700.

The decoder 701 outputs a signal to the write word line 708 or the read word line 721, and controls reading or writing of data in each memory cell 707. For example, at the time of writing, one of the write word lines 708 is in a high potential state (hereinafter referred to as “H potential”. Also referred to as “1” in the drawing), and at the time of reading, one of the read word lines 721 is at the H potential. It becomes. Note that when the write word line 708 and the read word line 721 are not selected, the ground potential state (hereinafter referred to as “L potential” and also referred to as “0” in the figure) is obtained.

The write bit signal line 712 and the write bit inverted signal line 713 are write bit lines, respectively. At the time of writing, external data is input to the write bit signal line 712 and the write bit inverted signal line 713. The read bit line 722 is a read bit line. At the time of reading, the potential of the read bit line that changes based on the data of the memory cell selected by the address is read after being precharged by the write / read circuit 702.

With such a semiconductor memory device 700, information corresponding to the number of bits and the number of lines can be stored.

Further, the configuration of the memory cell of FIG. 6B described in the first embodiment is shown in FIG. 8A, but in the memory cell shown in this embodiment, the inverter circuit is abbreviated as FIG. It will be represented by a circuit diagram as shown in FIG. The circuit diagrams shown in FIGS. 8A and 8B are the same circuit diagrams.

Next, a circuit diagram of the memory cell 707 in FIG. 7 will be described with reference to FIG. The memory cell 707 of this embodiment shown in FIG. 9 includes a write word line 708, a read word line 721, a write bit signal line 712, a write bit inverted signal line 713, a read bit line 722, as shown in FIG. The power supply line 715 and the ground line 716 are connected. The memory cell 707 includes a first N-channel transistor 801a (also referred to as a first transistor), a second N-channel transistor 801b (also referred to as a second transistor), a latch circuit 802, a diode 803, and a third N A channel transistor 804 (also referred to as a third transistor) and a fourth N-channel transistor 805 (also referred to as a fourth transistor) are included. The latch circuit 802 includes a first inverter circuit 802a and a second inverter circuit 802b.

In FIG. 9, the first N-channel transistor 801 a functions as a switch that switches whether to input the potential of the write bit signal line 712 to the latch circuit 802 based on the potential of the write word line 708. The second N-channel transistor 801b functions as a switch that switches whether to input the potential of the write bit inversion signal line 713 to the latch circuit 802 based on the potential of the write word line 708. The diode 803 has a function of supplying a power supply potential from the power supply line 715 to the latch circuit 802 and preventing leakage of electric charge from the latch circuit.

The third N-channel transistor 804 holds the potential of one node of the latch circuit 802 connected to the gate terminal (the output terminal of the first inverter circuit 802a) with a gate capacitance, and is applied to the gate terminal. The function of switching the electrical connection between the read bit line 722 and the fourth N-channel transistor 805 in accordance with the potential to be applied. As an example, in FIG. 9, the third N-channel transistor 804 has a first terminal connected to the read bit line 722 and a second terminal connected to the second terminal of the fourth N-channel transistor 805. .

The fourth N-channel transistor 805 has a function of switching electrical connection between the third N-channel transistor 804 and the ground line 716 in accordance with the potential of the read word line 721 connected to the gate terminal. . As an example, in FIG. 9, the fourth N-channel transistor 805 has a first terminal connected to the ground line 716 and a second terminal connected to the second terminal of the third N-channel transistor 804.

FIGS. 10A and 10B are circuit diagrams for explaining the operation of FIG.

Note that in this embodiment mode, data “1” is written in the memory cell 707 in FIG. 7 and data “0” is written to the memory cell 107 in the first embodiment. This is the same as the description of data writing.

10A and 10B, the principle of obtaining a nonvolatile semiconductor memory device when the memory cell 707 is nonvolatile is the same as in FIGS. 3 to 5 of the first embodiment. It is the same as the description. That is, the second capacitor 204b described with reference to FIGS. 3 to 5 corresponds to the gate capacitance of the third N-channel transistor 804 in FIGS. 10A and 10B. Similarly to the second capacitor 204b described with reference to FIGS. 3 to 5, the diode 803 prevents charge leakage even when the power supply potential of the power supply line 715 is changed to the ground potential by turning off the power supply. Can hold the charge.

Thus, FIGS. 10A and 10B illustrate operations of separately holding data in the memory cell 707 and writing and reading data from the memory cell.

First, in FIG. 10A, in addition to the operations of the write bit signal line 712, the write bit inversion signal line 713, and the write word line 708, the memory cell when the data “0” held in the memory cell 707 is read. The state of the potential of each wiring and node connected to 707 and the on / off state of each transistor will be described. First, in the read bit line FIG. 10A, in order to read data “0” from the memory cell 707, an H potential (indicated as “1” in the figure) is input to the read word line 721. The N-channel transistor 805 is turned on, and the third N-channel transistor 804 and the ground line 716 are electrically connected. Note that when the read word line 721 is not selected, the ground potential state (hereinafter referred to as “L potential” and also referred to as “0” in the figure) is obtained.

When data “0” is held in the memory cell 707, the potential of the node 1001 of the latch circuit 802 connected to the gate terminal of the third N-channel transistor 804 is H potential. Therefore, when data “0” is held in the memory cell 707, the third N-channel transistor 804 is turned on, and the fourth N-channel transistor 805 and the read word line 721 are electrically connected. Is done.

The read bit line 722 is precharged in order to read data, and the potential of the read bit line 722 is high. Note that the precharge referred to here means that the wiring is previously set at the H potential in order to read data. When data “0” is held in the memory cell 707, as described above, the third N-channel transistor 804 and the fourth N-channel transistor 805 are in an on state. The charge moves from the line 722 to the ground line 716, and the read bit line 722 becomes L potential. The write / read circuit 702 connected to the read bit line 722 can read that the data held in the selected memory cell is “0” when the potential of the read bit line 722 becomes the L potential.

Next, in FIG. 10B, in addition to the operations of the write bit signal line 712, the write bit inversion signal line 713, and the write word line 708, the data “1” held in the memory cell 707 is read. A state of potentials of wirings and nodes connected to the memory cell 707 and on / off of each transistor will be described. First, in the read bit line FIG. 10B, in order to read data “1” from the memory cell 707, when the H potential is input to the read word line 721, the fourth N-channel transistor 805 is turned on, The third N-channel transistor 804 and the ground line 716 are electrically connected. Note that when the read word line 721 is not selected, the ground potential is obtained.

When data “1” is held in the memory cell 707, the potential of the node 1001 of the latch circuit 802 connected to the gate terminal of the third N-channel transistor 804 becomes the L potential. Therefore, when data “1” is held in the memory cell 707, the third N-channel transistor 804 is turned off, and the fourth N-channel transistor 805 and the read bit line 722 are electrically connected. Not.

The read bit line 722 is precharged in order to read data, and the potential of the read bit line 722 is high. When data “1” is held in the memory cell 707, as described above, the fourth N-channel transistor 805 is on, but the third N-channel transistor 804 is off. In this state, the charge does not move from the read bit line 722 to the ground line 716, and the read bit line 722 remains at the H potential as in the precharge. The write / read circuit 702 connected to the read bit line 722 can read that the data held in the selected memory cell is “1” when the potential of the read bit line 722 becomes the H potential.

Note that the third N-channel transistor 804 and the fourth N-channel transistor 805 described with reference to FIGS. 9 and 10 indicate that the data held in the memory cell is “1” or “0”. It only has to be connected so that it can be read with a line. FIG. 11 shows a configuration different from the circuit diagram of the memory cell described in FIG. In the circuit diagram of the memory cell shown in FIG. 11, the difference from FIG. 9 is that the read word line 721 is connected to the gate terminal of the third N-channel transistor 804 and the gate terminal of the fourth N-channel transistor 805 is connected. The node 1001 of the latch circuit 802 is connected. Also in the memory cell shown in FIG. 11, in the case where both the third N-channel transistor 804 and the fourth N-channel transistor 805 are turned on, as in the circuit diagram of the memory cell of FIG. 9 described in FIG. By reading the change in potential of the read bit line 722, data in the memory cell can be read.

Note that although a structure in which the diode 803 is provided for each memory cell is described in this embodiment, the present invention is not limited to this. The diode may be provided for each power supply line. By adopting a structure in which a diode is provided for each power supply line, it is possible to reduce the size of the memory cell and to make each memory cell non-volatile.

Note that the memory cell of the semiconductor memory device described in this embodiment is powered off as described in Embodiment 1 due to the diode included in the memory cell and the gate capacitance of the third N-channel transistor 804. Data can be retained even in a state. If the memory cell holds either data “1” or data “0”, it is held in one of the gate capacitors of the third N-channel transistor 804 when the power supply potential is supplied again from the power supply line. Based on the charge, the memory cell can continue to hold data again.

Further, in the memory cell of the semiconductor memory device described in this embodiment, as in the configuration of the memory cell described in Embodiment 1, the power supply potential from the power supply line supplied to the latch circuit is not constantly supplied. Data can be retained. Therefore, in the memory cell of the semiconductor memory device described in this embodiment, power supply can be reduced because data power can be supplied every certain period in order to hold data. In addition, since a wiring for reading data from the memory cell and writing data to the memory cell can be separately provided, a semiconductor memory device capable of performing reading and writing of data more reliably and at high speed Can be obtained.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 3)

In this embodiment, a structure of a nonvolatile semiconductor memory device which is different from the above embodiment will be described with reference to a block diagram, a circuit diagram, and the like. In the semiconductor memory device described in this embodiment, in addition to the effects described in Embodiments 1 and 2, data is read from a memory cell by using a plurality of wirings. A configuration of a semiconductor memory device capable of performing reading at high speed will be described in detail.

FIG. 12 is a block diagram of a nonvolatile semiconductor memory device described in this embodiment. A semiconductor memory device 1200 illustrated in FIG. 12 includes a decoder 1201, a write / read circuit 1202, and a memory cell array 1203. The decoder 1201 is connected to the first write address signal line 1204, the first read address signal line 1205, the second read address signal line 1206, the write enable signal line 1207, and the read enable signal line 1225. . The decoder 1201 is connected to a plurality of memory cells 1208 via a write word line 1209, a first read word line 1210, and a second read word line 1211. The write / read circuit 1202 includes a write enable signal line 1207, a read enable signal line 1225, a second write address signal line 1212, a third read address signal line 1213, a fourth read address signal line 1214, The input data signal line 1215, the first output data signal line 1216, and the second output data signal line 1217 are connected. The write / read circuit 1202 is connected to the plurality of memory cells 1208, the write bit signal line 1218, the write bit inverted signal line 1219, the first read bit line 1220, and the second read bit line 1221. In the semiconductor memory device 1200, a plurality of memory cells include a power supply potential (also referred to as an H potential or a high potential power supply; also referred to as “1” in the drawing) and a ground potential (also referred to as an L potential or a low potential power supply). In addition, it has a first power supply control circuit 1222a and a second power supply control circuit 1222b for supplying "." The first power supply control circuit 1222a and the second power supply control circuit 1222b and the plurality of memory cells 1208 include a power supply line 1223 for inputting a power supply potential to the memory cell 1208 and a ground line 1224 for inputting a ground potential. Connected through.

Note that in this embodiment mode, a write word line refers to a word line for writing data in a memory cell. The read word line refers to a word line for reading data from a memory cell. The write bit line and the write bit inversion signal line are a bit line and a bit inversion signal line for writing data in the memory cell. The read bit line refers to a bit line for reading data from a memory cell.

Note that in this embodiment mode, the first power supply control circuit 1222a and the second power supply control circuit 1222b are arranged in the semiconductor memory device 1200, but any one of them may be used. As shown in FIG. 12, a configuration in which a power supply potential and a ground potential are supplied from both sides of the memory cell array 1203 can supply a desired potential to a plurality of memory cells more reliably.

Note that the semiconductor memory device shown in FIG. 12 is different from the semiconductor memory device shown in FIG. 7 of Embodiment 2 in that the first read word is used as a wiring for reading data from the memory cell. The line 1210, the second read word line 1211, the first read bit line 1220, and the second read bit line 1221 are used. By providing a plurality of wirings for reading data, a semiconductor memory device capable of reading data from memory cells at high speed can be obtained.

In FIG. 12, a memory cell 1208 can hold a 1-bit value. The memory cell array 1203 has as many memory cells 1208 as (number of bits) × (number of lines).

The write / read circuit 1202 writes data input from the input data signal line 1215 from the outside of the semiconductor memory device 1200 to each memory cell 1208 of the memory cell array 1203 and reads data from each memory cell 1208 of the memory cell array 1203 to read data. Processing for transmitting data to the outside of the memory is performed by one output data signal line 1216 and a second output data signal line 1217.

The decoder 1201 receives a write word line 1209 from the outside of the semiconductor memory device 1200 in accordance with addresses input from the first write address signal line 1204, the first read address signal line 1205, and the second read address signal line 1206. A signal is output to the first read word line 1210 or the second read word line 1211.

The decoder 1201 outputs a signal to the write word line 1209, the first read word line 1210, or the second read word line 1211 to control reading or writing of data in each memory cell 1208. For example, at the time of writing, one of the write word lines 1209 is in a high potential state (hereinafter referred to as “H potential”. Also referred to as “1” in the drawing), and at the time of reading, the first read word line 1210 and the first read word line 1210 One of the two read word lines 1211 becomes H potential. Note that when the write word line 1209, the first read word line 1210, and the second read word line 1211 are not selected, the ground potential state (hereinafter referred to as “L potential”. Also denoted as “0” in the figure). ).

The write bit signal line 1218 and the write bit inversion signal line 1219 are write bit lines, respectively. At the time of writing, external data is input to the write bit signal line 1218 and the write bit inverted signal line 1219. The first read bit line 1220 and the second read bit line 1221 are read bit lines. At the time of reading, the potential of the first read bit line 1220 and the second read bit line 1221 which change based on the data of the memory cell selected by the address is read after being precharged by the write / read circuit 1202.

Such a semiconductor memory device 1200 can store information corresponding to the number of bits and the number of lines.

Further, in the memory cell shown in this embodiment, as in the second embodiment, a circuit diagram as shown in FIG. 8B in which the inverter circuit is abbreviated is shown.

Next, a circuit diagram of the memory cell 1208 in FIG. 12 will be described with reference to FIG. As shown in FIG. 12, the memory cell 1208 of this embodiment mode shown in FIG. 13 includes a write word line 1209, a first read word line 1210, a second read word line 1211, a write bit signal line 1218, The write bit inversion signal line 1219, the first read bit line 1220, the second read bit line 1221, the power supply line 1223, and the ground line 1224 are connected. The memory cell 1208 includes a first N-channel transistor 1301a (also referred to as a first transistor), a second N-channel transistor 1301b (also referred to as a second transistor), a latch circuit 1302, a diode 1303, and a third N A channel transistor 1304 (also referred to as a third transistor), a fourth N-channel transistor 1305 (also referred to as a fourth transistor), a fifth N-channel transistor 1306 (also referred to as a fifth transistor), a sixth transistor An n-channel transistor 1307 (also referred to as a sixth transistor). The latch circuit 1302 includes a first inverter circuit 1302a and a second inverter circuit 1302b.

In FIG. 13, the first N-channel transistor 1301 a functions as a switch for switching whether to input the potential of the write bit signal line 1218 to the latch circuit 1302 based on the potential of the write word line 1209. The second N-channel transistor 1301 b functions as a switch for switching whether to input the potential of the write bit inversion signal line 1219 to the latch circuit 1302 based on the potential of the write word line 1209. The diode 1303 has a function of supplying a power supply potential from the power supply line 1223 to the latch circuit 1302 and preventing leakage of electric charge from the latch circuit 1302.

The third N-channel transistor 1304 holds the potential of one node of the latch circuit 1302 connected to the gate terminal (the output terminal of the first inverter circuit 1302a) with a gate capacitor, and is applied to the gate terminal. And a function of switching electrical connection between the first read bit line 1220 and the fourth N-channel transistor 1305 in accordance with the potential. As an example, in FIG. 13, the third N-channel transistor 1304 has a first terminal connected to the first read bit line 1220 and a second terminal connected to the second terminal of the fourth N-channel transistor 1305. Has been.

The fourth N-channel transistor 1305 switches the electrical connection between the third N-channel transistor 1304 and the ground line 1224 in accordance with the potential of the first read word line 1210 connected to the gate terminal. It has a function. As an example, in FIG. 13, the fourth N-channel transistor 1305 has a first terminal connected to the ground line 1224 and a second terminal connected to the second terminal of the third N-channel transistor 1304.

The fifth N-channel transistor 1306 holds the potential of the other node of the latch circuit 1302 connected to the gate terminal (the output terminal of the first inverter circuit 1302b) with a gate capacitance, and is applied to the gate terminal. A function of switching electrical connection between the second read bit line 1221 and the sixth N-channel transistor 1307 in accordance with the potential to be applied. As an example, in FIG. 13, the fifth N-channel transistor 1306 has a first terminal connected to the second read bit line 1221 and a second terminal connected to the second terminal of the sixth N-channel transistor 1307. Has been.

The sixth N-channel transistor 1307 switches electrical connection between the fifth N-channel transistor 1306 and the ground line 1224 in accordance with the potential of the second read word line 1211 connected to the gate terminal. It has a function. As an example, in FIG. 13, the sixth N-channel transistor 1307 has a first terminal connected to the ground line 1224 and a second terminal connected to the second terminal of the fifth N-channel transistor 1306.

Note that in this embodiment mode, data “1” is written in the memory cell 1208 in FIG. 12 and data “0” is written in the memory cell 107 in the first embodiment. This is the same as the description of writing data to the.

Note that in FIG. 13, the principle that a nonvolatile semiconductor memory device is obtained when the memory cell 1308 is nonvolatile is the same as that described in FIGS. 3 to 5 of Embodiment Mode 1. That is, the second capacitor 204b described in FIGS. 3 to 5 corresponds to the gate capacitor of the third N-channel transistor 1304 in FIG. 13, and the first capacitor 204a described in FIGS. Corresponds to the fifth N-channel transistor 1306 in FIG. As in the case of the first capacitor element 204a and the second capacitor element 204b described with reference to FIGS. 3 to 5, the diode is also applied when the power supply potential of the power supply line 1223 is changed to the ground potential by turning off the power supply. 1303 can prevent electric charge leakage and hold electric charge.

Therefore, in this embodiment, an operation of simultaneously reading a plurality of data from the memory cell 1308 separately using the first read bit line 1220 and the second read bit line 1221 which are different read bit lines is illustrated in FIG. A description will be given using (B).

14A shows the first memory cell 1308a and the second memory cell 1308 connected to the same write word line, first read word line, and second read word line in the memory cell 1308 described in FIG. The memory cell 1308b is shown. In FIG. 14A, data reading from the first memory cell 1308a and the second memory cell 1308b is similar to the data reading from the memory cell described in FIG. 10 of Embodiment 2 above. Description is omitted.

The memory cell described in this embodiment is connected to the first read word line and the second read word line, and reads data from the first read bit line and the second read bit line. . Thus, an example of reading data from the first memory cell 1308a and the second memory cell 1308b is described with reference to FIG. Both the first memory cell 1308a and the second memory cell 1308b illustrated in FIG. 14B are connected to the first read bit line 1220 and the second read bit line 1221. In FIG. 14B, data held in the first memory cell 1308a and the second memory cell 1308b is transmitted from the first read bit line 1220 and the second read bit line 1221 through the analog switch 1401. Read out. Therefore, the data in the first memory cell 1308a is read from the first read bit line 1220 by controlling the analog switch 1401, and at the same time, the data in the second memory cell 1308b is controlled by the analog switch 1401. 2 read bit lines 1221. Therefore, data can be read from two memory cells at the same time, so that data can be read at high speed.

Note that the third N-channel transistor 1304 and the fourth N-channel transistor 1305, and the fifth N-channel transistor 1305 and the sixth N-channel transistor 1306 described with reference to FIGS. It is only necessary that the first read bit line 1220 and the second read bit line 1221 be connected so that the data held in can be read as “1” or “0”. FIG. 15 shows a structure different from the circuit diagram of the memory cell described in FIG. 15 differs from the circuit diagram of the memory cell in FIG. 15 in that the first read word line 1210 is connected to the gate terminal of the third N-channel transistor 1304, and the fourth N-channel transistor 1305 has a gate terminal. The output terminal of the first inverter circuit 1302a is connected to the gate terminal, the second read word line 1211 is connected to the gate terminal of the fifth N-channel transistor 1306, and the gate terminal of the sixth N-channel transistor 1307. Is connected to the output terminal of the second inverter circuit 1302b. In the memory cell shown in FIG. 15 as well, in the case where both the third N-channel transistor 1304 and the fourth N-channel transistor 1305 are turned on, as in the circuit diagram of the memory cell shown in FIG. Reading the potential change of the first read bit line 1220 and the potential of the second read bit line 1221 when the fifth N-channel transistor 1306 and the sixth N-channel transistor 1307 are both turned on. By reading the change, the data in the memory cell can be read.

Note that although a structure in which the diode 1303 is provided for each memory cell is described in this embodiment, the present invention is not limited to this. The diode may be provided for each power supply line. By adopting a structure in which a diode is provided for each power supply line, it is possible to reduce the size of the memory cell and to make each memory cell non-volatile.

Note that the memory cell of the semiconductor memory device described in this embodiment mode includes the diodes included in the memory cell, the gate capacitance of the third N-channel transistor 1304, and the gate capacitance of the fifth N-channel transistor. As described in 1, data can be retained even when the power is turned off. If the memory cell holds either data “1” or data “0”, it is held in one of the gate capacitors of the third N-channel transistor 804 when the power supply potential is supplied again from the power supply line. Based on the charge, the memory cell can continue to hold data again.

Further, in the memory cell of the semiconductor memory device described in this embodiment, as in the configuration of the memory cell described in Embodiment 1, the power supply potential from the power supply line supplied to the latch circuit is not constantly supplied. Data can be retained. Therefore, in the memory cell of the semiconductor memory device described in this embodiment, power supply can be reduced because data power can be supplied every certain period in order to hold data. In addition, since a wiring for reading data from the memory cell and writing data to the memory cell can be separately provided, a semiconductor memory device capable of performing reading and writing of data more reliably and at high speed Can be obtained. Furthermore, by reading data from the memory cell using a plurality of wirings, a semiconductor memory device that can read data at high speed can be obtained.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 4)

The semiconductor memory device of the present invention can be applied to a central processing unit (CPU). In this embodiment mode, a structure of a CPU on which the semiconductor memory device of the present invention is mounted will be described. A simple configuration of the CPU is shown in FIG.

The CPU includes a D $ block (data cache: hereinafter D $ 1601), an I $ block (instruction cache: hereinafter I $ 1602), a DU block (data unit: hereinafter DU1603), an ALU block (Arithmatic Logic Unit, an arithmetic logic circuit) : ALU 1604), PC block (program counter: PC 1605), and IO block (InOut: IO 1606).

The D $ 1601 has a function of temporarily holding data at the recently accessed address so that the address data can be accessed at high speed. The I $ 1602 has a function of temporarily holding an instruction at a recently accessed address so that the instruction at the address can be accessed at high speed. The DU 1603 has a function of determining whether to access the D $ 1601 or the IO when a store or load instruction is executed. The ALU 1604 is an arithmetic logic operation circuit and has a function of performing four arithmetic operations, comparison operations, logical operations, and the like. The PC 1605 has a function of holding the address of the instruction currently being executed and fetching the next instruction after the end of the execution. Further, it has a function of determining whether to access the I $ 1602 or the IO1606 when fetching the next instruction. The IO 1606 has a function of receiving data from the DU 1603 and the PC 1605 and transmitting / receiving data to / from the outside. Each relationship will be described below.

When the PC 1605 fetches an instruction, it first accesses the I $ 1602, and if there is no instruction at an address corresponding to the I $ 1602, the IO 1606 is accessed. The instruction thus obtained is stored in the I $ 1602 and executed. If the instruction to be executed is an arithmetic logic operation, the ALU 1604 performs the operation. When the instruction to be executed is a store or load instruction, the DU 1603 performs an operation. At this time, the DU 1603 first accesses the D $ 1601, and accesses the IO 1606 when there is no data at the corresponding address in the D $ 1601.

In such a CPU, the semiconductor memory device of the present invention can be applied to registers existing in D $ 1601, I $ 1602, and ALU1604. As a result, a CPU having a nonvolatile semiconductor memory circuit can be provided, and data can be retained even when the power is turned off, so that power consumption can be reduced. Further, by using the semiconductor memory device described in Embodiment 3, a CPU including a nonvolatile semiconductor memory device that can read data at high speed can be used.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 5)

In this embodiment, an RFID tag including the semiconductor memory device described in the above embodiment (hereinafter referred to as a semiconductor device; also referred to as an ID chip, an IC tag, an ID tag, an RF tag, a wireless tag, an electronic tag, or a transponder) The configuration of will be described.

A structure of the semiconductor device is described with reference to FIGS. FIG. 17 is a block diagram in the semiconductor device. A semiconductor device 1700 includes an antenna 1702 and a semiconductor integrated circuit 1701. The semiconductor integrated circuit 1701 includes a transmission / reception circuit 1703, a power supply circuit 1704, a control circuit 1705, and a memory element 1706.

Next, operation of the semiconductor device will be described with reference to FIGS. As shown in FIG. 18, from an antenna unit 1721 connected to a control terminal 1722 via a wireless communication device (hereinafter referred to as a communication device 1720. Also referred to as a reader / writer, a reader / writer, a controller, an interrogator, or an interrogator). A radio signal with a modulated carrier wave is transmitted. Here, the radio signal includes a command from the communication device 1720 to the semiconductor device 1700.

In FIG. 17, an antenna 1702 included in the semiconductor device 1700 receives the wireless signal. The received wireless signal is sent to each circuit block via a transmission / reception circuit 1703 connected to the antenna 1702. A power supply circuit 1704, a control circuit 1705, and a memory element 1706 are connected to the transmission / reception circuit 1703.

A first high power supply potential (VDD1) is generated by the rectifying function of the transmission / reception circuit 1703, and a second high power supply potential (VDD2) is generated from the power supply circuit 1704. In the present embodiment, of the two generated high power supply potentials, the second high power supply potential VDD2 is supplied to each circuit block of the semiconductor integrated circuit 1701. Note that the low power supply potential (VSS) is common in this embodiment. In FIG. 17, the power supply circuit 1704 is formed of a constant voltage circuit.

The rectification function of the transmission / reception circuit 1703 and the operation of the power supply circuit 1704 will be briefly described. For example, a case where the rectifying function of the transmission / reception circuit 1703 is configured by one rectifier circuit and the power supply circuit 1704 is configured by a constant voltage circuit is considered. Here, a diode and a capacitor can be used as a rectifier circuit that performs a rectification function. The wireless signal transmitted to the transmission / reception circuit 1703 via the antenna 1702 is input to the rectifier circuit and rectified. Then, smoothing is performed by the capacitive element of the rectifier circuit, and the first high power supply potential (VDD1) is generated. The generated VDD1 passes through a constant voltage circuit and becomes a stable voltage (second high power supply potential, VDD2) equal to or lower than the input. The output voltage VDD2 of the constant voltage circuit is supplied to each circuit block as a power source. The generated VDD1 may be supplied to each circuit block as a power source. Furthermore, both VDD1 and VDD2 may be supplied to each circuit block. It is desirable to use VDD1 or VDD2 properly depending on the operating conditions and applications of each circuit block.

In the semiconductor device shown in FIG. 17, the constant voltage circuit has a function of keeping the DC voltage substantially constant, and any circuit can be used as long as the circuit can keep the DC voltage substantially constant by voltage, current, or both. But you can.

Further, a demodulated signal 1709 is generated by the demodulating function of the transmission / reception circuit 1703. The generated demodulated signal 1709 is supplied to each circuit block. The transmission / reception circuit 1703 and the control circuit 1705 are connected, and the demodulated signal 1709 generated by the transmission / reception circuit 1703 is supplied to the control circuit 1705.

The control circuit 1705 has a reset circuit. A reset signal is generated in the reset circuit. The reset signal is a signal for initializing the semiconductor device 1700.

The control circuit 1705 includes a clock generation circuit. The clock generation circuit generates a basic clock signal based on the demodulated signal 1709 sent via the transmission / reception circuit 1703. The basic clock signal generated by the clock generation circuit is used in a circuit in the control circuit.

Further, the control circuit 1705 extracts a command sent from the communication device 1720 to the semiconductor device 1700 from the demodulated signal 1709 sent via the transmission / reception circuit 1703, and determines what command has been sent. Determine. The control circuit 1705 also has a role of controlling the memory element 1706.

In this manner, what command is sent from the communication device 1720 is determined, and the memory element 1706 is operated according to the determined command. Then, a signal including data stored in the memory element 1706 or a signal including stored data such as a written identification number is output. Alternatively, information transmitted from the communication device 1720 is stored in the storage element 1706.

Here, the memory element 1706 can use the nonvolatile memory element 1706 described in the above embodiment and can hold data even when the power is turned off, so that power consumption can be reduced. Further, by using the semiconductor memory device described in Embodiment 3, a CPU including a nonvolatile semiconductor memory device that can read data at high speed can be used.

The control circuit 1705 also has a role of changing a signal including unique data such as an identification number stored or written in the storage element 1706 into a signal encoded by an encoding method compliant with a standard such as ISO. Then, according to the encoded signal 1710, the transmission / reception circuit 1703 modulates the signal transmitted to the antenna 1702.

The modulated signal is received by the antenna unit 1721 connected to the communication device 1720. The received signal is analyzed by the communication device 1720 and unique data such as an identification number of the semiconductor device 1700 can be recognized.

In this embodiment, an example in which communication between the semiconductor device 1700 and the communication device 1720 is performed by modulating a carrier wave is described. The carrier wave varies depending on the standard such as 125 KHz, 13.56 MHz, and 950 MHz. There are various modulation methods such as amplitude modulation, frequency modulation, and phase modulation depending on the standard. Any modulation method may be used as long as the modulation method conforms to the standard.

The signal transmission method can be classified into various types such as an electromagnetic coupling method, an electromagnetic induction method, and a microwave method depending on the wavelength of the carrier wave. Note that when a radio signal is transmitted and received between a semiconductor device and a communication device over a long distance, it is desirable to select a microwave method.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 6)

In this embodiment, an example of manufacturing a transistor included in the semiconductor memory device described in the above embodiment will be described. In this embodiment mode, a mode in which a transistor is manufactured using a semiconductor film formed over an insulating substrate and a semiconductor memory device is provided will be described.

  A separation layer 1902 is formed over one surface of the substrate 1901, and then an insulating film 1903 and an amorphous semiconductor film 1904 (for example, a film containing amorphous silicon) which serve as a base are formed (FIG. 19A). The separation layer 1902, the insulating film 1903, and the amorphous semiconductor film 1904 can be formed successively. The continuous formation prevents exposure to impurities since it is not exposed to the atmosphere.

  As the substrate 1901, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like is preferably used. If such a substrate is used, there is no significant limitation on the area and shape thereof. For example, if a substrate having a side of 1 meter or more and a rectangular shape is used, productivity can be significantly improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate. Therefore, even if the integrated circuit portion and the antenna are formed larger than the silicon substrate, cost reduction can be realized.

  Note that although the separation layer 1902 is provided over the entire surface of the substrate 1901 in this step, the separation layer 1902 is selectively provided by a photolithography method after being provided over the entire surface of the substrate 1901 as needed. Also good. In addition, the peeling layer 1902 is formed so as to be in contact with the substrate 1901, but if necessary, a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy) (x> y) film, or a nitriding film An insulating film such as a silicon (SiNx) film or a silicon nitride oxide (SiNxOy) (x> y) film may be formed, and the peeling layer 1902 may be formed in contact with the insulating film.

For the separation layer 1902, a metal film, a stacked structure of a metal film and a metal oxide film, or the like can be used. As the metal film, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), A single layer or a stack of films made of an element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or an alloy material or compound material containing the element as a main component To form. In addition, these materials can be formed using various CVD methods such as a sputtering method and a plasma CVD method. A stacked structure of a metal film and a metal oxide film, after forming a metal film described above, a plasma treatment under an oxygen atmosphere or an N _{2 O} atmosphere, by performing heat treatment in an oxygen atmosphere or an N _{2 O} atmosphere The oxide or oxynitride of the metal film can be provided on the surface of the metal film. In addition, after forming the metal film, the surface of the metal film is treated with a solution having strong oxidizing power such as ozone water, whereby the metal film oxide or oxynitride can be provided on the surface of the metal film.

  The insulating film 1903 is formed as a single layer or a stacked layer using a silicon oxide or a silicon nitride film by a sputtering method, a plasma CVD method, or the like. In the case where the base insulating film has a two-layer structure, for example, a silicon nitride oxide film may be formed as the first layer and a silicon oxynitride film may be formed as the second layer. When the base insulating film has a three-layer structure, a silicon oxide film is formed as the first insulating film, a silicon nitride oxide film is formed as the second insulating film, and oxynitriding is performed as the third insulating film. A silicon film is preferably formed. Alternatively, a silicon oxynitride film may be formed as the first insulating film, a silicon nitride oxide film may be formed as the second insulating film, and a silicon oxynitride film may be formed as the third insulating film. The insulating film serving as a base functions as a blocking film that prevents intrusion of impurities from the substrate 1901.

  The semiconductor film 1904 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the semiconductor film 1904, for example, an amorphous silicon film may be formed.

  Next, crystallization is performed by irradiating the amorphous semiconductor film 1904 with laser light. Note that the amorphous semiconductor film 1904 is crystallized by a combination of laser light irradiation, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. May be performed. After that, the obtained crystalline semiconductor film is etched into a desired shape to form semiconductor films 1904a to 1904d, and a gate insulating film 1905 is formed so as to cover the semiconductor films 1904a to 1904d (FIG. 19B). ).

  An example of a manufacturing process of the semiconductor films 1904a to 1904d will be briefly described below. First, an amorphous semiconductor film (for example, an amorphous silicon film) with a thickness of 50 to 60 nm is formed using a plasma CVD method. . Next, after a solution containing nickel, which is a metal element that promotes crystallization, is held on the amorphous semiconductor film, the amorphous semiconductor film is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor film. After that, the semiconductor films 1904a to 1904d are formed by irradiating laser light from a laser oscillator and using a photolithography method. Note that the amorphous semiconductor film may be crystallized only by laser light irradiation without performing thermal crystallization using a metal element that promotes crystallization.

As the laser oscillator, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as Ar laser, Kr laser, or excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( Ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants Lasers oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of these fundamental waves, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec. Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta as a medium, a laser, Ar ion laser, or Ti: sapphire laser with one or more added as a medium should be continuously oscillated It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or higher, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  Next, a gate insulating film 1905 is formed to cover the semiconductor films 1904a to 1904d. The gate insulating film 1905 is formed by a single layer or a stack of films containing silicon oxide or silicon nitride by a CVD method, a sputtering method, or the like. Specifically, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed as a single layer or a stacked layer.

Alternatively, the gate insulating film 1905 may be formed by performing high-density plasma treatment on the amorphous semiconductor films 1904a to 1904d and oxidizing or nitriding the surface. For example, the plasma treatment is performed by introducing a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide (NO ₂ ), ammonia, nitrogen, or hydrogen. When excitation of plasma in this case is performed by introducing microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

  By such treatment using high-density plasma, an insulating film with a thickness of 1 to 20 nm, typically 5 to 10 nm, is formed over the semiconductor film. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. Such high-density plasma treatment directly oxidizes (or nitrides) a semiconductor film (crystalline silicon or polycrystalline silicon), so that the thickness of the formed insulating film ideally has extremely small variation. can do. In addition, since oxidation is not strengthened even at the crystal grain boundaries of crystalline silicon, a very favorable state is obtained. That is, the surface of the semiconductor film is solid-phase oxidized by the high-density plasma treatment shown here, thereby forming an insulating film with good uniformity and low interface state density without causing an abnormal oxidation reaction at the grain boundaries. can do.

  As the gate insulating film 1905, only an insulating film formed by high-density plasma treatment may be used. In addition, an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride is formed by a CVD method using plasma or thermal reaction. May be deposited and laminated. In any case, a transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

  In addition, the semiconductor films 1904a to 1904d obtained by scanning and crystallizing in one direction while irradiating the semiconductor film with continuous wave laser light or laser light oscillating at a frequency of 10 MHz or more are scanned with the laser light. The crystal grows in the direction. By arranging the transistors in accordance with the scanning direction in the channel length direction (the direction in which carriers flow when a channel formation region is formed) and combining the gate insulating layer, characteristic variation is small and field effect mobility is reduced. A high thin film transistor (TFT) can be obtained.

  Next, a first conductive film and a second conductive film are stacked over the gate insulating film 1905. Here, the first conductive film is formed with a thickness of 20 to 100 nm by a plasma CVD method, a sputtering method, or the like. The second conductive film is formed with a thickness of 100 to 400 nm. The first conductive film and the second conductive film include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive film and the second conductive film include a tantalum nitride film and a tungsten film, a tungsten nitride film and a tungsten film, a molybdenum nitride film and a molybdenum film, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the first conductive film and the second conductive film are formed. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.

  Next, a resist mask is formed by photolithography, and an etching process for forming a gate electrode and a gate wiring is performed, so that a gate electrode 1907 is formed over the semiconductor films 1904a to 1904d.

  Next, a resist mask is formed by photolithography, and an impurity element imparting n-type conductivity is added to the semiconductor films 1904a to 1904d at a low concentration by ion doping or ion implantation. As the impurity element imparting n-type conductivity, an element belonging to Group 15 may be used. For example, phosphorus (P) or arsenic (As) is used.

  Next, an insulating film is formed so as to cover the gate insulating film 1905 and the gate electrode 1907. The insulating film is formed by a single layer or a stacked layer of a film containing an inorganic material such as silicon, silicon oxide or silicon nitride, or a film containing an organic material such as an organic resin by plasma CVD or sputtering. To do. Next, the insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that an insulating film 1908 (also referred to as a sidewall) in contact with the side surface of the gate electrode 1907 is formed. The insulating film 1908 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

  Next, an impurity element imparting n-type conductivity is added to the semiconductor films 1904a to 1904d using a resist mask formed by photolithography, the gate electrode 1907, and the insulating film 1908 as masks, so that a channel formation region 1906a is added. Then, a first impurity region 1906b and a second impurity region 1906c are formed (FIG. 19C). The first impurity region 1906b functions as a source region or a drain region of the thin film transistor, and the second impurity region 1906c functions as an LDD region. The concentration of the impurity element contained in the second impurity region 1906c is lower than the concentration of the impurity element contained in the first impurity region 1906b.

  Next, an insulating film is formed as a single layer or a stacked layer so as to cover the gate electrode 1907, the insulating film 1908, and the like, and a conductive film 1931 functioning as a source electrode or a drain electrode of the thin film transistor is formed over the insulating film. As a result, an element layer 1951 including thin film transistors 1930a to 1930d is obtained (FIG. 19D). Note that an element such as a thin film transistor may be provided over the entire surface of the region 1950 or may be provided in a portion excluding a part of the region 1950 (for example, the central portion).

  Insulating film is formed by CVD, sputtering, SOG, droplet discharge, screen printing, etc., inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, etc. A single layer or a stacked layer is formed using an organic material or a siloxane material. Here, an example in which an insulating film is provided in two layers is shown; a silicon nitride oxide film may be formed as the first insulating film 1909 and a silicon oxynitride film may be formed as the second insulating film 1910. it can.

  Note that before the insulating films 1909 and 1910 are formed, or after one or both of the insulating films 1909 and 1910 are formed, the crystallinity of the semiconductor films 1904a to 1904d is recovered and the activity of impurity elements added to the semiconductor films is increased. Heat treatment for the purpose of hydrogenation of the semiconductor film is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  The conductive film 1931 is formed by etching the insulating films 1909 and 1910 by a photolithography method to form a contact hole exposing the first impurity region 1906b, and then forming the conductive film so as to fill the contact hole. The conductive film is formed by selective etching. Note that silicide may be formed on the surfaces of the semiconductor films 1904a to 1904d exposed in the contact holes before the conductive film is formed.

  The conductive film 1931 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), CVD, sputtering, or the like. An element selected from copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy containing these elements as a main component The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 1931 has, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. Adopt it. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive film 1931 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

  Next, an insulating film 1911 is formed so as to cover the conductive film 1931 (FIG. 20A). The insulating film 1911 is formed as a single layer or a stacked layer using an inorganic material or an organic material by a CVD method, a sputtering method, an SOG method, a droplet discharge method, a screen printing method, or the like. The insulating film 1911 is preferably formed with a thickness of 0.75 μm to 3 μm.

  Next, a conductive film 1912 functioning as an antenna is selectively formed over the surface of the insulating film 1911 (FIG. 20B).

  The conductive film 1912 is formed by etching the insulating film 1911 by a photolithography method to form a contact hole exposing the conductive film 1931, and then forming the conductive film so as to fill the contact hole. It is formed by etching.

  The conductive film 1912 may be formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a plating process, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when the conductive film 1912 functioning as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle diameter of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. The conductive particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. By using the screen printing method, the process can be simplified and the cost can be reduced.

  Next, an insulating film 1913 is formed so as to cover the conductive film 1912 functioning as an antenna (FIG. 21A).

  The insulating film 1913 is formed by a CVD method, a sputtering method, an SOG method, a droplet discharge method, a screen printing method, or the like using an inorganic material such as a silicon oxide or a silicon nitride (e.g., a silicon oxide film, a silicon oxynitride film, (A silicon nitride film, a silicon nitride oxide film, etc.), polyimide, polyamide, benzocyclobutene, acrylic, an organic material such as epoxy, a siloxane material, or the like.

  Next, the element formation layer including the thin film transistors 1930 a to 1930 d and the conductive film 1912 functioning as an antenna is peeled from the substrate 1901.

  First, an opening 1918 is formed by laser light irradiation (FIG. 21B). Subsequently, after one surface of the element formation layer (here, the surface of the insulating film 1917) is attached to the first sheet material 1920, the element formation layer is peeled from the substrate 1901 using physical force ( FIG. 22 (A)). As the first sheet material 1920, a hot melt film or the like can be used. Further, when the first sheet material 1920 is peeled later, a heat peeling tape whose adhesive strength is weakened by applying heat can be used.

  Note that elements such as the thin film transistors 1930a to 1930d can be prevented from being damaged by static electricity or the like by being wetted with an aqueous solution such as water or ozone water when peeling. In addition, cost reduction can be realized by reusing the substrate 1901 from which the element formation layer has been peeled.

  Next, a second sheet material 1921 is provided on the other surface of the element formation layer (a surface exposed by peeling from the substrate 1901) (FIG. 22B). The second sheet material 1921 can be attached to the other surface of the element formation layer by performing one or both of heat treatment and pressure treatment using a hot melt film or the like. In the case where a heat peeling tape is used as the first sheet material 1920, the heat can be peeled using the heat applied when the second sheet material 1921 is bonded.

  Next, a plurality of semiconductor devices can be obtained by selectively dividing the element formation layer provided over the second sheet material 1921 by dicing, scribing, laser cutting, or the like. By using a flexible substrate such as plastic as the second sheet material 1921, a flexible semiconductor device can be manufactured.

  Note that although this embodiment mode describes the case where a flexible semiconductor device is manufactured by forming an element such as a thin film transistor or an antenna over the substrate 1901 and then peeling the element from the substrate 1901, the present invention is not limited thereto. I can't. For example, a semiconductor device in which an element such as a thin film transistor or an antenna is provided over the substrate 1901 can be manufactured by applying the steps of FIGS. 22A and 19A without providing the separation layer 1902 over the substrate 1901. can do.

  Note that although an example in which the antenna is formed over the same substrate as the semiconductor element is described in this embodiment mode, the present invention is not limited to this structure. After forming the semiconductor element, a separately formed antenna may be electrically connected to the integrated circuit. In this case, the electrical connection between the antenna and the integrated circuit is performed by crimping with an anisotropic conductive film (ACF (Anisotropic Conductive Film)), an anisotropic conductive paste (ACP (Anisotropic Conductive Paste)), or the like. Can be connected to. In addition, it is also possible to perform connection using a conductive adhesive such as silver paste, copper paste, or carbon paste, solder bonding, or the like.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 7)

In this embodiment mode, a mode in which a single crystal semiconductor is used as a semiconductor film over an insulating substrate used for manufacturing a transistor of the semiconductor device in Embodiment Mode 6 will be described.

  Hereinafter, in this embodiment, a method for manufacturing an insulating substrate over which a single crystal semiconductor is formed (hereinafter referred to as an SOI (Silicon on Insulator) substrate) will be described.

  First, a semiconductor substrate 2001 is prepared (see FIGS. 23A and 25A). As the semiconductor substrate 2001, a commercially available semiconductor substrate may be used, and examples thereof include a silicon substrate, a germanium substrate, and a compound semiconductor substrate such as gallium arsenide and indium phosphide. As a commercially available silicon substrate, those having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), and a diameter of 12 inches (300 mm) are typical, and the shape is circular. Is almost. Further, the film thickness can be appropriately selected up to about 1.5 mm.

Next, ions 2004 accelerated by an electric field from the surface of the semiconductor substrate 2001 are implanted to a predetermined depth to form an ion doping layer 2003 (see FIGS. 23A and 25A). The ion 2004 is implanted in consideration of the film thickness of an SOI layer to be transferred later to the base substrate. Preferably, the thickness of the SOI layer is 5 nm to 500 nm, more preferably 10 nm to 200 nm. The accelerating voltage and the ion dose at the time of ion implantation are appropriately selected in consideration of the thickness of the SOI layer to be transferred. As the ions 2004, hydrogen, helium, or a halogen ion such as fluorine can be used. Note that as the ions 2004, it is preferable to implant an ion species including one atom or a plurality of identical atoms generated by plasma excitation of a source gas selected from hydrogen, helium, or a halogen element. When hydrogen ions are implanted, H ⁺ , H ₂ ⁺ , H ₃ ⁺ ions are included, and if the ratio of H ₃ ⁺ ions is increased, the ion implantation efficiency can be increased and the implantation time is shortened. This is preferable because it can be performed. Moreover, peeling can be easily performed by setting it as such a structure.

  Note that in order to form the ion doping layer 2003 at a predetermined depth, it may be necessary to implant ions 2004 under a high dose condition. At this time, the surface of the semiconductor substrate 2001 becomes rough depending on conditions. Therefore, a silicon nitride layer, a silicon nitride oxide layer, or the like may be provided as a protective layer with a thickness of 50 nm to 200 nm on the surface of the semiconductor substrate into which ions are implanted.

  Next, the bonding layer 2022 is formed over the semiconductor substrate 2001 (see FIGS. 23B and 25B). The bonding layer 2022 is formed on a surface where the semiconductor substrate 2001 forms a bond with the base substrate. The bonding layer 2022 formed here is preferably a silicon oxide layer formed by a chemical vapor deposition method using organosilane as a source gas as described above. In addition, a silicon oxide layer formed by a chemical vapor deposition method using silane as a source gas can be used. In film formation by a chemical vapor deposition method, a temperature at which degassing does not occur from the ion doping layer 2003 formed on the semiconductor substrate 2001 is applied. For example, a film forming temperature of 350 ° C. or lower is applied. Note that a heat treatment temperature higher than a deposition temperature by a chemical vapor deposition method is applied to heat treatment for peeling the SOI layer from a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate.

  Next, the semiconductor substrate 2001 is processed into a desired size and shape (see FIGS. 23C and 25C). Specifically, it is processed to a desired size. FIG. 25C illustrates an example in which a circular semiconductor substrate 2001 is divided to form a rectangular semiconductor substrate 2002. At this time, the bonding layer 2022 and the ion doping layer 2003 are also divided. That is, the semiconductor substrate 2002 having a desired size, the ion doping layer 2003 formed at a predetermined depth, and the bonding layer 2022 formed on the surface (bonding surface with the base substrate) is obtained.

  The semiconductor substrate 2002 is preferably divided in advance to have a desired semiconductor device size. The semiconductor substrate 2001 can be divided using a cutting device such as a dicer or a wire saw, laser cutting, plasma cutting, electron beam cutting, or any other cutting means.

  Note that the order of steps until the bonding layer is formed on the surface of the semiconductor substrate can be changed as appropriate. 23 and 25 show an example in which an ion doping layer is formed on a semiconductor substrate, a bonding layer is formed on the surface of the semiconductor substrate, and then the semiconductor substrate is processed to a desired size. On the other hand, for example, after processing a semiconductor substrate to a desired size, an ion doping layer can be formed on the semiconductor substrate of the desired size, and a bonding layer can be formed on the surface of the semiconductor substrate of the desired size. .

  Next, the base substrate 2010 and the semiconductor substrate 2002 are attached to each other. In FIG. 24A, the base substrate 2010 and the surface of the semiconductor substrate 2002 where the bonding layer 2022 is formed are in close contact, the base substrate 2010 and the bonding layer 2022 are bonded, and the base substrate 2010 and the semiconductor substrate 2002 are attached. An example of matching is shown. In addition, it is preferable that the surface (bonding surface) for forming the bond is sufficiently cleaned. A bond is formed by closely attaching the base substrate 2010 and the bonding layer 2022. In this bonding, van der Waals force acts, and by pressing the base substrate 2010 and the semiconductor substrate 2002, a strong bond by hydrogen bonding can be formed.

  Further, in order to form a favorable bond between the base substrate 2010 and the bonding layer 2022, the bonding surface may be activated. For example, one or both of the surfaces on which the junction is formed are irradiated with an atomic beam or an ion beam. When an atomic beam or an ion beam is used, an inert gas neutral atom beam or inert gas ion beam such as argon can be used. In addition, the bonding surface can be activated by performing plasma irradiation or radical treatment. Such surface treatment makes it easy to form a bond between different materials even at a temperature of 400 ° C. or lower.

  In addition, after the base substrate 2010 and the semiconductor substrate 2002 are bonded to each other through the bonding layer 2022, heat treatment or pressure treatment is preferably performed. By performing the heat treatment or the pressure treatment, the bonding strength can be improved. The temperature of the heat treatment is preferably equal to or lower than the heat resistant temperature of the base substrate 2010. In the pressure treatment, pressure is applied in a direction perpendicular to the bonding surface, and the pressure resistance of the base substrate 2010 and the semiconductor substrate 2002 is taken into consideration.

  Next, heat treatment is performed, and part of the semiconductor substrate 2002 is separated from the base substrate 2010 with the ion doping layer 2003 as a cleavage plane (see FIG. 24B). The temperature of the heat treatment is preferably higher than the deposition temperature of the bonding layer 2022 and lower than the heat resistance temperature of the base substrate 2010. For example, by performing heat treatment at 400 ° C. to 600 ° C., deposition changes of minute cavities formed in the ion doping layer 2003 occur, and it is possible to cleave along the ion doping layer 2003. Since the bonding layer 2022 is bonded to the base substrate 2010, the same crystalline SOI layer 2030 as the semiconductor substrate 2002 remains on the base substrate 2010.

  Thus, an SOI structure in which the SOI layer 2030 is provided over the base substrate 2010 with the bonding layer 2022 formed is formed. Note that an SOI substrate has a structure in which a plurality of SOI layers are provided over a single base substrate with a bonding layer interposed therebetween.

  Note that the SOI layer obtained by peeling is preferably subjected to chemical mechanical polishing (CMP) in order to planarize the surface. Further, planarization may be performed by irradiating the surface of the SOI layer with a laser beam without using physical polishing means such as CMP. Note that the laser beam irradiation is preferably performed in a nitrogen atmosphere with an oxygen concentration of 10 ppm or less. This is because the surface of the SOI layer may be roughened when laser beam irradiation is performed in an oxygen atmosphere. Further, CMP or the like may be performed for the purpose of thinning the obtained SOI layer.

  With the method for manufacturing an SOI substrate described in this embodiment, an SOI layer 2030 having a strong bonding strength can be obtained even when the base substrate 2010 has a heat resistant temperature of 600 ° C. or lower, such as a glass substrate. In addition, since a temperature process of 600 ° C. or less may be applied, various glass substrates used for the electronic industry called non-alkali glass such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used as the base substrate 2010. It becomes possible to apply. Of course, a ceramic substrate, a sapphire substrate, a quartz substrate, or the like can also be applied.

In the SOI substrate described in this embodiment, since a single crystal semiconductor film can be directly formed over an insulating substrate such as a glass substrate, a crystallization process such as laser crystallization of a semiconductor film for improving semiconductor characteristics can be performed. There is no need. Therefore, by manufacturing an SOI substrate and manufacturing a transistor or the like using the method described in Embodiment Mode 4, a semiconductor device can be formed using elements with little variation in transistor characteristics. A semiconductor device with a high level can be manufactured.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 8)

In this embodiment, an example of manufacturing a transistor included in the semiconductor memory device described in the above embodiment will be described. In this embodiment mode, a mode in which a transistor included in a semiconductor device is manufactured using single crystal silicon and a semiconductor memory device is provided will be described with reference to FIGS.

  First, a manufacturing process of the transistor is described with reference to FIG. A silicon substrate 2601 made of single crystal silicon is prepared. Then, a p-type well 2602 is selectively formed in the element formation region in the element formation region of the main surface (element formation surface or circuit formation surface) of the silicon substrate provided with n-type conductivity. Further, it can be thinned by a method such as polishing the back surface of the silicon substrate. By thinning the silicon substrate in advance, the semiconductor device can be manufactured as a lightweight and thin semiconductor device.

  Next, a field oxide film 2603 serving as an element isolation region for partitioning the first element formation region and the second element formation region is formed. The field oxide film 2603 is a thick thermal oxide film and may be formed using a known LOCOS method. The element isolation method is not limited to the LOCOS method. For example, the element isolation region may have a trench structure using the trench isolation method, or may be a combination of the LOCOS structure and the trench structure.

  Next, the gate insulating film 2604 is formed by thermally oxidizing the surface of the silicon substrate, for example. The gate insulating film 2604 may be formed by a CVD method, and a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or a stacked film thereof can be used.

Next, a stacked film of a polysilicon layer 2605a and a silicide layer 2605b is formed over the entire surface, and a stacked film is formed based on a lithography technique and a dry etching technique, thereby forming a gate electrode 2605 having a polycide structure on the gate insulating film. . The polysilicon layer 2605a may be doped in advance with phosphorus (P) at a concentration of about 10 ²¹ / cm ³ in order to reduce the resistance, or after the polysilicon film is formed, a dense n-type impurity is diffused. You may let them. As a material for forming the silicide layer 2605b, molybdenum silicide (MoSix), tungsten silicide (WSix), tantalum silicide (TaSix), titanium silicide (TiSix), or the like can be applied. good.

  Note that a sidewall may be formed on the sidewall of the gate electrode. For example, an insulating material layer made of silicon oxide may be made to have a volume over the entire surface by a CVD method, and the insulating material layer may be etched back to form a sidewall. The gate insulating film may be selectively removed in a self-aligned manner during the etch back.

  Next, ion implantation is performed on the exposed silicon substrate to form a source region and a drain region. An element formation region where a p-channel FET is to be formed is covered with a resist material, and n-type impurities such as arsenic (As) and phosphorus (P) are implanted into a silicon substrate to form a source region 2613 and a drain region 2614. Further, an element formation region in which an n-channel FET is to be formed is covered with a resist material, and boron (B) which is a p-type impurity is implanted into a silicon substrate to form a source region 2615 and a drain region 2616.

  Next, an activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation.

  And after activation, an interlayer insulating film and so on. Metal wiring or the like to be a source electrode or a drain electrode is formed. As the interlayer insulating film 2617, a silicon oxide film, a silicon oxynitride film, or the like is formed by a plasma CVD method or a low pressure CVD method. Further, an interlayer insulating film of phosphorus glass (PSG), boron glass (BSG), or phosphorus boron glass (PBSG) may be formed thereon.

  The metal electrode 2619, the metal electrode 2621, the metal electrode 2620, and the metal electrode 2622 are formed after forming contact holes reaching the source region and the drain region of each FET in the interlayer insulating film 2617, and are usually good as a low resistance material. Aluminum (Al) used may be used. Alternatively, a stacked structure of Al and titanium (Ti) may be used.

  The contact hole may be formed by an electron beam direct drawing technique. In direct electron beam drawing, a positive electron beam drawing resist is formed on the entire surface of the interlayer insulating film 2617, and a portion irradiated with the electron beam is dissolved by a developer. Then, a hole is formed in the resist where the contact hole is to be formed, and by performing dry etching using the resist as a mask, the interlayer insulating film 2617 at a predetermined position can be etched to form a contact hole. As described above, the p-channel transistor 2651 and the n-channel transistor 2652 can be manufactured using a single crystal substrate (FIG. 26A).

  Next, an interlayer film 2624 is formed as shown in FIG. Then, the interlayer film 2624 is etched to form a contact hole, and a part of the metal electrode 2622 is exposed. The interlayer film 2624 is not limited to resin, and may be another film such as a CVD oxide film, but is preferably a resin from the viewpoint of flatness. Alternatively, a contact hole may be formed using a photosensitive resin without using etching. Next, a wiring 2625 that is in contact with the conductive film 2618 through a contact hole is formed over the interlayer film 2624.

  Next, a conductive film 2626 functioning as an antenna is formed so as to be in contact with the wiring 2625. The conductive film 2626 includes silver (Ag), gold (Au), copper (Cu), palladium (Pd), chromium (Cr), platinum (Pt), molybdenum (Mo), titanium (Ti), tantalum (Ta), It can be formed using a metal such as tungsten (W), aluminum (Al), iron (Fe), cobalt (Co), zinc (Zn), tin (Sn), nickel (Ni). As the conductive film 2626, a film formed using an alloy containing the metal as a main component or a film formed using a compound containing the metal may be used in addition to the film formed using the metal. As the conductive film 2626, the above-described film may be used as a single layer, or a plurality of the above-described films may be stacked.

  The conductive film 2626 can be formed by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, a photolithography method, an evaporation method, or the like.

  Note that although an example in which the antenna is formed over the same substrate as the semiconductor element is described in this embodiment mode, the present invention is not limited to this structure. After forming the semiconductor element, a separately formed antenna may be electrically connected to the integrated circuit. In this case, the electrical connection between the antenna and the integrated circuit is made by crimping with an anisotropic conductive film (ACF (Anisotropic Conductive Film)), an anisotropic conductive paste (ACP (Anisotropic Conductive Paste)), or the like. Can be connected to. In addition, it is also possible to perform connection using a conductive adhesive such as silver paste, copper paste, or carbon paste, solder bonding, or the like.

  Next, as illustrated in FIG. 27A, a protective film 2627 is formed so as to cover the conductive film 2626 functioning as an antenna. The protective film 2627 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. Further, an organic resin film may be laminated on the organic resin film or the protective film instead of the silicon nitride film or the like. As the organic resin material, polyimide, polyamide, acrylic, benzocyclobutene (BCB), or the like can be used. Advantages of using the organic resin film include that the film formation method is simple, that the parasitic capacitance can be reduced because the relative dielectric constant is low, and that it is suitable for planarization. Of course, organic resin films other than those described above may be used.

Then, as shown in FIG. 27B, the semiconductor device can be completed by covering with a film 2628. A protective film may be formed on the surface of the film 2628 in order to prevent entry of moisture, oxygen, and the like. The protective film can be formed using an oxide containing silicon or a nitride containing silicon. The film may be formed with a pattern to be a booster antenna of a semiconductor device.

In this manner, a semiconductor device formed over a single crystal substrate can provide a lighter and smaller product. Such a semiconductor device is preferable because a miniaturized semiconductor device can be manufactured and variation in transistor characteristics is small.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.
(Embodiment 9)

Electronic devices that can be mounted with the semiconductor memory device of the present invention include video cameras, digital cameras, goggles-type displays (head mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), computers, game machines, mobile phones An information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a recording medium such as a DVD: Digital Versatile Disc) is played, and the image is displayed. And the like). Specific examples of these electronic devices are shown in FIGS.

FIG. 28A illustrates a portable information terminal (so-called PDA: Personal Digital Assistant) which includes a main body 2801, a display portion 2802, operation keys 2803, a modem 2804, and the like, and the semiconductor memory device of the present invention as a memory element included in the main body 2801. Is provided. With the semiconductor memory device of the present invention, power consumption of the portable information terminal can be reduced.

FIG. 28B illustrates a cellular phone including a main body 2811, a display portion 2812, an audio input portion 2813, an audio output portion 2814, operation keys 2815, an external connection port 2816, an antenna 2817, and the like. A semiconductor memory device of the present invention is provided. With the semiconductor memory device of the present invention, power consumption of a cellular phone can be reduced.

FIG. 28C illustrates an electronic card, which includes a main body 2821, a display portion 2822, a connection terminal 2823, and the like, and the semiconductor memory device of the present invention is provided as a memory element included in the main body 2811. With the semiconductor memory device of the present invention, the power consumption of the electronic card can be reduced. Note that a contact-type electronic card is shown in FIG. 28C, but the semiconductor memory device of the present invention is also applied to a non-contact type electronic card or an electronic card having both a contact type and a non-contact type function. Can be used.

FIG. 28D illustrates an electronic book which includes a main body 2831, a display portion 2832, operation keys 2833, and the like, and the semiconductor memory device of the present invention is provided as a memory element included in the main body 2831. In the electronic book, a modem may be incorporated in the main body 2831. With the semiconductor memory device of the present invention, power consumption of an electronic book can be reduced.

FIG. 28E illustrates a computer, which includes a main body 2841, a display portion 2842, a keyboard 2843, a touch pad 2844, an external connection port 2845, a power plug 2846, and the like. The semiconductor memory device of the present invention is used as a memory element included in the main body 2841. Is provided. With the semiconductor memory device of the present invention, low power consumption of a computer can be achieved.

As described above, the applicable range of the present invention is so wide that it can be used for memory elements of any electronic devices.

Note that this embodiment mode can be implemented in combination with the technical elements of the embodiment modes in this specification.

FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 3 is a diagram for illustrating Embodiment 1; FIG. 3 is a diagram for illustrating Embodiment 1; FIG. 3 is a diagram for illustrating Embodiment 1; FIG. 3 is a diagram for illustrating Embodiment 1; FIG. 3 is a diagram for illustrating Embodiment 1; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 6 is a diagram for illustrating Embodiment 4; FIG. 6 is a diagram for illustrating Embodiment 5; FIG. 6 is a diagram for illustrating Embodiment 5; FIG. 10 is a diagram for illustrating Embodiment 6; FIG. 10 is a diagram for illustrating Embodiment 6; FIG. 10 is a diagram for illustrating Embodiment 6; FIG. 10 is a diagram for illustrating Embodiment 6; FIG. 10 is a diagram for illustrating Embodiment 7; FIG. 10 is a diagram for illustrating Embodiment 7; FIG. 10 is a diagram for illustrating Embodiment 7; FIG. 10 is a diagram for illustrating Embodiment 8; FIG. 10 is a diagram for illustrating Embodiment 8; FIG. 10 is a diagram for illustrating Embodiment 9;

Explanation of symbols

100 Semiconductor memory device 101 Decoder 102 Write / read circuit 103 Memory cell array 104 Address signal line 105 Write enable signal line 106 Read enable signal line 107 Memory cell 108 Read / write word line 109 Address signal line 110 Input data signal line 111 Output data signal line 112 Read / write bit signal line 113 Read / write bit inverted signal line 114a Power supply control circuit 114b Power supply control circuit 115 Power supply line 116 Ground line 201a N-channel transistor 201b N-channel transistor 202 Latch circuit 202a Inverter circuit 202b Inverter circuit 203 Diode 204a Capacitance element 204b Capacitance element 251 N-channel transistor 252 P-channel transistor 253 N-channel Transistor 254 P-channel transistor 281 Node 282 Node 700 Semiconductor memory device 701 Decoder 702 Write / read circuit 703 Memory cell array 704 Address signal line 705 Write enable signal line 706 Read enable signal line 707 Memory cell 708 Write word line 709 Address signal line 710 Input data signal line 711 Output data signal line 712 Write bit signal line 713 Write bit inverted signal line 714a Power supply control circuit 714b Power supply control circuit 715 Power supply line 716 Ground line 721 Read word line 722 Read bit line 801a N-channel transistor 801b N Channel type transistor 802 Latch circuit 802a Inverter circuit 802b Inverter circuit 803 Diode 804 N-channel Nell transistor 805 N channel transistor 1001 Node 1200 Semiconductor memory device 1201 Decoder 1202 Write / read circuit 1203 Memory cell array 1204 First write address signal line 1205 First read address signal line 1206 Second read address signal line 1207 Write enable Signal line 1208 Memory cell 1209 Write word line 1210 Read word line 1211 Read word line 1212 Second write address signal line 1213 Third read address signal line 1214 Fourth read address signal line 1215 Input data signal line 1216 Output data signal Line 1217 Output data signal line 1218 Write bit signal line 1219 Write bit inverted signal line 1220 First read bit line 1221 Second Read bit line 1222a Power supply control circuit 1222b Power supply control circuit 1223 Power supply line 1224 Ground line 1225 Read enable signal line 1301a N-channel transistor 1301b N-channel transistor 1302 Latch circuit 1302a Inverter circuit 1302b Inverter circuit 1303 Diode 1304 N-channel transistor 1305 N Channel type transistor 1306 N channel type transistor 1307 N channel type transistor 1308 Memory cell 1308a Memory cell 1308b Memory cell 1401 Analog switch 1601 D $
1602 I $
1603 DU
1604 ALU
1605 PC
1606 IO
1700 Semiconductor device 1701 Semiconductor integrated circuit 1702 Antenna 1703 Transmission / reception circuit 1704 Power supply circuit 1705 Control circuit 1706 Memory element 1709 Demodulated signal 1710 Signal 1720 Communication device 1721 Antenna unit 1722 Control terminal 1901 Substrate 1902 Peeling layer 1903 Insulating film 1904 Semiconductor film 1904a Semiconductor film 1904b Semiconductor film 1904c Semiconductor film 1904d Semiconductor film 1905 Gate insulating film 1906a Channel formation region 1906b Impurity region 1906c Impurity region 1907 Gate electrode 1908 Insulating film 1909 Insulating film 1910 Insulating film 1911 Insulating film 1912 Conductive film 1912 Conductive film 1913 Insulating film 1917 Insulating film 1918 Opening 1920 Sheet material 1921 Sheet material 1931 Conductive film 1950 Region 1951 Element layer 2 01 Semiconductor substrate 2002 Semiconductor substrate 2003 Ion doping layer 2004 Ion 2010 Base substrate 2022 Bonding layer 2030 SOI layer 2601 Silicon substrate 2602 P-type well 2603 Field oxide film 2604 Gate insulating film 2605 Gate electrode 2613 Source region 2614 Drain region 2615 Source region 2616 Drain Region 2617 Interlayer insulating film 2618 Conductive film 2619 Metal electrode 2620 Metal electrode 2621 Metal electrode 2622 Metal electrode 2624 Interlayer film 2625 Wiring 2626 Conductive film 2627 Protective film 2651 P-channel transistor 2651 n-channel transistor 2801 Main body 2802 Display portion 2803 Operation Key 2804 Modem 2811 Main body 2812 Display unit 2813 Voice input unit 281 Audio output unit 2815 Operation key 2816 External connection port 2817 Antenna 2821 Main unit 2822 Display unit 2823 Connection terminal 2831 Main unit 2832 Display unit 2833 Operation key 2841 Main unit 2842 Display unit 2843 Keyboard 2844 Touch pad 2845 External connection port 2846 Power plug 2605a Polysilicon layer 2605b Silicide layer

Claims (5)

A first transistor and a second transistor having gate terminals connected to the read / write word line;
A memory cell comprising: a read / write bit signal line connected to the first transistor; and a latch circuit for holding a storage state of data written from the read / write bit inverted signal line connected to the second transistor. Have
The first inverter circuit and the second inverter circuit constituting the latch circuit are connected so that a power supply potential is supplied from a diode connected to a power supply line,
A semiconductor memory device, wherein a capacitance element is connected to an output terminal of either the first inverter circuit or the second inverter circuit. A first transistor and a second transistor, each having a gate terminal connected to the write word line;
A latch circuit for holding a storage state of data written from a write bit signal line connected to the first transistor and a write bit inverted signal line connected to the second transistor;
A third transistor having a gate terminal connected to an output terminal of either the first inverter circuit or the second inverter circuit constituting the latch circuit;
A gate terminal having a memory cell including a fourth transistor connected to the read word line;
The first inverter circuit and the second inverter circuit are connected so that a power supply potential is supplied from a diode connected to a power supply line,
The first terminal of either the third transistor or the fourth transistor is connected to a ground line,
The other first terminal of the third transistor or the fourth transistor is connected to a read bit line,
2. A semiconductor memory device, wherein a second terminal of the third transistor and a second terminal of the fourth transistor are connected. A first transistor and a second transistor, each having a gate terminal connected to the write word line;
A latch circuit for holding a storage state of data written from a write bit signal line connected to the first transistor and a write bit inverted signal line connected to the second transistor;
A third transistor having a gate terminal connected to the output terminal of the first inverter circuit constituting the latch circuit;
A fifth transistor having a gate terminal connected to an output terminal of a second inverter circuit constituting the latch circuit;
A fourth transistor having a gate terminal connected to the first read word line;
A gate terminal having a memory cell including a sixth transistor connected to the second read word line;
The first inverter circuit and the second inverter circuit are connected so that a power supply potential is supplied from a diode connected to a power supply line,
The first terminal of either the third transistor or the fourth transistor is connected to a ground line,
The other first terminal of the third transistor or the fourth transistor is connected to a first read bit line,
A second terminal of the third transistor and a second terminal of the fourth transistor are connected;
The first terminal of either the fifth transistor or the sixth transistor is connected to the ground line,
The other first terminal of the fifth transistor or the sixth transistor is connected to a second read bit line,
A semiconductor memory device, wherein a second terminal of the fifth transistor and a second terminal of the fifth transistor are connected. In any one of Claim 1 thru | or 3,
The semiconductor memory device, wherein the transistor is a thin film transistor. An electronic apparatus comprising the semiconductor memory device according to claim 1.

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