TWI423392B - Semiconductor device and electronic device - Google Patents

Semiconductor device and electronic device Download PDF

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Publication number
TWI423392B
TWI423392B TW96122933A TW96122933A TWI423392B TW I423392 B TWI423392 B TW I423392B TW 96122933 A TW96122933 A TW 96122933A TW 96122933 A TW96122933 A TW 96122933A TW I423392 B TWI423392 B TW I423392B
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Taiwan
Prior art keywords
transistor
electrically connected
bit line
circuit
switching element
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TW96122933A
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Chinese (zh)
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TW200818400A (en
Inventor
Takayuki Inoue
Yoshiyuki Kurokawa
Takayuki Ikeda
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Semiconductor Energy Lab
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Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of TW200818400A publication Critical patent/TW200818400A/en
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Publication of TWI423392B publication Critical patent/TWI423392B/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Description

Semiconductor device and electronic device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device mounted with a memory. Further, the present invention relates to an electronic device including the semiconductor device.

In a semiconductor device in which a memory is mounted, the function of the memory is very important in determining the function of the semiconductor device. For example, in a semiconductor device in which a CPU and a memory are mounted, it is necessary to store instructions processed by the CPU and data required for processing in a memory. In addition, the CPU reads the data in the memory in order to perform processing. In other words, in order to achieve high functionality, the CPU needs to perform further complicated processing, so that a large-capacity memory needs to be mounted in a semiconductor device in which a CPU and a memory are mounted. Further, in a semiconductor device in which a memory is mounted, in many cases, the power consumption of the memory accounts for a large portion of the power consumption of the semiconductor device.

Non-Patent Document 1 discloses an RFID (Radio Frequency Identification) device (hereinafter referred to as RFID) to which a CPU (Central Processing Unit) and a memory are mounted as an example of a semiconductor device having a memory, and the non-patent document 1 One of the authors is the author of the present invention. Such RFID is required to increase the capacity of a memory to achieve high functionality and achieve low power consumption, which are not easily realized at the same time.

[Non-Patent Document 1] Hiroki Dembo and others ("RFCPUs on Glass and Plastic Substrates fabricated by TFT Transfer Technology" IEEE, TECHNICAL DIGEST OF INTERNATIONAL ELECTRON DEVICES MEETING, December 5, 2005, pp. 1067-1069.)

In a semiconductor device in which a memory is mounted, as the memory capacity increases in recent years, the increase in power consumption when reading data is remarkable. In particular, in a ROM (read only memory) that performs data reading at a high speed, when reading data stored therein, it is necessary to precharge each bit line. Therefore, the increase in power consumption when reading the data in the ROM is particularly large.

Here, an example of a ROM for reading data in a conventional memory will be described using the configuration of the mask ROM shown in FIG. In addition, FIG. 5 shows a block diagram of a mask ROM. Fig. 6 is a circuit diagram of the present invention in which the area 511 of Fig. 5 is enlarged. In addition, FIG. 7 is a timing chart of a circuit diagram of the mask ROM of FIG. 6.

First, Fig. 5 will be explained. In FIG. 5, the mask ROM is composed of an address signal line 501, an address input buffer 502, a column decoder 503, a ground line 504 (also referred to as a GND line), a memory matrix 505, a read enable signal line 506, The precharge circuit 507, the row decoder 508, the data output buffer 509, and the data signal line 510 are formed.

In FIG. 5, the address signal line 501 is composed of ten address signal lines A0 to A9. The memory matrix 505 is composed of a plurality of memory cells. Further, the data signal line 510 is composed of eight data signal lines D0 to D7. Note that the number of address signal lines 501 and the number of data signal lines 510 shown here are only an example, but are not limited thereto.

Next, the structure of the area 511 in Fig. 5 will be described using Fig. 6 . As the area 511 in FIG. 5, the nth (n is a natural number) word line 601, the n+1th word line 602, the mth (m is a natural number) bit line 603, and the m+1th bit line 604 are shown, corresponding to the The memory cell 605 of the nth column mth row arranged at the intersection of the n word line 601 and the mth bit line 603, the n+1th column arranged corresponding to the intersection of the n+1th word line 602 and the mth bit line 603 The memory unit 606 of the mth row, the memory cell 607 of the nth column m+1th row arranged corresponding to the intersection of the nth word line 601 and the m+1th bit line 604, corresponding to the n+1th word line 602 and the m+1th The memory cell 608 of the n+1th column m+1th row arranged at the intersection of the bit line 604, the mth precharge circuit 609, the m+1 precharge circuit 610, the read enable signal line 611, the mth latch circuit 612, and the The m+1 latch circuit 613, the mth analog switch 614, the m+1 analog switch 615, the mth selection signal line 616, the mth inversion selection signal line 617, the m+1th selection signal line 618, the m+1th inversion selection signal line 619, And an output data signal line 620 of the memory.

Further, in the present specification, a memory cell arranged corresponding to an intersection of the nth word line and the mth bit line is referred to as a memory cell of the nth column mth row.

The memory cell 605 of the mth row of the nth column, the memory cell 606 of the nth column mth row, the memory cell 607 of the nth column m+1 row, and the memory cell 608 of the n+1th column m+1 row are respectively composed of one N-channel type transistor. Here, in the memory cell 605 of the mth row of the nth column, the gate of the N-channel type transistor is electrically connected to the nth word line 601, the source is electrically connected to the ground line, and the drain is electrically connected to the mth bit. Yuan line 603. In the memory cell 606 of the nth column and the mth row, the gate of the N-channel type transistor is electrically connected to the n+1th word line 602, the drain is electrically connected to the mth bit line 603, and the source has no electrical connection relationship. It is in a floating state. In the memory cell 607 of the m+1th row of the nth column, the gate of the N channel type transistor is electrically connected to the nth word line 601, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 604. In the memory cell 608 of the n+1th column m+1th row, the gate of the N channel type transistor is electrically connected to the n+1th word line 602, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 604. Further, the mth precharge circuit 609 and the m+1th precharge circuit 610 are composed of a P channel type transistor. The gate of the P-channel type transistor of the mth precharge circuit 609 is electrically connected to the read enable signal line 611, the source is electrically connected to the power supply line 621, and the drain is electrically connected to the mth bit line 603. The gate of the P-channel type transistor of the m+1th precharge circuit 610 is electrically connected to the read enable signal line 611, the source is electrically connected to the power supply line 622, and the drain is electrically connected to the m+1th bit line 604.

The mth selection signal line 616 and the mth inversion selection signal line 617 are electrically connected to the mth analog switch 614, respectively. In addition, the potential of the mth selection signal line 616 is set to a high potential level (hereinafter referred to as an H level) and the potential of the mth inversion selection signal line 617 is set to a low potential level (hereinafter referred to as an L level). The m-th class can be electrically or non-conducted than the switch 614. The m+1th selection signal line 618 and the m+1th inversion selection signal line 619 are electrically connected to the m+1th analog switch 615, respectively. Further, by setting the potential of the (m+1)th selection signal line 618 to the H level and the potential of the m+1th inversion selection signal line 619 to the L level, the m+1 analog switch 615 can be electrically or non-conductive. Further, the potential of the mth selection signal line 616 and the potential of the m+1th selection signal line 618 are generated by decoding a specific bit of the memory address signal. In other words, either one becomes the H level and the other becomes the L level. Further, when the potential of the mth selection signal line 616 is the L level, the potential of the mth inversion selection signal line 617 is the H level, and when the potential of the mth selection signal line 616 is the H level, the mth inversion The potential of the selection signal line 617 is the L level. Similarly, when the potential of the m+1th selection signal line 618 is the L level, the potential of the m+1th inversion selection signal line 619 is the H level, and when the potential of the m+1th selection signal line 618 is the H level, the m+1th The potential of the phase selection signal line 619 is the L level.

Next, Fig. 7 shows a timing chart of signals input to and output from the memory unit shown in Fig. 6. 7 is the potential of the read enable signal line 611, the potential of the mth bit line 603, the potential of the m+1th bit line 604, the potential of the nth word line 601, the potential of the n+1th word line 620, and the mth selection signal. A timing chart of the potential of the line 616, the potential of the m+1th selection signal line 618, and the potential of the output data signal line 620.

In addition, in Fig. 7, T1-1 indicates a first precharge period, T1-2 indicates a first readout period, T2-1 indicates a second precharge period, and T2-2 indicates a second readout period, T3-1. Indicates a third precharge period, T3-2 indicates a third readout period, T4-1 indicates a fourth precharge period, and T4-2 indicates a fourth readout period.

Note that, although the present specification specifically describes an example in which the H level and the L level are input to the respective signal lines, the potential of each signal line depends on the polarity of the transistors constituting the circuit, and is not particularly limited thereto.

Next, the operation of the memory shown in FIG. 6 will be specifically described using the timing chart shown in FIG. The case of reading the data in the memory unit 605 of the mth row of the nth column will be described first.

First, in the first precharge period T1-1, the potential of the read enable signal line 611 supplied to the read enable signal line 611 becomes the L level. At this time, the potential of the gate of the P-channel type transistor of the mth precharge circuit 609 and the m+1th precharge circuit 610 becomes the L level. Therefore, the potentials of the mth bit line 603 and the m+1th bit line 604 all become the H level.

Further, the potentials of the nth word line 601 and the n+1th word line 602 are both set to the L level. Then, the potential of the mth selection signal line 616 is set to the H level and the potential of the m+1th selection signal line 618 is set to the L level so that the data in the memory cell 605 of the mth row of the nth column is read. In other words, the mth analog switch 614 is turned on, and the m+1th analog switch 615 is non-conductive.

Further, the mth latch circuit 612 and the m+1th latch circuit 613 are used to hold the potentials of the mth bit line 603 and the m+1th bit line 604, respectively. In other words, keep the H level. The above-described operation is the precharge operation in the mth precharge period T1-1.

Next, in the first readout period T1-2, the potential of the read enable signal line 611 is set to the H level. At this time, the potential of the gate of the P-channel type transistor of the mth precharge circuit 609 and the m+1th precharge circuit 610 becomes the H level.

Further, the potential of the nth word line 601 is set to the H level so that the data of the memory cell 605 of the mth row of the nth column is read. At this time, the potential of the gate of the N-channel type transistor in the memory cell 605 of the mth row of the nth column and the memory cell 607 of the m+1th row of the nth column becomes the H level.

At this time, since the source of the N-channel type transistor in the memory cell 605 of the mth row of the nth column is electrically connected to the ground line, the potential of the bit line 603 of the mth row of the nth column becomes the L level. . Similarly, since the source of the N-channel type transistor in the memory cell 607 of the m+1th row of the nth column is electrically connected to the ground line, the potential of the m+1th bit line 604 becomes the L level.

Here, since the mth analog switch 614 is turned on, the potential of the output data signal line 620 becomes the same L level as the potential of the mth bit line 603. Thereby, the material in the memory unit 605 of the mth row of the nth column is read. The above described operation is to read the data in the memory unit 605 of the mth row of the nth column.

Next, a case where the material in the memory unit 606 of the nthth column and the mth row is read will be described.

First, in the second precharge period T2-1, the potential of the read enable signal line 611 supplied to the read enable signal line 611 is set to the L level. At this time, the potential of the gate of the P-channel type transistor of the mth precharge circuit 609 and the m+1th precharge circuit 610 becomes the L level. Therefore, the potentials of the mth bit line 603 and the m+1th bit line 604 all become the H level.

Further, both the potential of the nth word line 601 and the potential of the n+1th word line 602 are set to the L level. Then, the potential of the mth selection signal line 616 is set to the H level and the potential of the m+1th selection signal line 618 is set to the L level so that the data in the memory cell 606 of the mth row of the n+1th column is read. In other words, the mth analog switch 614 is turned on, and the m+1th analog switch 615 is non-conductive.

At this time, the potential of the mth bit line 603 and the m+1th bit line 604 are held using the mth latch circuit 612 and the m+1th latch circuit 613, respectively. In other words, keep the H level. The above described work is the precharge operation in the second precharge period T2-1.

Next, in the second readout period T2-2, the potential of the read enable signal line 611 is set to the H level. At this time, the potential of the gate of the P-channel type transistor of the mth precharge circuit 609 and the m+1th precharge circuit 610 becomes the H level.

Further, the potential of the n+1th word line 602 is set to the H level so that the data in the memory cell 606 of the mth row of the n+1th column is read. At this time, the potential of the gate of the N-channel type transistor in the memory cell 606 of the m+1th row and the memory cell 608 of the (n+1)th m+1th row of the n+1th column becomes the H level.

At this time, since the source of the N-channel type transistor in the memory cell 606 of the mth row of the n+1th column has no connection relationship, the potential of the mth bit line 603 becomes the H level. On the other hand, since the source of the N-channel type transistor in the memory cell 608 of the m+1th row of the (n+1)th column is electrically connected to the ground line, the potential of the m+1th bit line 604 becomes the L level.

Here, since the mth analog switch 614 is turned on, the potential of the output data signal line 620 becomes the same H level as the potential of the mth bit line 603. Thereby, the material in the memory unit 606 of the mth row of the n+1th column is read. The above described work is the operation of reading the data in the memory unit 606.

Similarly, the precharge operation is performed in the third precharge period T3-1, and the data in the memory unit 607 in the m+1th row of the nth column is read in the third readout period T3-2. Similarly, the precharge operation is performed in the fourth precharge period T4-1, and the data in the memory unit 608 of the (n+1) th+1th row in the n+1th column is read in the fourth readout period T4-2.

What has been described above is the operation of the memory shown in FIG. 6.

As shown in the timing chart of FIG. 7, when the data is read by the conventional memory, since the potential of the bit line is set to the H level in the precharge period, the fluctuation of the potential is increased, and a large amount of power is consumed. Further, in the case of reading data in the conventional memory, since the potential of the bit line is set to the L level in the read period, the fluctuation of the potential is increased, and a large amount of electric power is consumed.

For example, in the second readout period T2-2 of FIG. 7, the memory cell to be read out is the memory cell 606 of the n+1th column mth row, but at the same time, connected to the n+1th column m+1th row. The potential of the m+1th bit line 604 of the memory unit 608 also becomes the L level. In other words, it can be known that the bit line that does not need to read the data also consumes power.

The present invention has been made in view of the above various problems, and an object thereof is to provide a semiconductor device in which a memory for reading data from a memory with low power consumption is mounted.

The memory-mounted semiconductor device of the present invention has a structure of selectively precharging a bit line connected to a memory cell in which material to be read is stored, and not pre-charging to a memory that does not require reading. The potential of the bit line of the cell. The specific structure of the present invention is to provide an analog switch to selectively precharge the potential of the bit line and the data line in the memory. The specific structure of the present invention is shown below.

One of the semiconductor devices of the present invention has: a word line, a first bit line, a second bit line, a first memory unit electrically connected to the word line and the first bit line, electrically connected to the word line, and second a second memory unit of the bit line, a first precharge circuit for outputting a potential for reading data held in the first memory unit to the first bit line, and a second bit line output for reading a second precharge circuit for maintaining a potential of the material in the second memory unit, a first switching element disposed between the first bit line and the first precharge circuit, and a second bit line and a second switching element between the second pre-charge circuits. A potential for reading out the material held in the first memory is input to the first bit line selected by the first switching element. A potential for reading out the material held in the second memory is input to the second bit line selected by the second switching element.

One of the semiconductor devices of the present invention has: a word line, a first bit line, a second bit line, a first memory unit electrically connected to the word line and the first bit line, electrically connected to the word line, and second a second memory unit of the bit line, the bit line output selected from the first bit line and the second bit line for reading out one of the first memory unit and the second memory unit a precharge circuit for potential of the data in the memory unit, a first switching element disposed between the first bit line and the precharge circuit, and a second switch disposed between the second bit line and the precharge circuit element. A potential for reading out the material held in the first memory is input to the first bit line selected by the first switching element. A potential for reading out the material held in the second memory is input to the second bit line selected by the second switching element.

Further, in the present invention, the memory unit may include a transistor having a gate terminal connected to the word line and one of its source and drain terminals connected to the bit line. In addition, the transistor may be disposed on the same substrate, and the substrate is any one of a glass substrate, a quartz substrate, and a plastic substrate. In addition, the transistor may also have an SOI substrate.

Further, in the present invention, it is also possible to have a latch circuit electrically connected to the bit line and holding the potential for reading the material held in the memory unit.

Further, in the present invention, the precharge circuit may include a transistor, and one of the source and the drain of the transistor is electrically connected to the switching element.

Further, in the present invention, a decoder for selecting any one of the memory cells and reading the held data may be provided, and the decoder is connected to the memory cell through the word line and the bit line.

Further, the switches shown in this specification can use various types of switches, and as an example thereof, there are an electric switch, a mechanical switch, and the like. In other words, as long as it can control the flow of current, there is no particular limitation. For example, the switch may be a transistor, a diode (PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), or a logic circuit combining them. Therefore, in the case where a transistor is used as the switch, the transistor operates as a simple switch, so there is no particular limitation on the polarity (conductivity type) of the transistor. However, in the case where the off current (OFF) is preferably small, it is preferable to use a transistor having a polarity having a small off current. As the transistor having a small off current, there is a transistor provided with an LDD region or a transistor having a multi-gate structure. In addition, when the potential of the source terminal of the transistor operating as a switch is close to the low-potential side power supply (Vss, GND, 0V, etc.), it is preferable to use an N-channel type transistor, and conversely, at the source terminal. When the potential is close to the high-potential side power supply (Vdd, etc.), it is preferable to use a P-channel type transistor. This is because the transistor can be stably operated as a switch since the absolute value of the gate-source voltage can be increased. In addition, the switch may be a CMOS switch using both an N-channel type transistor and a P-channel type transistor. When a CMOS switch is used, it is also possible to operate properly in the following cases: since the voltage output through the switch (i.e., the input voltage to the switch) is high or low with respect to the output voltage, the condition changes.

In addition, the "connection" in the present invention includes the case of "electrical connection" and "direct connection". Therefore, in the structure proposed by the present invention, not only a predetermined connection relationship but also other elements capable of achieving electrical connection (for example, a switch, a transistor, a capacitor element, an inductor, a resistance element or a diode) may be provided therebetween. Body, etc.). Alternatively, it may be arranged in a direct connection without interposing other elements. In addition, the following case is a "direct connection", that is, a case where only the other elements in the middle of which the clip can be electrically connected are connected and directly connected, and the case where the electrical connection is not included. In addition, the "electrical connection" is a case including a case of electrical connection and a case of direct connection.

In the present invention, various types of transistors can be used for the transistor, and the kind thereof is not particularly limited. Thus, a transistor using a thin film transistor (TFT) of a non-single-crystal semiconductor film typified by amorphous germanium or polycrystalline germanium, a transistor formed using a semiconductor substrate or an SOI substrate, a MOS transistor, and a junction dielectric can be used. A crystal, a bipolar transistor, a transistor using a compound semiconductor such as ZnO or a-InGaZnO, a transistor using an organic semiconductor or a carbon nanotube, or other transistor. Further, hydrogen or a halogen may be contained in the non-single crystal semiconductor film. Further, the type of the substrate on which the transistor is disposed is not limited to a specific type, and various substrates can be used. For example, the transistor may be disposed on a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having a stainless steel foil, or the like. Further, it is also possible to move the transistor to another substrate after forming a transistor on a certain substrate to arrange the transistor on the other substrate.

In addition, the structure of the transistor is not limited to a specific structure, and various methods can be employed. For example, it is also possible to adopt a multi-gate structure in which the number of gate electrodes is two or more. By adopting this structure, the off current can be lowered, the withstand voltage of the transistor can be improved to improve reliability, and the drain-source current does not change much even when the drain-source voltage changes while operating in the saturation region. It has stable characteristics. Further, a structure in which gate electrodes are arranged above and below the channel can also be employed. By adopting a structure in which gate electrodes are arranged on and below the channel, the channel region is increased, so that the current value can be increased, and the depletion layer is easily generated, thereby reducing the S value. In addition, a structure in which a gate electrode is arranged on a channel, a structure in which a gate electrode is arranged under a channel, a staggered structure, an inverted staggered structure, a structure in which a channel is divided into a plurality of regions, a structure in parallel connection, and a series connection may also be employed. Structure. In addition, the source electrode or the drain electrode may be overlapped with the channel (or a portion thereof). By adopting a structure in which a source electrode or a drain electrode is overlapped with a channel (or a portion thereof), it is possible to prevent a part of the channel from accumulating charges and its operation becomes unstable. In addition, it is also possible to have an LDD (lightly doped germanium) region. By setting the LDD region, the off current can be reduced, the voltage resistance of the transistor can be improved to improve reliability, and when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change much. Has stable characteristics.

In addition, the transistor is an element having at least three terminals including a gate, a drain and a source, and has a channel region between the buffer region and the source region. Here, since the source and the drain are changed depending on the structure of the transistor, the operating conditions, and the like, it is not easy to define the source or the drain. Thus, in the present invention, a region serving as a source and a drain is not referred to as a source or a drain in some cases. In this case, as an example thereof, they are referred to as a first terminal and a second terminal, respectively.

In addition, the gate refers to an entirety or a part thereof including a gate electrode and a gate wiring (also referred to as a gate line). The gate electrode refers to a conductive film in which a gate insulating film is interposed with a semiconductor forming a channel region and an LDD (lightly doped germanium) region or the like.

In addition, the source means an entirety or a part thereof including a source region, a source electrode, and a source wiring (also referred to as a source line or a source signal line, etc.). The source region refers to a semiconductor region containing a large amount of P-type impurities (boron or gallium, etc.) or N-type impurities (phosphorus or arsenic, etc.). Therefore, the source region does not include a region containing a small amount of P-type impurities or N-type impurities, a so-called LDD region. The source electrode refers to a conductive layer of a portion formed of a material different from the source region and electrically connected to the source region. However, sometimes the source region is referred to as a source electrode. The source wiring refers to a wiring for connecting source electrodes of respective pixels or a wiring for connecting a source electrode and another wiring.

However, there are also portions that function as source electrodes and serve as source wiring. Such a region may be referred to as a source electrode or a source wiring. In other words, there is also a region where the source electrode and the source wiring are not clearly distinguished. For example, when a source region is provided overlapping with an extended source wiring, the region serves as a source wiring and also serves as a source electrode. Therefore, such a region may be referred to as a source electrode and may also be referred to as a source wiring.

Further, a region formed of the same material as the source electrode and connected to the source electrode or a portion connecting the source electrode and the source electrode may also be referred to as a source electrode. In addition, a portion overlapping the source region may also be referred to as a source electrode. Likewise, a region formed of the same material as the source wiring and connected to the source wiring may also be referred to as a source wiring. Strictly speaking, this area sometimes has no function of connecting to other source electrodes. However, there are regions formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring due to manufacturing efficiency or the like. Therefore, such a region can also be referred to as a source electrode or a source wiring.

In addition, for example, a conductive film that connects a portion of the source electrode and the source wiring may be referred to as a source electrode and may also be referred to as a source wiring.

In addition, the source terminal refers to a source region, a source electrode, or a portion of a region electrically connected to the source electrode.

In addition, the definition of the drain is the same as the source, and the description thereof is omitted.

Further, in the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, etc.). Further, it is also possible to operate all devices that utilize semiconductor characteristics.

In addition, in the present invention, "above" or "on" "on top of an object" or "formed on" The above description is not limited to the case of direct contact with an object. They also include situations where there is no direct contact, ie where other substances are sandwiched. Thus, for example, "the layer B is formed over the layer A (or on the layer A)" includes the following cases: the case where the layer B is formed in direct contact on the layer A; the layer A is formed in direct contact with another layer The layer (for example, layer C or layer D, etc.), and the layer B is formed in direct contact thereon. In addition, "above" also includes the case where another substance is interposed, and is not limited to the case of direct contact with a substance. Thus, for example, "the layer B is formed over the layer A" includes a case where the layer B is directly contacted on the layer A; another layer (for example, layer C or layer D, etc.) is formed in direct contact on the layer A. And the case where the layer B is formed in direct contact therewith. In addition, the terms "below" or "below" include the case of direct contact and the absence of contact.

According to the present invention, pre-charging of individual bit lines can be selectively performed in a memory mounted in a semiconductor device. In other words, the bit line which is not related to the reading of the data from the memory is not precharged, and a semiconductor device in which a memory having low power consumption is mounted can be manufactured.

Hereinafter, embodiment modes and embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention can be implemented in a variety of different ways, and one of ordinary skill in the art can readily understand the fact that the manner and details can be changed to various types without departing from the spirit and scope of the invention. form. Therefore, the present invention should not be construed as being limited to the contents described in the mode of the embodiment. In the drawings to be described below, the same reference numerals are used to refer to the same parts or parts having the same functions, and the repeated description thereof is omitted.

Embodiment mode 1

Hereinafter, the mode of the present embodiment will be described using FIG. 1, FIG. 2, and FIG. Figure 1 shows a block diagram of a mask ROM of the present invention. Fig. 2 shows a circuit diagram of the invention in which the area 111 in Fig. 1 is enlarged. FIG. 3 shows a timing chart of the circuit diagram of FIG. 2. Further, in the present embodiment mode, although the memory cell is described as the memory of the second row and the second row, it may be generally the memory of the nth column mth row (n, m are natural numbers).

In the present embodiment mode, a mask ROM is used as an example of a ROM for reading data. In FIG. 1, the mask ROM is composed of an address signal line 101, an address input buffer 102, a column decoder 103, a ground line 104, a memory matrix 105, a read enable signal line 106, a switch circuit 107, and a precharge circuit. 108. The data output buffer 109 and the data signal line 110 are formed.

In Fig. 1, the address signal line 101 is composed of ten address signal lines A0 to A9. The memory matrix 105 is composed of a plurality of memory cells. The data signal line 110 is composed of eight data signal lines D0 to D7. In addition, the number of address signal lines 101 and the number of data signal lines 110 shown here are merely examples, and are not limited thereto.

Next, the configuration of the region 111 of the mask ROM in Fig. 1 will be described using Fig. 2 . The area 111 shown in FIG. 2 is composed of an nth word line 201, an n+1th word line 202, an mth bit line 203, an m+1th bit line 204, and an intersection of the nth word line 201 and the mth bit line 203. The memory cell 205 of the nth column mth row, the memory cell 206 of the n+1th column mth row disposed at the intersection of the n+1th word line 202 and the mth bit line 203, and the nth word line 201 and The memory cell 207 of the nth column m+1 row of the intersection of the m+1th bit line 204, the memory cell 208 of the n+1th column m+1th row disposed at the intersection of the n+1th word line 202 and the m+1th bit line 204, The mth latch circuit 209, the m+1th latch circuit 210, the mth analog switch 211, the m+1th analog switch 212, the mth selection signal line 213, the mth inversion selection signal line 214, the m+1th selection signal line 215, and the The m+1 inversion selection signal line 216, the mth precharge circuit 217, the m+1th precharge circuit 218, the read enable signal line 219, and the output data signal line 220 of the memory are formed.

Further, in the present specification, a memory cell arranged corresponding to an intersection of the nth word line and the mth bit line is referred to as a memory cell of the nth column mth row.

The memory cell 205 of the mth row of the nth column, the memory cell 206 of the nth column mth row, the memory cell 207 of the nth column m+1 row, and the memory cell 208 of the n+1th column m+1 row are respectively composed of one N-channel type transistor. Here, in the memory cell 205 of the mth row of the nth column, the gate of the N channel type transistor is electrically connected to the nth word line 201, the source is electrically connected to the ground line, and the drain is electrically connected to the mth bit. Yuan line 203. In the memory cell 206 of the mth row of the n+1th column, the gate of the N-channel type transistor is electrically connected to the n+1th word line 202, the drain is electrically connected to the mth bit line 203, and the source has no electrical connection relationship. It is in a floating state. In the memory cell 207 of the m+1th row of the nth column, the gate of the N-channel type transistor is electrically connected to the nth word line 201, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 204. In the memory cell 208 of the n+1th column m+1th row, the gate of the N channel type transistor is electrically connected to the n+1th word line 202, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 204. Further, the mth precharge circuit 217 and the m+1th precharge circuit 218 are constituted by a P channel type transistor. The gate of the P-channel type transistor of the mth precharge circuit 217 is electrically connected to the read enable signal line 219, the source is electrically connected to the power supply line 221, and the drain is electrically connected to the output data signal line 220 of the memory. The gate of the P-channel type transistor of the m+1 precharge circuit 218 is electrically connected to the read enable signal line 219, the source is electrically connected to the power supply line 222, and the drain is electrically connected to the output data signal line 220 of the memory.

The mth selection signal line 213 and the mth inversion selection signal line 214 are electrically connected to the mth analog switch 211, respectively. Further, by setting the potential of the mth selection signal line 213 to the H level and the potential of the mth inversion selection signal line 214 to the L level, the mth analog switch 211 can be electrically or non-conductive. The m+1th selection signal line 215 and the m+1th inversion selection signal line 216 are electrically connected to the m+1th analog switch 212, respectively. Further, by setting the potential of the (m+1)th selection signal line 215 to the H level and the potential of the m+1th inversion selection signal line 216 to the L level, the m+1th analog switch can be electrically turned on or off. Further, the potential of the mth selection signal line 213 and the potential of the m+1th selection signal line 215 are generated by decoding a specific bit in the memory address signal. In other words, either one is the H level and the other is the L level. Further, when the potential of the mth selection signal line 213 is the L level, the potential of the mth inversion selection signal line 214 is the H level, and when the potential of the mth selection signal line 213 is the H level, the mth inversion The potential of the selection signal line 214 is the L level. Similarly, when the potential of the m+1th selection signal line 215 is the L level, the potential of the m+1th inverted selection signal line 216 is the H level, and when the potential of the m+1th selection signal line 215 is the H level, the m+1th The potential of the inverted selection signal line 216 is the L level.

3 shows the potential of the read enable signal line 219, the potential of the mth bit line 203, the potential of the m+1th bit line 204, the potential of the nth word line 201, and the potential of the n+1th word line 202, m selects the potential of the signal line 213, the potential of the m+1th selection signal line 215, and the timing chart of the output data signal line 220 of the memory, and each potential corresponds to the read enable signal line 219 and the mth bit line of FIG. 203. Potentials of the m+1th bit line 204, the nth word line 201, the n+1th word line 202, the mth selection signal line 213, the m+1th selection signal line 215, and the output data signal line 220 of the memory.

In addition, in FIG. 3, S1-1 is the first precharge period, S1-2 is the first readout period, S2-1 is the second precharge period, and S2-2 is the second readout period, S3-1. It is the third precharge period, S3-2 is the third readout period, S4-1 is the fourth precharge period, and S4-2 is the fourth readout period.

Next, the operation of the memory shown in Fig. 2 will be described. The case of reading the material in the memory unit 205 of the mth row of the nth column will be described first.

First, the potential of the read enable signal line 219 is brought to the L level in the first precharge period S1-1. At this time, the potential of the gate of the P-channel type transistor of the mth precharge circuit 217 and the m+1th precharge circuit 218 becomes the L level. Further, the potential of the nth word line 201 and the potential of the n+1th word line 202 are set to the L level.

Then, the potential of the mth selection signal line 213 is set to the H level, and the potential of the m+1th selection signal line 215 is set to the L level. At this time, the mth analog switch 211 is turned on, and the m+1th analog switch 212 is non-conductive. Therefore, the potential of the mth bit line 203 becomes the H level. On the other hand, the potential of the m+1th bit line 204 is not changed.

Further, the mth latch circuit 209 holds the potential of the mth bit line 203. In other words, keep the H level. The above is the precharge operation in the first precharge period S1-1.

Next, in the first readout period S1-2, the potential of the read enable signal line 219 is set to the H level. At this time, the gate potential of the P-channel type transistor of the mth precharge circuit 217 and the m+1th precharge circuit 218 becomes the L level.

Further, the nth word line 201 is made H level so as to read the data in the memory cell 205 of the mth row of the nth column. At this time, the gate potential of the N-channel type transistor of the memory cell 205 of the nth column and the mth row of the memory cell 207 of the nth column and the m+1th row becomes the H level.

At this time, since the source of the N-channel type transistor of the memory cell 205 of the mth row of the nth column is electrically connected to the ground line, the potential of the mth bit line 203 becomes the L level. Similarly, since the source of the N-channel type transistor of the memory cell 207 of the m+1th row of the nth column is electrically connected to the ground line, the potential of the m+1th bit line 204 becomes the L level.

Here, the mth analog switch 211 is turned on, and the potential of the output data signal line 220 becomes the L level similarly to the potential of the mth bit line 203. Thereby, the material in the memory unit 205 is read. The above is the operation of reading the material in the memory unit 205.

Next, a case where the material in the memory unit 206 of the nthth column and the mth row is read will be described.

First, in the second precharge period S2-1, the read enable signal line 219 is brought to the L level. At this time, the gate potential of the P-channel type transistor of the mth precharge circuit 217 and the m+1th precharge circuit 218 becomes the L level. In addition, the nth word line 201 and the n+1th word line 202 maintain the L level state without change.

Further, the mth selection signal line 213 is set to the H level, and the m+1th selection signal line 215 is set to the L level. At this time, the mth analog switch 211 is turned on, and the m+1th analog switch 212 is non-conductive. Therefore, the potential of the mth bit line 203 becomes the H level. Further, the potential of the m+1th bit line 204 becomes the L level.

Further, the mth latch circuit 209 holds the potential of the mth bit line 203. In other words, keep the H level. Similarly, the m+1th latch circuit 210 holds the potential of the m+1th bit line 204. In other words, keep the L level. The above is the precharge operation in the second precharge period S2-1.

Next, in the second readout period S2-2, the potential of the read enable signal line 219 is set to the H level. At this time, the gate potential of the P-channel type transistor of the mth precharge circuit 217 and the m+1th precharge circuit 218 becomes the L level.

Further, the potential of the n+1th word line 202 is set to the H level so that the data in the memory cell 206 of the n+1th column m row is read. At this time, the gate potential of the N-channel type transistor of the memory cell 206 of the n+1th column mth row and the memory cell unit 208 of the (n+1th column) m+1th row becomes the H level.

At this time, since the source of the N-channel type transistor in the memory cell 206 of the mth row of the n+1th column has no connection relationship, the potential of the mth bit line 203 becomes the H level. On the other hand, since the source of the N-channel type transistor in the memory cell 208 of the m+1th row of the (n+1)th column is electrically connected to the ground line, the potential of the m+1th bit line 204 becomes the L level.

Here, since the m-th class ratio switch 211 is turned on, the potential of the output data signal line 220 becomes the H level in the same manner as the potential of the m-th bit line 203. Thereby, the material in the memory unit 206 is read. The above is the operation of reading the material in the memory unit 206.

Similarly, in the third pre-charging period S3-1, the pre-charging operation is performed, and in the third reading period S3-2, the data in the m-th row m+1-th memory unit 207 is read. Similarly, the precharge operation is performed in the fourth precharge period S4-1, and the data in the memory unit 208 of the n+1th column m+1th row is read in the fourth readout period S4-2.

The above is the operation of the memory shown in FIG. 2.

Further, the advantages of the structure of the read data of the ROM of the present invention compared with the configuration of the read data of the conventional ROM shown in Figs. 5 to 7 will be described.

In the circuit of the mask ROM as a conventional example - the circuit of FIG. 6, as shown in the timing chart of FIG. 7, the mth bit line 603 becomes the H level twice, and the m+1th bit line 604 becomes the fourth time. H level. On the other hand, in the circuit of Fig. 2, as shown in the timing chart of Fig. 3, the potential of the mth bit line 203 becomes the H level once, and the potential of the m+1th bit line 204 becomes the H level three times. In other words, the present invention can eliminate unnecessary pre-charging. That is, power consumption can be reduced. By adopting the above configuration, it is possible to provide a semiconductor device in which a memory is mounted and which realizes low power consumption.

In addition, this embodiment mode can be implemented in combination with other embodiment modes and embodiments as appropriate.

Embodiment mode 2

In the present embodiment mode, a configuration different from the configuration described in the first embodiment mode will be described.

Note that since the block diagram of the structure of the mask ROM in the present embodiment mode is the same as the structure shown in FIG. 1 of the embodiment mode 1, in the embodiment mode, the example 1 is described with reference to FIG. Instructions for explanation.

In addition, FIG. 4 is a circuit diagram of a mask ROM in the present embodiment mode. In the embodiment mode, the region 111 in FIG. 1 shown in the embodiment mode 1 is arranged by the nth word line 201, the n+1th word line 202, the mth bit line 203, and the m+1th bit line 204. The memory cell 205 of the nth column mth row of the intersection of the n word line 201 and the mth bit line 203, and the m+1th row mth row disposed at the intersection of the n+1th word line 202 and the mth bit line 203 The memory unit 206, the memory unit 207 of the nth column m+1th row disposed at the intersection of the nth word line 201 and the m+1th bit line 204, and the intersection of the n+1th word line 202 and the m+1th bit line 204 are disposed. The n+1th column m+1th row of the memory cell 208, the mth latch circuit 209, the m+1th latch circuit 210, the mth analog switch 211, the m+1 analog switch 212, the mth selection signal line 213, and the mth inversion The selection signal line 214, the m+1th selection signal line 215, the m+1th inversion selection signal line 216, the precharge circuit 401, the read enable signal line 219, and the output data signal line 220 of the memory are formed.

The memory cell 205 of the mth row of the nth column, the memory cell 206 of the nth column mth row, the memory cell 207 of the nth column m+1 row, and the memory cell 208 of the n+1th column m+1 row are respectively composed of one N-channel type transistor. Here, in the memory cell 205 of the mth row of the nth column, the gate of the N channel type transistor is electrically connected to the nth word line 201, the source is electrically connected to the ground line, and the drain is electrically connected to the mth bit. Yuan line 203. In the memory cell 206 of the mth row of the n+1th column, the gate of the N-channel type transistor is electrically connected to the n+1th word line 202, the drain is electrically connected to the mth bit line 203, and the source has no electrical connection relationship. It is in a floating state. In the memory cell 207 of the m+1th row of the nth column, the gate of the N-channel type transistor is electrically connected to the nth word line 201, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 204. In the memory cell 208 of the n+1th column m+1th row, the gate of the N channel type transistor is electrically connected to the n+1th word line 202, the source is electrically connected to the ground line, and the drain is electrically connected to the m+1th bit line. 204. In addition, the precharge circuit 401 is composed of a P channel type transistor. The gate of the P-channel type transistor of the precharge circuit 401 is electrically connected to the read enable signal line 219, the source is electrically connected to the power supply line 402, and the drain is electrically connected to the output data signal line 220 of the memory.

The mth selection signal line 213 and the mth inversion selection signal line 214 are electrically connected to the mth analog switch 211, respectively. Further, by setting the potential of the mth selection signal line 213 to the H level and the potential of the mth inversion selection signal line 214 to the L level, the mth analog switch 211 can be electrically or non-conductive. The m+1th selection signal line 215 and the m+1th inversion selection signal line 216 are electrically connected to the m+1th analog switch 212, respectively. Further, by setting the potential of the (m+1)th selection signal line 215 to the H level and the potential of the m+1th inversion selection signal line 216 to the L level, the m+1th analog switch 212 can be electrically or non-conductive. Further, the potential of the mth selection signal line 213 and the potential of the m+1th selection signal line 215 are generated by decoding a specific bit in the memory address signal. In other words, either one is the H level and the other is the L level. Further, when the potential of the mth selection signal line 213 is the L level, the potential of the mth inversion selection signal line 214 is the H level, and when the potential of the mth selection signal line 213 is the H level, the mth inversion The potential of the selection signal line 214 is the L level. Similarly, when the potential of the m+1th selection signal line 215 is the L level, the potential of the m+1th inversion selection signal line 216 is the H level, and when the potential of the m+1th selection signal line 215 is the H level, the m+1th The potential of the phase selection signal line 216 is the L level.

The timing chart of the configuration of the mask ROM shown in FIG. 4 is the same as the configuration shown in FIG. 3 of the first embodiment mode. Therefore, in the present embodiment mode, the description of FIG. 3 described in the embodiment mode 1 is used. To carry out its description.

The structure of the mask ROM of FIG. 4 is different from the structure of FIG. 2 of Embodiment Mode 1 in that a precharge circuit is provided corresponding to each bit line in the structure of FIG. 2 of Embodiment Mode 1, and A precharge circuit 401 is provided in the mask ROM of 4 corresponding to a plurality of bit lines.

Therefore, in the circuit diagram of the mask ROM of Embodiment Mode 1 - FIG. 2 and the circuit diagram of the mask ROM of Embodiment Mode 2 - FIG. 4, the number of transistors of the precharge circuit of FIG. 4 is small. The timing chart of the mask ROM of FIGS. 2 and 4 is the same, and has the same function for reducing power consumption. Therefore, since the number of transistors of the precharge circuit is small, the mask ROM of FIG. 4 is superior to miniaturization. In other words, it can be considered that the semiconductor device having the mask ROM shown in FIG. 4 can provide a semiconductor device which is further miniaturized as compared with the semiconductor device having the mask ROM shown in FIG. 2.

By adopting the above configuration, it is possible to provide a semiconductor device in which a memory is mounted and which is low in power consumption and small in size.

In addition, this embodiment mode can be implemented in combination with other embodiment modes and other embodiments freely.

Example 1

The semiconductor device of the present invention can be applied to electronic devices having all fields of memory. In other words, the invention includes an electronic device having a memory. For example, examples of the electronic device using the semiconductor device of the present invention include a video camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, and an audio reproduction device (a car body sound, an audio component, etc.). ), computer, game machine, portable information terminal (mobile computer, mobile phone, portable game machine or e-book, etc.), or an image reproduction device having a recording medium (specifically, capable of playing a recording medium such as a digital universal optical disc (DVD) ) and the like, and having a display capable of displaying an image thereof, and the like. Specific examples of these electronic devices are shown in Figs. 8A to 8E.

8A and 8B illustrate a digital camera. Figure 8B shows the back side of Figure 8A. The digital camera includes a housing 2111, a display portion 2112, a lens 2113, an operation key 2114, a shutter release button 2115, and the like. In addition, the digital camera also has a removable memory 2116 and has a structure for storing data photographed using the digital camera in the memory 2116. The semiconductor device of the present invention can be applied to the memory 2116.

Further, Fig. 8C shows a mobile phone which is a representative example of the mobile terminal. The mobile phone includes a housing 2121, a display portion 2122, an operation key 2123, and the like. Further, the mobile phone has a removable memory 2125, and data, video, audio data, and the like of the telephone number of the mobile phone can be stored in the memory 2125 and reproduced. The semiconductor device of the present invention can be applied to the memory 2125.

Further, Fig. 8D shows a digital audio device which is a representative example of an audio device. The digital acoustic device shown in FIG. 8D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Alternatively, instead of the headset 2134, a headset or a wireless headset can be used. The semiconductor device of the present invention can be used for the memory portion 2132. For example, the operation portion 2133 can be operated by using a large-capacity memory having a storage capacity of 20 to 200 million bytes (GB), and image or audio (music) can be stored and reproduced. Further, the display unit 2131 can suppress the power consumption by displaying white characters on a black background. This is especially effective in carrying audio components. In addition, the memory portion 2132 may also be a removable structure.

In addition, FIG. 8E shows an electronic book (also referred to as electronic paper). The electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a memory portion 2144. In addition, the e-book can be equipped with a data machine inside the main body 2141, and can be a structure for transmitting and receiving information wirelessly. The semiconductor device of the present invention can be used for the memory portion 2144. For example, image or audio (music) can be stored and reproduced by operating the operation key 2143 using a memory having a storage capacity of 20 to 200 million bytes (GB). In addition, the memory portion 2144 may also be a removable structure.

As described above, the scope of application of the present invention is wide, and as long as it has a memory, it can be applied to electronic devices in all fields. Since the semiconductor device of the present invention consumes low power, it is possible to carry data in the battery-driven electronic device shown in FIGS. 8A to 8E without affecting the battery driving time.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes.

Example 2

In recent years, a small-sized semiconductor device (hereinafter, also referred to as a wireless chip) in which an ultra-small IC chip is combined with an antenna for wireless communication has attracted attention. By transmitting and receiving communication signals (working magnetic fields) using a wireless communication device (hereinafter referred to as a reader/writer), data can be written to or read from the wireless wafer.

As a field of application of the wireless chip, for example, product management in the distribution industry can be cited. At present, commodity management using bar codes and the like is the mainstream, however, since the barcode is optically read, when there is a mask, the data cannot be read. On the other hand, since the wireless chip reads data wirelessly, it can pass through the wireless communication signal, and the material can be read even if there is a mask. Therefore, product management such as higher efficiency and lower cost is expected. In addition, look forward to a wide range of applications, such as tickets, airline tickets, automatic payments and so on.

As the range of applications for wireless wafers expands, there is a growing need for wireless wafers with higher functionality. For example, it is expected to prevent data leakage to third parties by encrypting the data being sent and received. There are a method of performing decoding/encoding processing by hardware, a method of performing decoding/encoding processing by software, and a method of performing decoding/encoding processing by using hardware and software. In the processing method using hardware, the arithmetic circuit is constituted by a dedicated circuit for decoding/encoding. In the processing method using the software, the arithmetic circuit is constituted by a CPU (Central Processing Unit) and a large-scale memory, and the decoding/encoding program is executed by the CPU. In the processing method in which the hardware and software are used in combination, the arithmetic circuit is composed of a dedicated circuit, a CPU, and a memory, and the dedicated circuit performs a part of decoding/encoding operation processing, and the CPU executes other arithmetic processing programs. Either way, large-scale memory is installed in the wireless chip. By applying the present invention, it is possible to avoid an increase in power consumption as the capacity of the memory increases.

In the present embodiment, a wireless wafer having an encryption function is described as an example of the semiconductor device of the present invention, using FIGS. 9 and 10. 9 is a block diagram of a wireless wafer, and FIG. 10 is a layout view of a wireless wafer.

First, the block diagram structure of the wireless wafer will be described using FIG. In FIG. 9, the wireless wafer 1001 is composed of an arithmetic circuit 1006 including a CPU 1002, a ROM 1003, a RAM 1004, and a controller 1005, and an analog portion 1015 including an antenna 1007 and a resonance circuit 1008. A power supply circuit 1009, a reset circuit 1010, a clock generation circuit 1011, a demodulation circuit 1012, a modulation circuit 1013, and a power management circuit 1014. The controller 1005 is composed of a CPU interface (CPUIF) 1016, a control register 1017, a code extraction circuit 1018, and an encoding circuit 1019. Note that in FIG. 9, for simplification of explanation, the communication signals are respectively denoted as the reception signal 1020 and the transmission signal 1021; however, they are actually combined to constitute one signal, and the signals are simultaneously on the wireless wafer 1001 and read/write. Transmitted between the devices. After the received signal 1020 is received by the antenna 1007 and the resonant circuit 1008, it is demodulated by the demodulation circuit 1012. Further, the transmission signal 1021 is modulated by the modulation circuit 1013 and then transmitted by the antenna 1007.

In FIG. 9, when the wireless wafer 1001 is placed in a magnetic field generated by a communication signal, an induced electromotive force is generated by the antenna 1007 and the resonance circuit 1008. The induced electromotive force is held in the capacitor of the power supply circuit 1009, and the transmission capacitor stabilizes the potential, and the induced electromotive force is supplied to the respective circuits of the wireless wafer 1001 as the power supply voltage. The reset circuit 1010 generates an initial reset signal for the entire wireless wafer 1001. For example, the reset circuit 1010 generates a signal that is delayed in rise after the power supply voltage rises as a reset signal. The clock generation circuit 1011 changes the frequency and duty ratio of the clock signal corresponding to the control signal generated by the power management circuit 1014. The demodulation circuit 1012 detects the amplitude change of the received signal 1020 of the ASK system as the received data 1022 "0"/"1". The demodulation circuit 1012 is, for example, a low pass filter. Further, the modulation circuit 1013 transmits the transmitted data by changing the amplitude of the ASK-type transmission signal 1021. For example, in the case where the transmission material 1023 is "0", the resonance point of the resonance circuit 1008 is changed, thereby changing the amplitude of the communication signal. The power management circuit 1014 monitors the power supply voltage supplied from the power supply circuit 1009 to the power supply voltage of the arithmetic circuit 1006 or the current consumption in the arithmetic circuit 1006, thereby generating a control signal for changing the frequency and duty ratio of the clock signal in the clock generating circuit 1011. .

The operation of the wireless wafer of the present embodiment will be described below. First, the wireless chip 1001 receives the received signal 1020 having ciphertext data transmitted from the reader/writer. After the received signal 1020 is demodulated by the demodulation circuit 1012, it is separated into a control command, ciphertext data, etc. by the code extraction circuit 1018, and then stored in the control register 1017. Here, the control command is information for specifying the response of the wireless wafer 1001. For example, transmission of a unique ID number, work stop, decoding, and the like are specified. Here, it is assumed that a control instruction for decoding is received.

Next, in the arithmetic circuit 1006, the CPU 1002 decodes the ciphertext using the private key 1024 stored in the ROM 1003 in advance based on the decoding program stored in the ROM 1003. The decoded ciphertext (decoded text) is stored in the control register 1017. At this time, the RAM 1004 is used as a data storage area. Note that the CPU 1002 accesses the ROM 1003, the RAM 1004, and the control register 1017 via the CPU interface 1016. The CPU interface 1016 has a function of generating an access signal with respect to any of the ROM 1003, the RAM 1004, and the control register 1017 in accordance with an address required by the CPU 1002.

Finally, in the encoding circuit 1019, the transmission material 1023 is generated from the decoded text and modulated by the modulation circuit 1013, and the transmission signal 1021 is transmitted from the antenna 1007 to the reader/writer.

Further, in the present embodiment, the processing method using the software is described as the arithmetic method, that is, the method in which the arithmetic circuit is composed of the CPU and the large-scale memory and executes the program through the CPU; however, the arithmetic method may be appropriately selected according to the purpose. And based on this method, an arithmetic circuit is constructed. For example, as an arithmetic method, there are also a method of processing using a hardware and a method of using a combination of soft and hard bodies. In the processing method using hardware, the arithmetic processing is performed using an arithmetic circuit composed of a dedicated circuit that performs only specific processing. In the method of using a combination of hardware and software, the arithmetic circuit is composed of a dedicated circuit, a CPU, and a memory, and the dedicated circuit performs a part of arithmetic processing, and the CPU executes other arithmetic processing programs.

Next, the layout structure of the wireless wafer will be described using FIG. Note that, in FIG. 10, elements corresponding to the elements shown in FIG. 9 are denoted by the same reference numerals, and thus the description thereof will be omitted.

In FIG. 10, the FPC pad 1107 is an electrode pad group for attaching an FPC (Flexible Printed Circuit) to the wireless wafer 1001, and the antenna protrusion 1108 is an electrode pad for attaching an antenna (not shown). . Note that an overpressure can be applied to the antenna protrusion 1108 when the antenna is attached. Therefore, it is preferable that an element constituting a circuit such as a transistor is not disposed under the antenna protrusion 1108.

The FPC pad 1107 is mainly effective for use in defect analysis. In a wireless chip, the power supply voltage is obtained through a communication signal, so that the arithmetic circuit does not operate at all when a defect is generated, for example, in an antenna or a power supply circuit. Therefore, defect analysis is quite difficult. However, the arithmetic circuit can be operated by supplying a power supply voltage from the FPC to the wireless wafer 1001 via the FPC pad 1107 and inputting an arbitrary electrical signal instead of the electrical signal supplied from the antenna. Therefore, the defect analysis can be performed efficiently.

In addition, it is more effective to arrange the FPC pad 1107 so that measurement using the detector can be performed. Specifically, in the FPC pad 1107, measurement by the detector can be performed by arranging the electrode pads in accordance with the pitch of the probe probes. By using the detector, the processing steps for attaching the FPC can be reduced during defect analysis. Further, the measurement can be performed even in a state in which a plurality of wireless wafers are formed on the substrate; therefore, the processing steps divided into the respective wireless wafers can also be reduced. Furthermore, quality inspection of the wireless wafer can be performed prior to the step of attaching the antenna in mass production. Therefore, defective defects can be screened at an earlier stage in the production process, thereby reducing production costs.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes. In other words, in a memory mounted as a semiconductor device in a wireless wafer, individual bit lines can be selectively precharged. In other words, by not precharging the bit line irrelevant to the reading of data from the memory, it is possible to provide a semiconductor device in which a memory having low power consumption is mounted.

Example 3

In the present embodiment, a method of manufacturing the wireless wafer shown in the above embodiment will be described. The respective circuits constituting the wireless wafer according to the present invention may be fabricated from a thin film transistor. The present embodiment shows a method of forming a circuit constituting a wireless wafer from a thin film transistor, and transferring the circuit from a substrate for manufacturing a thin film transistor to a substrate having flexibility to fabricate a flexible wireless wafer.

In the present embodiment, a P-channel type TFT (also referred to as a P-TFT) constituting an inverter or the like, an N-channel type TFT (also referred to as an N-TFT), and a thin film transistor are typically shown. The antenna is used as a circuit constituting a wireless chip. A method of manufacturing a wireless wafer will be described hereinafter using a cross-sectional view shown in FIGS. 11A to 13B.

First, a peeling layer 1303 is formed on one surface of the substrate 1301 with an insulating film 1302 interposed therebetween, followed by lamination to form an insulating film 1304 and a semiconductor film 1305 (for example, a film including amorphous germanium) serving as a base film (refer to FIG. 11A). . In addition, the insulating film 1302, the peeling layer 1303, the insulating film 1304, and the amorphous semiconductor film 1305 may be continuously formed.

The substrate 1301 is a substrate selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate, etc.), a ceramic substrate, a semiconductor substrate such as a germanium substrate, or the like. Further, as the plastic substrate, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether oxime (PES), or propylene can be selected. Further, in the method, the peeling layer 1303 is formed on the entire surface of the substrate 1301 with the insulating film 1302 interposed therebetween, but may be selectively provided by the photolithography method after the peeling layer is provided on the entire surface of the substrate 1301 as needed. A release layer is formed.

The insulating film 1302 and the insulating film 1304 are transmitted by using a CVD method, a sputtering method, or the like, and using yttrium oxide, lanthanum nitride, yttrium oxynitride (SiO x N y ) (x>y>0), yttrium oxynitride (SiN x O). y ) (x>y>0) is formed of an insulating material. For example, in the case where the insulating film 1302 and the insulating film 1304 are formed in a two-layer structure, a hafnium oxynitride film is preferably formed as the first insulating film, and a hafnium oxynitride film is formed as the second insulating film. Further, a tantalum nitride film may be formed as the first insulating film, and a hafnium oxide film may be formed as the second insulating film. The insulating film 1302 functions as a barrier layer for preventing impurity elements from being mixed from the substrate 1301 into the peeling layer 1303 or an element formed thereon, and the insulating film 1304 serves to prevent impurity elements from being mixed from the substrate 1301 and the peeling layer 1303 to be formed in the peeling layer. A barrier layer in the component on 1303. Thus, by forming the insulating films 1302 and 1304 serving as the barrier layers, it is possible to prevent the alkali metal or alkaline earth metal such as Na in the substrate 1301 and the impurity elements in the peeling layer 1303 from being negatively affected to be formed on the peeling layer 1303. Components. Further, when quartz is used as the substrate 1301, the insulating films 1302 and 1304 may not be formed.

The peeling layer 1303 can be a metal film, a laminated structure of a metal film and a metal oxide film, or the like. The metal film may be formed as a single layer or a laminate of a film selected from the group consisting of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt. (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), and iridium (Ir), or with the above elements as the main component Alloy material or compound material. Further, these materials can be formed by various CVD methods such as a sputtering method or a plasma CVD method. As the metal film and a laminated structure of metal oxide film through, or N 2 O plasma treatment in an atmosphere after the formation of the metal film in an oxygen atmosphere or a heat treatment and in an atmosphere of N 2 O in an oxygen atmosphere An oxide or oxynitride of the metal film may be provided on the surface of the metal film. For example, when a tungsten film is provided as a metal film by a sputtering method, a CVD method, or the like, a metal oxide film made of a tungsten oxide can be formed on the surface of the tungsten film by plasma treatment of the tungsten film. In this case, the oxide of tungsten is represented by WO x , where x is 2 to 3. There are cases where x is 2 (WO 2 ), x is 2.5 (W 2 O 5 ), x is 2.75 (W 4 O 11 ), and x is 3 (WO 3 ). When the oxide of tungsten is formed, the above-mentioned value of x is not particularly limited, and it is preferred to determine which oxide is formed based on the etching rate or the like. Further, for example, after forming a metal film (for example, tungsten), an insulating film of yttrium oxide (SiO 2 ) or the like may be provided on the metal film by a sputtering method, and a metal oxide may be formed on the metal film (for example, Tungsten oxide is formed on tungsten). Further, as the plasma treatment, for example, the above-described high-density plasma treatment may be performed. Further, in addition to the metal oxide film, a metal nitride or a metal oxynitride may be used. In this case, the metal film may be subjected to plasma treatment or heat treatment in a nitrogen atmosphere or a nitrogen gas and oxygen atmosphere.

The amorphous semiconductor film 1305 is formed by a sputtering method, an LPCVD method, a plasma CVD method or the like with a thickness of 25 to 200 nm (preferably 30 to 150 nm).

Next, the amorphous semiconductor film 1305 is irradiated with a laser beam to be crystallized. Further, the amorphous semiconductor film 1305 may be crystallized by irradiation with a combined laser beam, thermal crystallization by RTA or an annealing furnace, or a thermal crystallization method using a metal element for promoting crystallization. Thereafter, the obtained crystalline semiconductor film is etched into a desired shape, thereby forming crystalline semiconductor films 1305a to 1305f, and a gate insulating film 1306 is formed covering the semiconductor films 1305a to 1305f (refer to FIG. 11B).

The gate insulating film 1306 is used by using a CVD method, a sputtering method, or the like and using yttrium oxide, lanthanum nitride, yttrium oxynitride (SiO x N y ) (x>y>0), yttrium oxynitride (SiN x O y ). An insulating material such as (x>y>0) is formed. For example, in the case where the gate insulating film 1306 is formed in a two-layer structure, a hafnium oxynitride film is preferably formed as the first insulating film, and a hafnium oxynitride film is formed as the second insulating film. Further, a ruthenium oxide film may be formed as the first insulating film, and a tantalum nitride film may be formed as the second insulating film.

Hereinafter, an example of a method of manufacturing the crystalline semiconductor films 1305a to 1305f will be briefly described. First, an amorphous semiconductor film of 50 to 60 nm thick is formed using a plasma CVD method. Next, a solution containing a metal element for promoting nickel crystallization is held on the amorphous semiconductor film, and then the amorphous semiconductor film is subjected to dehydrogenation treatment (at 500 ° C for one hour) and thermal crystallization treatment (at 550). At ° C for four hours) to form a crystalline semiconductor film. Thereafter, the laser beam is irradiated and the photolithography method is used to form the crystalline semiconductor films 1305a to 1305f. Further, it is also possible to perform crystallization of the amorphous semiconductor film only by irradiation of the laser beam without performing thermal crystallization of a metal element which promotes crystallization.

As the laser oscillator for crystallization, a continuous oscillation type laser beam (CW laser beam) or a pulse oscillation type laser beam (pulsed laser beam) can be used. The laser beam that can be used here is a laser beam that is oscillated from one or more of the following lasers: a gas laser such as an Ar laser, a Kr laser, an excimer laser, etc. Single crystal YAG, YVO 4 , forsterite (Mg 2 SiO 4 ), YAlO 3 and added with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm and Ta as dopants GdVO 4 , or polycrystalline (ceramic) YAG, Y 2 O 3 , YVO 4 , YAlO 3 and GdVO 4 as medium lasers; glass lasers; ruby lasers; marbled lasers; Ti: Sapphire laser; copper vapor laser; and gold vapor laser. By irradiating the fundamental wave of the above-described laser beam and the laser beam of the second to fourth harmonics of the fundamental wave, crystals having a large particle diameter can be obtained. For example, a second higher harmonic (532 nm) or a third higher harmonic (355 nm) of a Nd:YVO 4 laser (the fundamental wave is 1064 nm) can be used. At this time, the power density of the laser needs to be about 0.01 to 100 MW/cm 2 (preferably 0.1 to 10 MW/cm 2 ). Further, the irradiation is performed at a scanning speed of about 10 to 2000 cm/sec. In addition, single crystal YAG, YVO 4 , forsterite (Mg 2 SiO 4 ), YAlO 3 added with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm and Ta as dopants And lasers of GdVO 4 , or polycrystalline (ceramic) YAG, Y 2 O 3 , YVO 4 , YAlO 3 and GdVO 4 as media; Ar ion lasers; and Ti: sapphire lasers can make thunder The laser beam can be oscillated at an oscillation frequency of 10 MHz or more by performing Q-switching operation or mode-locking. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the next pulse is irradiated to the semiconductor film during the period from the laser film to the solidification of the semiconductor film. Therefore, unlike the case of using a pulsed laser having a low oscillation frequency, the interface between the solid and the liquid can be continuously moved in the semiconductor film, and therefore, crystal grains continuously growing in the scanning direction can be obtained.

Further, the high-density plasma treatment may be performed on the semiconductor films 1305a to 1305f to oxidize or nitride the surface to form the gate insulating film 1306. For example, it is formed by plasma treatment by introducing a rare gas such as He, Ar, Kr, Xe, or the like with a mixed gas of oxygen, nitrogen oxide (NO 2 ), ammonia, nitrogen, hydrogen, or the like. Excitation of the plasma in this case is carried out by introduction of microwaves, and high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by an oxy group (which also includes an OH group) or a nitrogen group (including a case where an NH group is formed) which is formed by the high-density plasma.

An insulating film of 1 to 20 nm representing 5 to 10 nm is formed on the semiconductor film by the treatment using the high-density plasma as described above. Since the reaction in this case is a solid phase reaction, the dielectric density of the insulating film and the semiconductor film can be made extremely low. Such high-density plasma treatment can directly oxidize (or nitride) a semiconductor film (crystalline germanium or polycrystalline germanium), so that the thickness unevenness of the formed insulating film can be made extremely small. In addition, even if the grain interface of the crystalline germanium is oxidized, it does not strengthen, so it is in an ideal state. That is, the surface of the semiconductor film is solid-phase oxidized by the high-density plasma treatment shown here, and an insulating film having good uniformity and low dielectric density can be formed without causing an abnormal oxidation reaction in the grain interface.

The gate insulating film may use only an insulating film formed by high-density plasma treatment, or may deposit an insulating film of yttrium oxide, yttrium oxynitride, tantalum nitride or the like on the plasma by thermal plasma or thermal reaction. Cascade. In any case, it is also possible to reduce the unevenness of the characteristics of the transistor which is formed in a part or all portions of its gate insulating film including an insulating film formed by a high-density plasma.

Further, the semiconductor films 1305a to 1305f obtained by irradiating a semiconductor film with a continuous oscillation laser or a laser beam oscillating at a frequency of 10 MHz or more and scanning it in one direction have crystals grown in the scanning direction of the light beam thereof. characteristic. By arranging the transistor in such a manner that its scanning direction corresponds to the channel length direction (the direction in which the carriers flow when the channel forming region is formed), and combining the above-mentioned gate insulating layers, a characteristic unevenness and field effect can be obtained. Thin film transistor (TFT) with high mobility.

Next, a first conductive film and a second conductive film are laminated on the gate insulating film 1306. Here, the first conductive film is formed by a CVD method, a sputtering method, or the like with a thickness of 20 to 100 nm. The second conductive film is formed with a thickness of 100 to 400 nm. The first conductive film and the second conductive film are selected from the group consisting of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and niobium (Nb). An element such as an alloy material or a compound material containing the above elements as a main component. Alternatively, the first conductive film and the second conductive film are formed of a semiconductor material typified by polycrystalline germanium doped with an impurity element such as phosphorus. As an example of the combination of the first conductive film and the second conductive film, a tantalum nitride film and a tungsten film, a tungsten nitride film, and a tungsten film or a molybdenum nitride film, a molybdenum film, or the like can be given. Since tungsten and tantalum nitride have high heat resistance, heat treatment for hot start can be performed after forming the first conductive film and the second conductive film. Further, in the case of not a two-layer structure but a three-layer structure, a laminated structure composed of a molybdenum film, an aluminum film, and a molybdenum film is preferably used.

Next, a mask made of a resist is formed by photolithography, and an etching process for forming a gate electrode and a gate line is performed to form a gate electrode 1307 over the semiconductor films 1305a to 1305f. Here, an example in which the first conductive film 1307a and the second conductive film 1307b are provided as a gate electrode 1307 in a stacked structure is shown.

Next, an impurity element imparting an n-type is added to the semiconductor films 1305a to 1305f at a low concentration by an ion doping method or an ion implantation method using the gate electrode 1307 as a mask, and then selectively formed by the light lithography by the photoresist A mask composed of a solvent is added with a p-type impurity element at a high concentration. As the impurity element imparting n-type, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element imparting n-type, and it is selectively introduced into the semiconductor films 1305a to 1305f at a concentration of 1 × 10 15 to 1 × 10 19 /cm 3 to form a presentation n Type impurity region 1308. Further, boron (B) is used as the impurity element imparting the p-type, and it is selectively introduced into the semiconductor films 1305c and 1305e at a concentration of 1 × 10 19 to 1 × 10 20 /cm 3 to form a presentation p. A type impurity region 1309 (refer to FIG. 11C).

Next, an insulating film is formed covering the gate insulating film 1306 and the gate electrode 1307. The insulating film is formed by forming a film of an inorganic material such as an oxide of cerium, lanthanum or cerium, or a film containing an organic material such as an organic resin in a single layer or a laminate by a plasma CVD method or a sputtering method. Next, the insulating film is selectively etched through anisotropic etching mainly in the vertical direction to form an insulating film 1310 (also referred to as a sidewall) which is in contact with the side surface of the gate electrode 1307. The insulating film 1310 is used as a mask for doping when an LDD (lightly doped germanium) region is formed.

Next, using a mask made of a resist formed by a photolithography method, a gate electrode 1307, and an insulating film 1310 as a mask, an impurity element imparting an n-type is added to the semiconductor films 1305a, 1305b, and 1305d at a high concentration. In 1305, to form an impurity region 1311 exhibiting an n-type. Here, phosphorus (P) is used as the impurity element imparting n-type, and it is selectively introduced into the semiconductor film 1305a, 1305b, 1305d, 1305f at a concentration of 1 × 10 19 to 1 × 10 20 /cm 3 . To form an impurity region 1311 exhibiting an n-type, the concentration of the impurity region being higher than the concentration of the impurity region 1308.

Through the above method, N-channel type thin film transistors 1300a, 1300b, 1300d, and 1300f, and P-channel type thin film transistors 1300c and 1300e are formed (refer to FIG. 11D).

The N-channel type thin film transistor 1300a is formed with a channel formation region in a region of the semiconductor film 1305a overlapping the gate electrode 1307, and an impurity constituting the source region or the germanium region is formed in a region not overlapping the gate electrode 1307 and the insulating film 1310. The region 1311 and a low concentration impurity region (LDD region) are formed in a region overlapping the insulating film 1310 and between the channel formation region and the impurity region 1311. Further, a channel formation region, a low concentration impurity region, and an impurity region 1311 are also formed in the N channel type thin film transistors 1300b, 1300d, and 1300f.

The P-channel type thin film transistor 1300c is formed with a channel formation region in a region of the semiconductor film 1305c overlapping the gate electrode 1307, and an impurity region 1309 constituting a source region or a germanium region is formed in a region not overlapping the gate electrode 1307. Further, the P channel type thin film transistor 1300e is similarly formed with a channel formation region and an impurity region 1309. Further, here, the LDD region is not provided in the P channel type thin film transistors 1300c and 1300e, but the LDD region may be provided in the P channel type thin film transistor, or the LDD region may not be provided in the N channel type thin film transistor.

Next, an insulating film is formed in a single layer or a laminate by covering the semiconductor films 1305a to 1305f, and the gate electrode 1307 and the like, and a conductive film 1313 is formed on the insulating film, the conductive film 1313 and the thin film transistors 1300a to 1300f. The impurity regions 1309, 1311 of the source region or the germanium region are electrically connected (refer to FIG. 12A). The insulating film is made of an inorganic material such as a cerium oxide or a cerium nitride by a CVD method, a sputtering method, a SOG method, a droplet discharge method, a screen printing method, or the like; a polyimine, a polyamide, or a styrene ring; An organic material such as an ene, a propylene, or an epoxy; or a siloxane or the like is formed in a single layer or a laminate. Here, the insulating film is provided in two layers, a hafnium oxynitride film is formed as the first layer insulating film 1312a, and a hafnium oxynitride film is formed as the second layer insulating film 1312b. In addition, the conductive film 1313 may form a source electrode or a drain electrode of the thin film transistors 1300a to 1300f.

In addition, it is preferable to perform the recovery of the crystallinity of the semiconductor film, the activation of the impurity element added to the semiconductor film, or the formation of the insulating film 1312a, 1312b or after the formation of one or more of the insulating films 1312a, 1312b, and The hydrogenation of the semiconductor film is a heat treatment for the purpose. Preferably, a thermal annealing method, an electro-radiation annealing method, or an RTA method is used for the heat treatment.

The conductive film 1313 is transmitted through a CVD method, a sputtering method, or the like and is selected from the group consisting of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), An element in copper (Cu), gold (Au), silver (Ag), manganese (Mn), niobium (Nd), carbon (C), antimony (Si), or an alloy material containing the above element as a main component or The compound material is formed in a single layer or a laminate. The alloy material containing aluminum as its main component corresponds to, for example, a material whose main component is aluminum and contains nickel, or an alloy material whose main component is aluminum and contains nickel or one or both of carbon and niobium. As the conductive film 1313, for example, a laminate structure using a barrier film, an aluminum-germanium (Al-Si) film and a barrier film; or a barrier film, an aluminum-germanium (Al-Si) film, or titanium nitride (TiN) is preferable. a laminated structure of a film and a barrier film. Further, the barrier film corresponds to a film composed of a nitride of titanium, titanium, molybdenum, or a nitride of molybdenum. Since aluminum and aluminum tantalum have low electrical resistance and are inexpensive, they are an optimum material for forming the conductive film 1313. In addition, it is possible to prevent the occurrence of hillocks of aluminum or aluminum bismuth when the barrier layers of the upper layer and the lower layer are provided. Further, when a barrier film is formed of titanium or a highly reductive element, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film can be reduced to obtain better contact with the crystalline semiconductor film.

Next, an insulating film 1314 is formed over the conductive film 1313, and conductive films 1315a, 1315b are formed on the insulating film 1314, and the conductive films 1315a, 1315b and the conductive film constituting the source electrode or the drain electrode of the thin film transistors 1300a, 1300f 1313 is electrically connected. Further, a conductive film 1316 is formed which is electrically connected to the conductive film 1313 constituting the source electrode or the drain electrode of the thin film transistors 1300b and 1300e, respectively. In addition, the conductive films 1315a, 1315b and the conductive film 1316 may be simultaneously formed of the same material. The conductive films 1315a, 1315b and the conductive film 1316 may be formed using any of the materials for the above-described conductive film 1313.

Next, a conductive film 1317 functioning as an antenna is formed electrically connected to the conductive film 1316 (refer to FIG. 12B).

The insulating film 1314 can be formed by a CVD method, a sputtering method, or the like and in a single layer or a stacked structure using an insulating film containing oxygen or nitrogen such as yttrium oxide (SiO x ), tantalum nitride (SiN x ), or oxygen nitrogen. Plutonium (SiO x N y ) (x>y>0) and yttrium oxynitride (SiN x O y ) (x>y>0); carbon-containing films such as DLC (diamond-like carbon); organic materials such as Epoxy, polyimine, polyamine, polyvinyl phenol, benzocyclobutene, propylene, etc.; or a phthalate material such as a decane resin. Note that the siloxane material corresponds to a material containing a Si-O-Si bond. The skeleton structure of the siloxane is composed of a bond of cerium (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. As the substituent, a fluorine group can also be used. Alternatively, as the substituent, an organic group containing at least hydrogen and a fluorine group can also be used.

The conductive film 1317 is formed by a printing method such as a CVD method, a sputtering method, screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like, and is formed in a single layer or a laminate using the following conductive material: From aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), tantalum (Ta) and molybdenum (Mo) An element in the alloy, or an alloy material or a compound material containing these elements as a main component.

For example, in the case where the conductive film 1317 serving as an antenna is formed by screen printing, a conductive paste may be selectively printed by dissolving conductive particles having a particle diameter of several nm to several tens of nm or Dispersed in an organic resin. As the conductive particles, silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo), and titanium (Ti) can be used. Any one or more of metal particles, silver halide fine particles or dispersible nanoparticles. In addition, as the organic resin contained in the conductive paste, one or more of a binder selected from metal particles, a solvent, a dispersant, and an organic resin used as a coating agent can be used. An organic resin such as an epoxy resin or an anthrone resin can be typically used. Further, in forming the conductive film, it is preferred to perform baking after the conductive paste is pushed out. For example, in the case where fine particles containing silver as a main component (for example, a particle diameter of 1 nm or more and 100 nm or less) is used as a material of the conductive paste, it is possible to obtain a conductive property by baking and solidifying in a temperature range of 150 to 300 ° C. membrane. Further, fine particles containing solder or lead-free solder as a main component may be used, and in this case, fine particles having a particle diameter of 20 μm or less are preferably used. Solder and lead-free solder have the advantage of low cost.

In addition, the conductive films 1315a, 1315b can be used as wirings electrically connected to the battery included in the semiconductor device of the present invention in the subsequent process. In addition, when the conductive film 1317 serving as an antenna is formed, a conductive film may be additionally formed electrically connected to the conductive films 1315a, 1315b to use the conductive film as a wiring connected to the battery.

Next, after the insulating film 1318 is formed to cover the conductive film 1317, a layer including the thin film transistors 1300a to 1300f, the conductive film 1317, and the like (hereinafter referred to as "element forming layer 1319") is peeled off from the substrate 1301. Here, after the opening is formed by irradiating a laser beam (for example, UV light) in a region avoiding the thin film transistors 1300a to 1300f (refer to FIG. 12C), the element forming layer 1319 can be peeled off from the substrate 1301 by physical force. Further, before the element forming layer 1319 is peeled off from the substrate 1301, an etchant may be introduced into the formed opening portion to selectively remove the peeling layer 1303. As the etchant, a gas or a liquid containing a halogen fluoride or a halogenated compound is used. For example, chlorine trifluoride (ClF 3 ) is used as a gas containing a halogen fluoride. When chlorine trifluoride is used, the element formation layer 1319 is in a state of being peeled off from the substrate 1301. In addition, the release layer 1303 may be partially left without being completely removed. By leaving a part of the peeling layer 1303, the consumption of the etchant can be reduced and the processing time required to remove the peeling layer can be shortened. Further, the element forming layer 1319 may remain on the substrate 1301 even after the peeling layer 1303 has been removed. Further, the cost can be reduced by reusing the substrate 1301 from which the element formation layer 1319 is peeled off.

The insulating film 1318 can be formed by a CVD method, a sputtering method, or the like and formed of a single layer or a stacked structure using an insulating film containing oxygen or nitrogen such as yttrium oxide (SiO x ), tantalum nitride (SiN x ), or oxygen nitrogen. Plutonium (SiO x N y ) (x>y>0) and yttrium oxynitride (SiN x O y ) (x>y>0); carbon-containing films such as DLC (diamond-like carbon); organic materials such as Epoxy, polyimine, polyamine, polyvinyl phenol, benzocyclobutene, propylene, etc.; or a phthalate material such as a decane resin.

In the present embodiment, after the opening is formed in the element forming layer 1319 by the irradiation of the laser beam, the first film is bonded to one surface of the element forming layer 1319 (the surface on which the insulating film 1318 is exposed). 1320, the element formation layer 1319 is then peeled off from the substrate 1301 (refer to FIG. 13A).

Next, the second film 1321 is bonded to the other surface (surface exposed by peeling) of the element forming layer 1319, and then one or both of them are subjected to heat treatment and pressure treatment to adhere the second film 1321 (refer to Figure 13B). As the first film 1320 and the second film 1321, a hot melt film or the like can be used.

As the first film 1320 and the second film 1321, a film subjected to an antistatic treatment to prevent static electricity or the like (hereinafter referred to as an antistatic film) can also be used. Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film in which an antistatic material is bonded, and the like. The film provided with the antistatic material may be a film having an antistatic material on its surface or a film having antistatic materials on both surfaces. Moreover, for a film provided with an antistatic material on one surface, a surface provided with an antistatic material may be attached to the inside or the outside of the film. In addition, the antistatic material may be disposed on the entire surface or part of the surface of the film. As the antistatic material herein, a metal, an oxide of indium and tin (ITO), or a surfactant such as an amphoteric surfactant, a cationic surfactant, a nonionic surfactant, or the like can be used. Further, as the antistatic material, a resin material or the like containing a crosslinked copolymer polymer having a carboxyl group and a polyamino base in a side chain may be used in addition to the above materials. The antistatic film can be obtained by laminating, blending or coating these materials on a film. By using an antistatic film seal, the semiconductor element can be prevented from being adversely affected by static electricity or the like from the outside when it is treated as a product.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes. In other words, in the memory mounted in the semiconductor device, the respective bit lines can be selectively precharged. In other words, by not precharging the bit line irrelevant to the reading of data from the memory, it is possible to provide a semiconductor device in which a memory having low power consumption is mounted.

Example 4

In the present embodiment, a method of manufacturing a wireless wafer different from the above embodiment will be described. The transistor of the present invention may be composed of a thin film transistor on the insulating substrate described in the above embodiment, or may be composed of a MOS transistor on a single crystal substrate.

In the present embodiment, a P-channel type TFT (also referred to as "Pch-TFT") constituting an inverter or the like and an N-channel type TFT (also referred to as Nch-TFT) are representatively shown as a circuit constituting a wireless wafer. . Hereinafter, a method of manufacturing a wireless wafer will be described using the cross-sectional views shown in FIGS. 14A to 16.

First, regions 2304 and 2306 (hereinafter also referred to as regions 2304 and 2306) of spacer elements are formed on the semiconductor substrate 2300 (see FIG. 14A). The regions 2304, 2306 provided on the semiconductor substrate 2300 are respectively separated by an insulating film 2302 (also referred to as a field oxide film). In addition, an example is shown here in which a single crystal Si substrate having an n conductivity type is used as the semiconductor substrate 2300, and a p well 2307 is disposed in a region 2306 of the semiconductor substrate 2300.

Further, it can be used as the substrate 2300 as long as it is a semiconductor substrate, and is not particularly limited. For example, a single crystal germanium substrate having an n or p conductivity type, a compound semiconductor substrate (a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, a sapphire substrate, a ZnSe substrate, etc.), a paste method or SIMOX (oxygen ion implantation isolation) may be used. An SOI (Insulator Upload) substrate manufactured by the method.

For the element isolation regions 2304, 2306, a selective oxidation method (LOCOS method) or a trench isolation method or the like can be suitably used.

In addition, a p-well can be formed in the region 2306 of the semiconductor substrate 2300 by selectively introducing an impurity element having a p-conductivity type into the region 2306 of the semiconductor substrate 2300. As the impurity element exhibiting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

In addition, in the present embodiment, since the semiconductor substrate having the n-conductivity type is used as the semiconductor substrate 2300, the impurity element is not introduced into the region 2304, however, an impurity element exhibiting an n-type may be introduced to form the n-well in the region 2304. As the impurity element exhibiting an n-type, phosphorus (P) or arsenic (As) or the like can be used. On the other hand, when a semiconductor substrate having a p-conductivity type is used, it is also possible to have a structure in which an impurity element exhibiting an n-type is introduced in the region 2304 to form an n-well, and an impurity element is not introduced into the region 2306.

Next, insulating films 2332 and 2334 are formed in the covering regions 2304 and 2306, respectively (see FIG. 14B).

The insulating films 2332 and 2334 can oxidize the surfaces of the regions 2304 and 2306 provided on the semiconductor substrate 2300 by heat treatment, for example, and form the insulating films 2332 and 2334 from the hafnium oxide film. Alternatively, the surface of the yttrium oxide film may be nitrided by forming a ruthenium oxide film by a thermal oxidation method, and a ruthenium oxide film and a film having oxygen and nitrogen (a yttrium oxynitride film) may be formed in a stacked structure. ).

Further, as described above, the insulating films 2332 and 2334 may be formed using plasma treatment. For example, by oxidizing or nitriding the surface of the regions 2304, 2306 provided on the semiconductor substrate 2300 by high-density plasma treatment, a yttrium oxide (SiO x ) film or a tantalum nitride (SiN x ) film may be formed as an insulating layer. Membrane 2332, 2334. Alternatively, the surface of the regions 2304 and 2306 may be oxidized by high-density plasma treatment, and then subjected to high-density plasma treatment to perform nitriding treatment. In this case, a hafnium oxide film is formed in contact with the surfaces of the regions 2304, 2306, and a hafnium oxynitride film is formed on the hafnium oxide film, whereby the insulating films 2332, 2334 are laminated with a hafnium oxide film and hafnium oxynitride. Membrane of the membrane. Alternatively, the ruthenium oxide film may be formed on the surfaces of the regions 2304 and 2306 by a thermal oxidation method, and then subjected to oxidation treatment or nitridation treatment by high-density plasma treatment.

In addition, the insulating films 2332, 2334 formed in the regions 2304, 2306 of the semiconductor substrate 2300 function as a gate insulating film in the transistor which is completed later.

Next, a conductive film is formed covering the insulating films 2332 and 2334 formed over the regions 2304 and 2306 (refer to FIG. 14C). Here, an example in which the conductive film 2336 and the conductive film 2338 are laminated in this order as a conductive film is shown. Of course, the conductive film may be formed in a single layer or a laminated structure of three or more layers.

The conductive films 2336, 2338 may be formed using a material selected from the group consisting of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and tantalum ( An element such as Nb) or an alloy material or a compound material containing these elements as a main component. Further, a metal nitride film obtained by nitriding these elements may be used. Further, it is also possible to form a semiconductor material typified by polycrystalline germanium doped with an impurity element such as phosphorus.

Here, the conductive film 2336 is formed using tantalum nitride, and the conductive film 2338 is formed in a stacked structure using tungsten thereon. In addition, as the conductive film 2336, a single layer or a laminated film selected from tungsten nitride, molybdenum nitride or titanium nitride may be used, and as the conductive film 2338, a single layer or a stack selected from ruthenium, molybdenum or titanium may be used. Layer film.

Next, by selectively etching and removing the conductive films 2336 and 2338 which are laminated, the conductive films 2336 and 2338 are left over a portion of the regions 2304 and 2306 to form the gate electrodes 2340 and 2342, respectively (refer to FIG. 15A). .

Next, a resist mask 2348 is selectively formed in the capping region 2304, and an impurity element is introduced in the region 2306 with the resist mask 2348 and the gate electrode 2342 as a mask to form an impurity region (refer to FIG. 15B). ). As the impurity element, an impurity element imparting an n-type or an impurity element imparting a p-type is used. As the impurity element exhibiting an n-type, phosphorus (P) or arsenic (As) or the like can be used. As the impurity element exhibiting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Phosphorus (P) is used here as an impurity element.

In FIG. 15B, an impurity region 2352 and a channel formation region 2350 are formed in the region 2306 by introducing an impurity element, and the impurity region 2352 forms a source region or a germanium region.

Next, a resist mask 2366 is selectively formed in the capping region 2306, and an impurity element is introduced in the region 2304 with the resist mask 2366 and the gate electrode 2340 as a mask to form an impurity region (refer to FIG. 15C). ). As the impurity element, an impurity element imparting an n-type or an impurity element imparting a p-type is used. As the impurity element exhibiting an n-type, phosphorus (P) or arsenic (As) or the like can be used. As the impurity element exhibiting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (for example, boron (B)) having a conductivity type different from that of the impurity element introduced into the region 2306 in FIG. 15B is introduced. As a result, an impurity region 2370 and a channel formation region 2368 are formed in the region 2304, which forms a source region or a germanium region.

Next, a second insulating film 2372 is formed over the insulating films 2332, 2334, the gate electrodes 2340, 2342, and a wiring 2374 is formed which is formed in the regions 2304, 2306 respectively formed on the second insulating film 2372 The impurity regions 2352, 2370 are electrically connected (refer to FIG. 16).

The second insulating film 2372 may be formed by a CVD method, a sputtering method, or the like and in a single layer or a stacked structure using an insulating film containing oxygen or nitrogen such as yttrium oxide (SiO x ), tantalum nitride (SiN x ), Bismuth oxynitride (SiO x N y ) (x>y>0) and niobium oxynitride (SiN x O y ) (x>y>0); carbon-containing films such as DLC (diamond-like carbon); organic Materials such as epoxy, polyimine, polyamine, polyvinyl phenol, benzocyclobutene and propylene, etc.; or oxirane materials such as decane resin. Note that the siloxane material corresponds to a material containing a Si-O-Si bond. The skeleton structure of the siloxane is composed of a bond of cerium (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. As the substituent, a fluorine group can also be used. Alternatively, as the substituent, an organic group containing at least hydrogen and a fluorine group can also be used.

The wiring 2374 is formed by a CVD method, a sputtering method, or the like and is formed in a single layer or a laminate using a material selected from the group consisting of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), and nickel. Elements in (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), niobium (Nd), carbon (C), and antimony (Si), or The element is an alloy material or a compound material which is a main component. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel or one or both of carbon and niobium. The wiring 2374 preferably adopts a structure such as a barrier film, an aluminum-iridium (Al-Si) film, and a stacked structure of a barrier film; a barrier film, an aluminum-iridium (Al-Si) film, and a titanium nitride (TiN) film. And a laminate structure of the barrier film. Further, the barrier film corresponds to a film composed of a nitride of titanium, titanium, or a nitride of molybdenum or molybdenum. Since aluminum and aluminum tantalum have low resistance values and are inexpensive, they are most suitable as a material for forming the wiring 2374. In addition, by providing the barrier layers of the upper and lower layers, it is possible to prevent the occurrence of hillocks of aluminum or aluminum bismuth. Further, by forming a barrier film made of titanium having a highly reducing element, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film can be reduced to be in good contact with the crystalline semiconductor film.

Further, the structure of the transistor constituting the semiconductor device of the present invention is not limited to the structure shown in the drawing. For example, a transistor having an inverted staggered structure, a fin FET structure, or the like can be employed. The fin FET structure is excellent in suppressing the short channel effect generated together with the refinement of the transistor size.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes. In other words, in the memory mounted in the semiconductor device, the respective bit lines can be selectively precharged. In other words, by not precharging the bit line irrelevant to the reading of data from the memory, it is possible to provide a semiconductor device in which a memory having low power consumption is mounted.

Example 5

This embodiment explains a method of manufacturing a wireless wafer different from the above embodiment. The transistor in the semiconductor device of the present invention may be formed of a MOS transistor provided through a manufacturing method different from the MOS transistor on the single crystal substrate described in the above embodiment.

In the present embodiment, a P-channel type TFT (also referred to as "Pch-TFT") constituting an inverter or the like and an N-channel type TFT (also referred to as "Nch-TFT") are shown as circuit representatives constituting the wireless wafer. . Hereinafter, a method of manufacturing a wireless wafer will be described using a cross-sectional view shown in FIGS. 17A to 20B.

First, an insulating film is formed on the substrate 2600. Here, single crystal Si having an n conductivity type is used as the substrate 2600, and an insulating film 2602 and an insulating film 2604 are formed on the substrate 2600 (refer to FIG. 17A). For example, the substrate 2600 is heat-treated to form a silicon oxide (SiO x) as the insulating film 2602, and forming a silicon nitride (SiN x) film using a CVD method on the insulating film 2602.

In addition, as long as it is a semiconductor substrate, it can be used as the substrate 2600 without particular limitation. For example, a single crystal Si substrate having a n or p conductivity type, a compound semiconductor substrate (a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, a sapphire substrate, a ZnSe substrate, etc.), a paste method or SIMOX (oxygen ion implantation isolation) may be used. An SOI (Insulator Upload) substrate manufactured by the method.

In addition, the insulating film 2604 may be provided by nitriding the insulating film 2602 by high-density plasma treatment after the insulating film 2602 is formed. Further, the insulating film provided on the substrate 2600 may be formed in a single layer or a laminated structure of three or more layers.

Next, a pattern of the resist mask 2606 is selectively formed on the insulating film 2604, and the resist mask 2606 is selectively etched as a mask to selectively form the recess 2608 in the substrate 2600 ( Refer to Figure 17B). As the etching of the substrate 2600 and the insulating films 2602 and 2604, dry etching using plasma can be performed.

Next, after the pattern of the resist mask 2606 is removed, the insulating film 2610 is formed by covering the recess 2608 formed in the substrate 2600 (refer to FIG. 17C).

The insulating film 2610 is transmitted by using a CVD method, a sputtering method, or the like and using yttrium oxide, lanthanum nitride, yttrium oxynitride (SiO x N y ) (x>y>0), yttrium oxynitride (SiN x O y ) (x) >y>0) is formed of an insulating material. Here, a ruthenium oxide film is formed as an insulating film 2610 by an atmospheric pressure CVD method or a low pressure CVD method using TEOS (former tetraethyl phthalate) gas.

Next, a grinding process, a buffing process, or a CMP (Chemical Mechanical Polishing) process is performed to expose the surface of the substrate 2600. Here, by exposing the surface of the substrate 2600, the regions 2612 and 2613 are formed between the insulating films 2611 in the recess 2608 of the substrate 2600. In addition, the insulating film 2611 is obtained by removing the insulating film 2610 formed on the surface of the substrate 2600 by a grinding process, a buffing process, or a CMP process. Next, a p-well is formed in the region 2613 of the substrate 2600 by selectively introducing an impurity element having a p-conductivity type (refer to FIG. 18A).

As the impurity element exhibiting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced to the region 2613 as an impurity element.

In addition, in the present embodiment, since the semiconductor substrate having the n-conductivity type is used as the substrate 2600, the impurity element is not introduced into the region 2612, however, an impurity element exhibiting an n-type may be introduced to form the n-well in the region 2612. As the impurity element exhibiting an n-type, phosphorus (P) or arsenic (As) or the like can be used.

On the other hand, when a semiconductor substrate having a p-conductivity type is used, it is also possible to have a structure in which an impurity element exhibiting an n-type is introduced to the region 2612 to form an n-well, and an impurity element exhibiting an n-type is not introduced into the region 2613.

Next, insulating films 2632 and 2634 are formed on the surfaces of the regions 2612 and 2613 of the substrate 2600 (see FIG. 18B).

The insulating films 2632 and 2634 can oxidize the surface of the regions 2612 and 2613 provided in the substrate 2600 by heat treatment, for example, and form the insulating films 2632 and 2634 from the yttrium oxide film. Alternatively, the surface of the yttrium oxide film may be nitrided by forming a ruthenium oxide film by a thermal oxidation method, and a ruthenium oxide film and a film having oxygen and nitrogen (a yttrium oxynitride film) may be formed in a stacked structure. ).

Further, as described above, the insulating films 2632 and 2634 may be formed using plasma treatment. For example, by oxidizing or nitriding the surface of the regions 2612 and 2613 provided in the substrate 2600 by high-density plasma treatment, a yttrium oxide (SiO x ) film or a tantalum nitride (SiN x ) film may be formed as an insulating film. 2632, 2634. Alternatively, the surface of the regions 2612 and 2613 may be oxidized by high-density plasma treatment, and then subjected to high-density plasma treatment for nitriding treatment. In this case, a hafnium oxide film is formed in contact with the surfaces of the regions 2612, 2613, and a hafnium oxynitride film is formed on the hafnium oxide film, whereby the insulating films 2632, 2634 are laminated with a hafnium oxide film and hafnium oxynitride. Membrane of the membrane. Alternatively, the ruthenium oxide film may be formed on the surface of the regions 2612 and 2613 by thermal oxidation, and then subjected to oxidation treatment or nitridation treatment by high-density plasma treatment.

In addition, the insulating films 2632, 2634 formed in the regions 2612, 2613 of the substrate 2600 function as a gate insulating film in the transistor which is completed later.

Next, a conductive film (refer to FIG. 18C) is formed covering the insulating films 2632, 2634 formed over the regions 2612, 2613, and the regions 2612, 2613 are disposed in the substrate 2600. Here, an example in which the conductive film 2636 and the conductive film 2638 are laminated in this order as a conductive film is shown. Of course, the conductive film may be formed in a single layer or a laminated structure of three or more layers.

As the conductive films 2636 and 2638, one selected from the group consisting of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and niobium (Nb) can be used. An element such as an alloy material or a compound material containing these elements as a main component. Further, a metal nitride film obtained by nitriding these elements may be used. Further, it is also possible to form a semiconductor material typified by polycrystalline germanium doped with an impurity element such as phosphorus.

Here, the conductive film 2636 is formed using tantalum nitride, and the conductive film 2638 is formed in a stacked structure using tungsten thereon. In addition, as the conductive film 2636, a single layer or a laminated film selected from the group consisting of tantalum nitride, tungsten nitride, molybdenum nitride or titanium nitride, and as the conductive film 2638, may be selected from tungsten, tantalum, molybdenum or A single layer or laminated film of titanium.

Next, by selectively etching and removing the conductive films 2636, 2638 provided by lamination, a portion of the upper portion of the substrate 2600 is left over the regions 2612, 2613 to leave conductive films 2636, 2638 to form a conductive film for use as a gate electrode, respectively. 2640, 2642 (refer to FIG. 19A). Further, here, the surfaces of the regions 2612 and 2613 of the substrate 2600 which are not overlapped with the conductive films 2640 and 2642 are exposed.

Specifically, in the region 2612 of the substrate 2600, a portion of the insulating film 2632 formed under the conductive film 2640 that does not overlap the conductive film 2640 is selectively removed, and the ends of the conductive film 2640 and the insulating film 2632 are made. It is roughly the same. Further, in the region 2613 of the substrate 2600, a portion of the insulating film 2634 formed under the conductive film 2642 that does not overlap the conductive film 2642 is selectively removed, and the ends of the conductive film 2642 and the insulating film 2634 are substantially aligned. .

In this case, it is also possible to remove the insulating film or the like of the portion which does not overlap while forming the conductive films 2640, 2642, or to leave the resist mask or the conductive film 2640 after the formation of the conductive films 2640, 2642. And 2642 as a mask removes an insulating film or the like of a portion that does not overlap.

Next, impurity elements are selectively introduced into the regions 2612, 2613 of the substrate 2600 (refer to FIG. 19B). Here, the conductive film 2642 is used as a mask to selectively introduce a low-concentration impurity element imparting an n-type in the region 2613, and the conductive film 2640 is used as a mask to selectively introduce a low-concentration impurity element imparting a p-type in the region 2612. . As the impurity element imparting n-type, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

Next, sidewalls 2654 that are in contact with the side surfaces of the conductive films 2640, 2642 are formed. Specifically, a film containing an inorganic material such as an oxide of cerium, lanthanum or cerium, or a film containing an organic material such as an organic resin is formed by a plasma CVD method, a sputtering method, or the like in a single layer or a laminate. Insulating film. Thereafter, the insulating film is selectively etched through anisotropic etching mainly in the vertical direction to form an insulating film in contact with the side faces of the conductive films 2640 and 2642. The sidewall 2654 is used as a mask for doping when an LDD (lightly doped germanium) region is formed. Further, here, the side wall 2654 is also formed in contact with the side surface of the insulating film or the gate electrode formed under the conductive films 2640, 2642.

Next, the sidewalls 2654, the conductive films 2640, 2642 are used as masks to introduce impurity elements into the regions 2612, 2613 of the substrate 2600 to form an impurity region serving as a source region or a germanium region (refer to FIG. 19C). Here, the sidewall 2654 and the conductive film 2642 are used as a mask to introduce a high concentration of an impurity element imparting n-type in the region 2613 of the substrate 2600, and a high concentration is imparted in the region 2612 by using the sidewall 2654 and the conductive film 2640 as a mask. P type impurity element.

As a result, an impurity region 2658, a low concentration impurity region 2660, and a channel formation region 2656 are formed in the region 2612 of the substrate 2600, the impurity region 2658 forming a source region or a germanium region, and the low concentration impurity region 2660 forms an LDD region. In addition, an impurity region 2664, a low concentration impurity region 2666, and a channel formation region 2662 are formed in the region 2613 of the substrate 2600, the impurity region 2664 forms a source region or a germanium region, and the low concentration impurity region 2666 forms an LDD region.

Further, in the present embodiment, the impurity element is introduced in a state where the regions 2612, 2613 of the substrate 2600 which are not overlapped with the conductive films 2640, 2642 are exposed. Therefore, the channel formation regions 2656, 2662 are formed in a self-aligned manner with the conductive films 2640, 2642 in the regions 2612, 2613 of the substrate 2600, respectively.

Next, a second insulating film 2677 is formed covering an insulating film or a conductive film or the like provided on the regions 2612, 2613 of the substrate 2600, and an opening portion 2678 is formed in the insulating film 2677 (refer to FIG. 20A).

The second insulating film 2677 may be through the use of a CVD method or a sputtering method using a material and a single layer or a layered structure is formed: an insulating film containing oxygen or nitrogen such as silicon oxide (SiO x), silicon nitride (SiN x) , yttrium oxynitride (SiO x N y ) (x>y>0) and yttrium oxynitride (SiN x O y ) (x>y>0), etc.; carbon-containing film such as DLC (diamond-like carbon); Organic materials such as epoxy, polyimine, polyamine, polyvinylphenol, benzocyclobutene, and propylene; or a siloxane such as a decane resin. Note that the siloxane material corresponds to a material containing a Si-O-Si bond. The skeleton structure of the siloxane is composed of a bond of cerium (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. As the substituent, a fluorine group can also be used. Alternatively, as the substituent, an organic group containing at least hydrogen and a fluorine group can also be used.

Next, a conductive film 2680 is formed in the opening portion 2678 by a CVD method, and conductive films 2682a to 2682d are selectively formed on the insulating film 2677 in electrical connection with the conductive film 2680 (refer to FIG. 20B).

The conductive films 2680, 2682a to 2682d are formed by a CVD method or a sputtering method or the like and are formed in a single layer or a laminate using a material selected from the group consisting of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), Molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), niobium (Nd), carbon (C) and niobium (Si) Element; alloy material or compound material with these elements as the main component. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel or one or both of carbon and niobium. The conductive films 2680, 2682a to 2682d preferably have a structure such as a barrier film, an aluminum-iridium (Al-Si) film, and a stacked structure of a barrier film; a barrier film, an aluminum-iridium (Al-Si) film, and nitridation. A laminated structure of a titanium (TiN) film and a barrier film. Note that the barrier film corresponds to a film composed of a nitride of titanium, titanium, or a nitride of molybdenum or molybdenum. Since aluminum and aluminum tantalum have low resistance values and are inexpensive, they are most suitable as a material for forming the conductive film 2680. In addition, by providing a barrier layer of the upper layer and the lower layer, it is possible to prevent the occurrence of hillocks of aluminum or aluminum bismuth. Further, by forming a barrier film made of titanium having a highly reducing element, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film can be reduced to be in good contact with the crystalline semiconductor film. Here, the conductive film 2680 can be formed by selectively growing tungsten (W) by a CVD method.

Through the above processing, a semiconductor device having a p-type transistor formed in the region 2612 of the substrate 2600 and an n-type transistor formed in the region 2613 can be obtained.

Further, the structure of the transistor constituting the semiconductor device of the present invention is not limited to the structure shown in the drawing. For example, a transistor having an inverted staggered structure, a fin FET structure, or the like can be employed. The fin FET structure is preferable because it can suppress the short channel effect which is generated together with the refinement of the crystal size.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes. In other words, in a memory mounted as a semiconductor device in a wireless wafer, individual bit lines of the structural components of the present invention can be selectively precharged. In other words, by not precharging the bit line irrelevant to the reading of data from the memory, it is possible to provide a semiconductor device in which a memory having low power consumption is mounted.

Example 6

A method of using the semiconductor device 3000, which is used as the wireless wafer described in the above embodiment, will be described using Figs. 21A to 21F.

The wireless chip can be widely applied, for example, to banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 21A), packaging containers (wrapping paper, bottles, etc., see FIG. 21C), recording Media (DVD software, video tape, etc., see Fig. 21B), vehicles (bicycles, etc., see Fig. 21D), personal items (packages, glasses, etc.), food, plants, animals, human bodies, clothes, daily necessities, electronic devices, etc. The goods or parcels are transported on the object (see Figures 21E and 21F). The electronic device refers to a liquid crystal display, an EL display, a television device (also simply referred to as a television, a television or a television receiver), a portable telephone, or the like.

The semiconductor device 3000 of the present invention is mounted on a printed substrate or attached to the surface of the article or embedded in the article for attachment to the article. For example, if it is a book, it is embedded in paper, or if it is a package made of an organic resin, it is embedded in the organic resin to be fixed to each article. Since the semiconductor device 3000 of the present invention is small, thin, and light, it can be fixed to an article without detracting from the design of the article itself. Further, by providing the semiconductor device 3000 of the present invention in banknotes, coins, securities, bearer bonds, certificates, and the like, it is possible to have an authentication function. If this authentication function is utilized, counterfeiting can be prevented. In addition, by mounting the semiconductor device 3000 of the present invention in a packaging container, a recording medium, a personal belonging, a food, a clothes, a daily necessities, an electronic device, or the like, a system such as an inspection system can be more efficiently executed.

Further, the present embodiment can be implemented in appropriate combination with the above-described embodiment modes. In other words, in a memory mounted as a semiconductor device in a wireless wafer, individual bit lines of the structural components of the present invention can be selectively precharged. In other words, by not precharging the bit line irrelevant to the reading of data from the memory, it is possible to provide a semiconductor device in which a memory having low power consumption is mounted.

501. . . Address signal line

502. . . Address input buffer

503. . . Column decoder

504. . . Ground wire

505. . . Memory matrix

506. . . Read enable signal line

507. . . Precharge circuit

508. . . Row decoder

509. . . Data output buffer

510. . . Data signal line

511. . . region

601. . . Nth word line

602. . . N+1th word line

603. . . Mth bit line

604. . . M+1th bit line

605, 606, 607, 608. . . Memory unit

609. . . Mth precharge circuit

610. . . M+1 precharge circuit

611. . . Read enable signal line

612. . . Mth latch circuit

613. . . M+1th latch circuit

614. . . M-class ratio switch

615. . . M+1 analog switch

616. . . Mth selection signal line

617. . . Mth inverted selection signal line

618. . . M+1 select signal line

619. . . The m+1th inversion selection signal line

620. . . Output data signal line

622, 621. . . power cable

101. . . Address signal line

102. . . Address input buffer

103. . . Column decoder

104. . . Ground wire

105. . . Memory matrix

106. . . Read enable signal line

107. . . Switch circuit

108. . . Precharge circuit

109. . . Data output buffer

110. . . Data signal line

111. . . region

201. . . Nth word line

202. . . N+1th word line

203. . . Mth bit line

204. . . M+1th bit line

205, 206, 207, 208. . . Memory unit

209. . . Mth latch circuit

210. . . M+1th latch circuit

211. . . M-class ratio switch

212. . . M+1 analog switch

213. . . Mth selection signal line

214. . . Mth inverted selection signal line

215. . . M+1 select signal line

216. . . The m+1th inversion selection signal line

217. . . Mth precharge circuit

218. . . M+1 precharge circuit

219. . . Read enable signal line

220. . . Output data signal line

221, 222. . . power cable

401. . . Precharge circuit

402. . . power cable

2111. . . framework

2112. . . Display department

2113. . . Lens

2114. . . Operation key

2115. . . Shutter release button

2116. . . Memory

2121. . . framework

2122. . . Display department

2123. . . Operation key

2125. . . Memory

2130. . . main body

2131. . . Display department

2132. . . Memory department

2133. . . Operation department

2134. . . headset

2141. . . main body

2142. . . Display department

2143. . . Operation key

2144. . . Memory department

1001. . . Wireless chip

1006. . . Operation circuit

1002. . . CPU

1003. . . ROM

1004. . . RAM

1005. . . Controller

1007. . . antenna

1008. . . Resonant circuit

1009. . . Power circuit

1010. . . Reset circuit

1011. . . Clock generation circuit

1012. . . Demodulation circuit

1013. . . Modulation circuit

1014. . . Power management circuit

1016. . . CPU interface

1017. . . Control register

1018. . . Code extraction circuit

1019. . . Coding circuit

1020. . . Receiving signal

1021. . . Send signal

1022. . . Receiving data

1023. . . Sending information

1015. . . Analogy

1107. . . FPC pad

1108. . . Antenna protrusion

1301. . . Substrate

1302. . . Insulating film

1303. . . Peeling layer

1304. . . Insulating film

1305. . . Semiconductor film

1306. . . Gate insulating film

1307. . . Gate electrode

1307a. . . First conductive film

1307b. . . Second conductive film

1310. . . Insulating film

1311. . . N-type impurity region

1300a, 1300b, 1300d, 1300f. . . N-channel transistor

1300c, 1300e. . . P channel transistor

1308, 1309. . . Impurity zone

1312a. . . First insulating film

1312b. . . Second insulating film

1313. . . Conductive film

1314. . . Insulating film

1315a, 1315b, 1316, 1317. . . Conductive film

1318. . . Insulating film

1319. . . Component forming layer

1320. . . First film

1321. . . Second film

2304, 2306. . . Component area

2300. . . Semiconductor substrate

2302. . . Insulating film

2307. . . P-well

2332, 2334. . . Insulating film

2336, 2338. . . Conductive film

2340, 2342. . . Gate electrode

2348. . . Resist mask

2350. . . Channel formation zone

2352. . . Impurity zone

2366. . . Resist mask

2370. . . Impurity zone

2368. . . Channel formation zone

2372. . . Second insulating film

2374. . . wiring

2360. . . region

2600. . . Substrate

2602, 2604. . . Insulating film

2606. . . Resist mask

2608. . . Concave

2610, 2611. . . Insulating film

2612, 2613. . . region

2615. . . P-well

2632, 2634. . . Insulating film

2636, 2638, 2640, 2642. . . Conductive film

2643, 2654. . . Side wall

2658. . . Impurity zone

2660. . . Low concentration impurity region

2656, 2662. . . Channel formation zone

2664. . . Impurity zone

2666. . . Low concentration impurity region

2677. . . Second insulating film

2678. . . Opening

2680, 2682a-2682d. . . Conductive film

3000. . . Semiconductor device

1 is a block diagram of a mask ROM of the present invention; FIG. 2 is a precharge circuit diagram of Embodiment Mode 1; FIG. 3 is a timing diagram of the circuit diagram of FIG. 2; and FIG. 4 is a precharge circuit diagram in Embodiment Mode 2; 5 is a block diagram of a conventional mask ROM; FIG. 6 is a conventional precharge circuit diagram; FIG. 7 is a timing chart of the circuit diagram of FIG. 6; and FIGS. 8A to 8E show a structure using Embodiment 1 of the present invention; The structure of Embodiment 2 of the present invention is shown; FIG. 10 shows the structure of Embodiment 2 using the present invention; FIGS. 11A to 11D show the structure of Embodiment 3 using the present invention; FIGS. 12A to 12C show the use of the present embodiment. Structure of Embodiment 3 of the Invention; Figs. 13A and 13B show the structure of Embodiment 3 using the present invention; Figs. 14A to 14C show the structure of Embodiment 4 using the present invention; Figs. 15A to 15C show the use of the present invention. The structure of Embodiment 4; FIG. 16 shows the structure of Embodiment 4 using the present invention; FIGS. 17A to 17C show the structure of Embodiment 5 using the present invention; and FIGS. 18A to 18C show the use of Embodiment 5 of the present invention. 19A to 19C show the structure of Embodiment 5 using the present invention; FIGS. 20A and 20B show the use of the present invention Example of the configuration of the embodiment 5; FIG. 21A to 21F shows a configuration of Example 6 of the present invention.

201. . . Nth word line

202. . . N+1th word line

203. . . Mth bit line

204. . . M+1th bit line

205, 206, 207, 208. . . Memory unit

209. . . Mth latch circuit

210. . . M+1th latch circuit

211. . . M-class ratio switch

212. . . M+1 analog switch

213. . . Mth selection signal line

214. . . Mth inverted selection signal line

215. . . M+1 select signal line

216. . . The m+1th inversion selection signal line

217. . . Mth precharge circuit

218. . . M+1 precharge circuit

219. . . Read enable signal line

220. . . Output data signal line

221, 222. . . power cable

Claims (20)

  1. A semiconductor device comprising: a word line; a first bit line and a second bit line; a first memory unit electrically connected to the word line and the first bit line; electrically connected to the word line and the a second memory cell of the second bit line; a first switching element including a first terminal electrically connected to the first bit line; and a second switching element including a first terminal electrically connected to the second bit a first precharge circuit for outputting a precharge potential to the first bit line, wherein the first precharge circuit is electrically connected to the first bit line via the first switching element; and the second precharge circuit For outputting a precharge potential to the second bit line, wherein the second precharge circuit is electrically connected to the second bit line via the second switching element; and a switching circuit for selectively operating the second A switching element and the second switching element.
  2. The semiconductor device of claim 1, wherein the first pre-charging circuit comprises a first transistor, and the second pre-charging circuit comprises a second transistor, One of a source and a drain of the first transistor is electrically connected to a second terminal of the first switching element, and one of a source and a drain of the second transistor is electrically connected to the second switching element The second terminal.
  3. The semiconductor device of claim 2, wherein the first transistor and the second transistor are disposed on the same substrate, and wherein the substrate is any one of a glass substrate, a quartz substrate, and a plastic substrate.
  4. The semiconductor device of claim 2, wherein the first transistor and the second transistor are formed on the SOI substrate.
  5. The semiconductor device of claim 1, wherein the first memory unit comprises a first transistor, the second memory unit comprises a second transistor, and a gate of the first transistor is electrically connected to the word line And one of a source and a drain of the first transistor is electrically connected to the first bit line, and a gate of the second transistor is electrically connected to the word line, and a source of the second transistor One of the pole and the drain is electrically connected to the second bit line.
  6. The semiconductor device of claim 1, wherein the first bit line is electrically connected to the first latch circuit, and the first latch circuit is configured to be stored for reading in the first memory unit. a potential of the data; and the second bit line is electrically connected to the second latch circuit for storing data for reading the data stored in the second memory unit Potential.
  7. An electronic device comprising the semiconductor device of claim 1 of the patent application.
  8. The semiconductor device of claim 1, wherein the first switching element and the second switching element are selectively operated, the switching circuit is configured to apply a signal to the first switching element without applying the signal to the second Switching element.
  9. The semiconductor device of claim 1, wherein the first switching element and the second switching element are selectively operated, the switching circuit is configured to simultaneously apply a first signal to a third terminal and a first terminal of the first switching element The second signal is to the third terminal of the second switching element.
  10. The semiconductor device of claim 1, wherein the first precharge circuit is operative to be electrically connected to a read signal line of the first terminal of the first precharge circuit, wherein the read signal line is not powered Connected to one of the first or second switching elements.
  11. A semiconductor device comprising: a modulation circuit; a demodulation circuit; an antenna; a logic circuit; and a memory circuit including a word line; a first bit line and a second bit line; electrically connected to the word Line and first memory list of the first bit line a second memory cell electrically connected to the word line and the second bit line; a first switching element including a first terminal electrically connected to the first bit line; and a second switching element including One terminal is electrically connected to the second bit line; a first pre-charging circuit is configured to output a pre-charge potential to the first bit line, wherein the first pre-charge circuit is electrically connected to the first via the first switching element a first precharge circuit for outputting a precharge potential to the second bit line, wherein the second precharge circuit is electrically connected to the second bit line via the second switching element; and a switch And a circuit for selectively operating the first switching element and the second switching element.
  12. The semiconductor device of claim 11, wherein the first pre-charging circuit comprises a first transistor, the second pre-charging circuit comprising a second transistor, one of a source and a drain of the first transistor Electrically connected to the second terminal of the first switching element, and one of the source and the drain of the second transistor is electrically coupled to the second terminal of the second switching element.
  13. The semiconductor device of claim 12, wherein the first transistor and the second transistor are both disposed on a substrate And, wherein the substrate is any one of a glass substrate, a quartz substrate, and a plastic substrate.
  14. The semiconductor device of claim 12, wherein the first transistor and the second transistor are formed on the SOI substrate.
  15. The semiconductor device of claim 11, wherein the first memory unit comprises a first transistor, the second memory unit comprises a second transistor, and a gate of the first transistor is electrically connected to the word line And one of a source and a drain of the first transistor is electrically connected to the first bit line, and a gate of the second transistor is electrically connected to the word line, and a source of the second transistor One of the pole and the drain is electrically connected to the second bit line.
  16. The semiconductor device of claim 11, wherein the first bit line is electrically connected to the first latch circuit, and the first latch circuit is configured to be stored for reading in the first memory unit. a potential of the data; and the second bit line is electrically coupled to the second latch circuit for storing a potential for reading data stored in the second memory unit.
  17. An electronic device comprising the semiconductor device of claim 11 of the patent application.
  18. The semiconductor device of claim 11, wherein the first switching element and the second switching element are selectively operated, the switching circuit is configured to apply a signal to the first switching element without applying the signal to the second Switching element.
  19. The semiconductor device of claim 11, wherein the first switching element and the second switching element are selectively operated, the switching circuit is configured to simultaneously apply a first signal to a third terminal and a first terminal of the first switching element The second signal is to the third terminal of the second switching element.
  20. The semiconductor device of claim 11, wherein the first precharge circuit is operative to be electrically connected to a read signal line of the first terminal of the first precharge circuit, wherein the read signal line is not powered Connected to one of the first or second switching elements.
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