JP2865119B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit capable of mapping the entire memory space, in which a plurality of memory ICs (integrated circuits) having different memory capacities are connected, with continuous addresses.

[0002]

2. Description of the Related Art Conventionally, a storage area (memory space) having a required capacity has been constructed using several memory ICs. In this case, the capacities of the memory ICs used are often different. FIG.
Two 1M word memory ICs and 4M word memory ICs
2 shows an example of a memory map of a memory space configured by using two memory spaces. In this example, 1M,
4M, 1M, and 4M. The address line of a 1M word memory IC is 20 bits, and the address line of a 4M word memory IC is 22 bits.

In such an example, for example, an input address line (for example, an address bus line) has 24 bits, and the upper 2 bits are decoded to generate a chip select signal. The chip select signal specifies which of the areas in FIG. 10 to access. The address lines of the four memory ICs are all connected to the lower side of the input address lines. That is, a 1M word memory IC
20 bits of the address line are the lower 2 bits of the input address line.
22 bits of the address line of the 4M word memory IC are connected to the lower 22 bits of the input address line.

[0004]

With the above connection method, the entire memory space does not have continuous addresses. For example, when connecting as shown in FIG.
In the area from bank address 0H to FFFFFH and bank address 800000H to 8FFFFFFH, there is a substance of the memory.
There is a problem that a so-called alias (virtual image) is generated in a region from 000H to 3FFFFFFH and a bank address from 900000H to BFFFFFFH.
Here,... H indicates hexadecimal notation.

On the other hand, in some systems using such storage areas, it is necessary to access data by giving continuous addresses. For example,
Examples include a waveform memory for storing waveform data in an electronic musical instrument and a sequence pattern memory of a digital sequencer.

The present invention has been made in view of the above-described problems in the conventional example, and provides a memory control circuit capable of mapping all memory spaces configured using memory ICs having different memory capacities with continuous addresses. The purpose is to:

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for accessing a storage area formed by mixing a plurality of memories having at least two or more different capacities with continuous address data. a memory control circuit for use in a storage means for storing information indicating whether the memory of what capacity sequentially from address low position of the storage area is set, is input
For the upper multiple bits related to the memory selection of the address data,
To calculate a plurality of predetermined values separately and
Whether the lower multiple bits of the plurality of operation results indicate zero
The detection result, the lower part of the plurality of calculation results
Position based on the plurality of bits other than the bit values, and the information stored in the storage means, and specifying a memory to be accessed by the address data, and the selection signal generating means for outputting a selection signal for selecting the memory It is characterized by having.

As the memory IC, a DRAM (dynamic RAM) is used in addition to an SRAM (static RAM).
Or the like may be used. A memory IC of a type that multiplexes an input address into a row address and a column address may be used.

The storage means may be any as long as it can store information indicating the capacity of the memory IC set in order from the lowest address. For example, it may be set by an appropriate switch, or may be a register holding information input by the user. Further, the information may be set from the beginning, or the system may be able to automatically detect this information. In this case, a means for detecting what capacity of memory IC is set in order from the lowest address is provided.

[0010]

With respect to a storage area configured by mixing a plurality of memory ICs having different capacities, information indicating what capacity of the memory IC is set in order from the lowest address of the storage area is stored in the storage means. It is remembered. Then, based on the upper predetermined bits of the input address data and the information stored in the storage means, a selection signal for specifying a memory IC to be accessed by the input address data is output. Therefore, for example, when the second memory IC is connected next to the first memory IC, the second memory IC starts from the address next to the last address of the first memory IC.
Of the memory IC is output.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block configuration of an electronic musical instrument to which a memory control circuit according to one embodiment of the present invention is applied. The electronic musical instrument of this embodiment includes a keyboard 101, a waveform input unit 102, a microphone 103, a display 104, a panel switch 105, a central processing unit (CPU) 106, a read only memory (ROM) 107, a random access memory (RAM) 108, A sound source 109, a sound system 110, and a bus line 111 are provided.

The keyboard 101 has a plurality of keys corresponding to musical scales, and outputs performance information such as a sounding instruction signal, pitch information, and touch information in response to a player's operation of the keyboard. The waveform input unit 102 is a unit for inputting waveform data stored in a waveform memory provided inside the sound source 109. A microphone 103 can be connected to the waveform input unit 102, and the waveform data of the sound input by the microphone 103 is transmitted to the sound source 10 via the waveform input unit 102.
9 is stored in the waveform memory. Note that an input using a magnetic disk or MIDI can be used instead of the microphone 103.

The display 104 is a display device for displaying various information. The panel switch 105
A switch for performing various operations such as setting of a tone color and reading of waveform data. Central processing unit (CPU) 1
Reference numeral 06 controls the operation of the entire electronic musical instrument. The read-only memory (ROM) 107 stores programs executed by the CPU 106 and various tables.

[0015] Random access memory (RAM) 108
Is used for a work register or the like. The sound source 109 is
A tone signal is generated based on an instruction from the CPU 106.
The details of the sound source 109 will be described later with reference to FIG. The sound system 110 actually emits a tone based on a tone signal from the sound source 109. The bus line 111 is a bidirectional bus line that connects the above-described units.

In this electronic musical instrument, by operating the panel switch 105 while referring to the display 104, a sound is input from the microphone 103, and waveform data obtained by sampling the sound is stored in a waveform memory in the sound source 109. it can. Further, by a predetermined operation, a musical sound can be generated using the waveform data stored in the waveform memory. For example, it is possible to sample a human voice, store it in a waveform memory, reproduce the waveform data by playing the keyboard 101, and generate a musical tone in the tone of the human voice.

FIG. 2 shows a detailed block configuration of the sound source 109. The sound source 109 includes an interface 201, an address generator 202, an address converter 203, a waveform memory 204, a direct write / read unit 205, an envelope generator 206, a multiplier 207, and a digital / analog (D / A) converter 208. ing.

The interface 201 is a bus line 1
11 is an interface for exchanging information through the interface 11. The address generation unit 202 includes a waveform memory 204
Generates an address when accessing. The generated address is subjected to a predetermined conversion by the address conversion unit 203. The converted address is input to waveform memory 204, and the waveform data at that address is read. The read waveform data is supplied to the envelope generator 2 in the multiplier 207.
The envelope data is multiplied by the envelope data output from 06 to give an envelope. The waveform data to which the envelope has been added is converted into an analog tone signal by the D / A converter 208 and sent to the sound system 110. The direct write / read unit 205 is a unit for directly writing / reading to / from the waveform memory 204.

FIG. 3 shows the address conversion unit 2 in the sound source 109.
3 shows the detailed block configuration of the waveform memory 03 and the waveform memory 204. The waveform memory 204 is composed of four banks. Each bank is referred to as a 0th bank DB0, a first bank DB1, a second bank DB2, and a third bank DB3 in order from the lowest address. FIG. 7B shows the arrangement of the four banks. The head position of the 0th bank DB0 is address “0”.

Each bank is composed of 4M words or 1M words of DRAM. FIG. 7C shows a connection example of the DRAM. In this example, the 1M word DR is stored in the 0th bank DB0.
AM, 1M word DRAM in first bank DB1, second bank
A 4M word DRAM is connected to the bank DB2, and a 4M word DRAM is connected to the third bank DB3. The memory capacity of the entire waveform memory 204 varies depending on which capacity DRAM is used for each bank. However, in any combination, the waveform memory 204 must always be accessible at consecutive addresses.

Therefore, the address conversion unit 203 to which the memory control circuit of the present invention is applied performs a predetermined conversion on the input address (consecutive addresses) to access the waveform memory 204, and each bank has 4M or 1M. Regardless of which DRAM is used, the entire memory space of the waveform memory 204 can be accessed with continuous addresses. Since the maximum capacity of the entire memory space of the waveform memory 204 is 4 M words × 4 banks = 16 M words, the input address to the address conversion unit 203 is 24 bits.

Referring to FIG. 3, waveform memory 204 forms a DRAM 305 forming a 0th bank DB0, a DRAM 306 forming a first bank DB1, a DRAM 307 forming a second bank DB2, and a third bank DB3. It comprises a DRAM 308. DRAMs 305 to 30
8 has a capacity of either 4M words or 1M words as described above. A 4M word DRAM uses an 11-bit row address and an 11-bit row address.
The address terminal has 11 bits in order to multiplex and input a bit column address.

These DRAMs have a row address selection signal as a control signal for selecting a row address input, a column address selection signal as a control signal for selecting a column address input, and a refresh control signal. It has an input terminal for each control signal. 1M word DRAMs have similar terminals, but address terminals are 10 bits.

The address converter 203 includes a memory size register 301, an address decoder 302, an address multiplexer 303, and a RAS controller 304.
Consists of

The memory size register 301 stores a 4M or 1M DRA in each bank of the waveform memory 204.
This is a 4-bit register that stores memory size information indicating whether M is used. 0 of the waveform memory 204
Bank DB0, first bank DB1, second bank DB2,
And bits for storing memory size information relating to the third bank DB3 are respectively referred to as memory size bits B0,
These are called memory size bits B1, memory size bits B2, and memory size bits B3. For each memory size bit, "1" indicates that a 4M word DRAM is connected to the bank, and "0" indicates that a 1M word DRAM is connected to the bank.

The address decoder 302 decodes the upper 4 bits of the input address 24 bits and decodes the decoded signal U.
D is output. Details of the address decoder 302 and the decode signal UD will be described later with reference to FIGS.

The RAS controller 304 receives a decode signal UD from the address decoder 302 and memory size information from the memory size register 301,
It outputs row address select signals RAS0, RAS1, RAS2, and RAS3 indicating which bank of DRAM is actually accessed for the input address (24 bits). Row address selection signals RAS0, RAS1, RAS
2 and RAS3 are the 0th bank DB0, the first bank DB1, the second bank DB2, and the third bank DB3, respectively.
Is a negative logic signal indicating that the selected DRAM is selected and a row address is output to the selected bank. 24
When one bit input address is input, one of the row address selection signals RAS0, RAS1, RAS2, and RAS3 is "0" and the other is "1". Note that RA
Details of the S controller 304 will be described later with reference to FIG.

The address multiplexer 303 multiplexes an input address into a row address and a column address. In the electronic musical instrument of this embodiment, the DRAMs 305 to 308 constituting the waveform memory 204 are adapted to receive multiplexed row and column addresses. The address multiplexer (11 bits) of the 4M word DRAM has an address multiplexer 3
The 11-bit address line from 03 is connected.
The lower 10 bits of the 11-bit address line from the address multiplexer 33 are connected to the address terminal (10 bits) of the 1M word DRAM.

FIG. 4A shows a timing generator for generating various timing signals. Timing generator 40
1 outputs a row address selection clock φRAS, a column address selection clock φCAS, and a refresh control signal φref in addition to the basic clock φ0. These timing signals are all signals of positive logic.

FIG. 4B shows the configuration of the address multiplexer 303. Address multiplexer 303
Is a selector 402, inverters 403 and 404, AN
It has D gates 405 and 406. To the terminal A of the selector 402, the lower 11 bits (2 0 to 2 10 bits) of the input address 24 bits are connected. The terminal B is connected to 10 bits from 2 10 bits to 2 19 bits of the 24 bits of the input address. The terminal C is connected to the upper 11 bits of the 24 bits of the input address (2 11 bits to 2 21 bits).

The row address selection clock φRAS is input to the inverter 403. The output of the inverter 403 is connected to the terminal SA of the selector 402. The inverter 404 receives a 4M word flag signal 4MF. The 4M word flag signal 4MF is used to access a 4M word DRAM or a 1M word DRA.
M. That is, it is determined which bank of the DRAM should be accessed for the input address. When the bank is a 4M word DRAM, the 4M word flag signal 4MF is "1", and when the bank is a 1M word DRAM, It is set to “0”. 4M word flag signal 4MF
Are generated and output by the RAS controller 304 in FIG.

The AND gate 405 inputs the row address selection clock φRAS and the output signal of the inverter 404. The output terminal of the AND gate 405 is connected to the selector 4
02 terminal SB. AND gate 406
Inputs a row address selection clock φRAS and a 4M word flag signal 4MF. The output terminal of the AND gate 406 is connected to the terminal SC of the selector 402. The selector 402 selects the terminal A when the terminal SA is “1”.
Select and output the input. Similarly, when the terminal SB is “1”, the input of the terminal B is selectively output, and when the terminal SC is “1”, the input of the terminal C is selectively output.

Row address selection clock φRAS is "1"
And the bank to be accessed is a 1M word DRA
When M (4MF is “0”), the terminal SB becomes “1”, and the selector 402 outputs 2 to the 19th power of 24 bits of the input address input to the terminal B.
Output 10 bits up to the power bit. However, 1-bit “0” is added to the most significant bit, and the data is actually output as 11-bit data. At this time, the input address 2
2 bits are an address for accessing a 1M word DRAM, 2 0 to 2 9 bits are a column address, 2 10 to 2 19 bits are a row address, 2 to the 20 power The bits from the bit to the most significant bit are meaningless. Therefore, the selector 402 selects and outputs the row address for the DRAM of 1M words input to the terminal B.

Row address selection clock φRAS is "1"
And the bank to be accessed is 4M words DRA
When M is 4 (4MF is “1”), the terminal SC becomes “1”, and the selector 402 determines the 11th bit from 2 11 to 2 21 bits of the 22 bits of the input address input to the terminal C. Output a bit. At this time, the input 22 bits of the address are addresses for accessing a 4M word DRAM, and 2 0 to 2 10 bits are column addresses, 2 11 to 2 21 bits. Is a row address. Therefore, the selector 402 selects and outputs the row address for the 4M word DRAM input to the terminal C.

Row address select clock φRAS is "0"
At this time, the terminal SA becomes “1”, and the selector 402 outputs the lower 11 bits of the address 22 bits input to the terminal A. At this time, the DR of the bank to be accessed is
The column address is output regardless of the capacity of AM. Since a column address for accessing a 1M word DRAM is 10 bits, the 11 most significant bits output from the selector 402 are not used.

FIG. 5 is a circuit diagram of the address decoder 302 of FIG. The address decoder 302 includes the adder 51
1,521,531, "00" detectors 501,512,
522, 532, 533, decoders 502, 513, N
OR gate 523, inverter 525, and AND gates 503, 504, 505, 506, 514, 51
5,516,524,526,527,534.

The lower 2 bits of the 4-bit data (upper 4 bits of the input address 24 bits) input to the address decoder 302 are input to a “00” detector 501. "0
0 ”detector 501 detects that the input 2-bit data is“ 0 ”.
When it is "0", it outputs "1", and when it is other than "00", it outputs "0". The operation of the other "00" detectors is the same. The upper 2 bits of the input data 4 bits are input to the decoder 502.

The decoder 502 outputs "1" to the terminal Y0 when the input two bits are "00", "1" to the terminal Y1 when "01", and "1" to the terminal Y2 when "10".
Is output to the terminal Y3 when "11". Outputs from the terminals Y0, Y1, Y2, and Y3 of the decoder 502 are directly decoded signals UA0-
3, UA4-7, UA8-11, and UA12-15.

The AND gate 503 is connected to the "00" detector 5
01 and the output from the terminal Y0 of the decoder 502, and outputs the result of the AND operation to the decoded signal UA0.
Output as AND gate 504 receives the output from “00” detector 501 and the output from terminal Y 1 of decoder 502, and outputs the result of the AND operation to decode signal U.
Output as A4. AND gate 505 is "00"
The output from the detector 501 and the terminal Y of the decoder 502
2 and outputs the result of the AND operation as a decoded signal UA8. The AND gate 506 outputs “0”
The output from the "0" detector 501 and the output from the terminal Y3 of the decoder 502 are input, and the result of the AND operation is output as a decode signal UA12.

The 4-bit data input to the address decoder 302 is input to the adder 511 and added to "-1". The lower two bits of the result are input to a “00” detector 512. The upper two bits of the four bits of output data from the adder 511 are input to the decoder 513. Decoder 51
3 is “1” at the terminal Y0 when the input 2 bits are “00”, “1” at the terminal Y1 when “2” is “01”, and “1” at the terminal Y1.
When "0", "1" is output to the terminal Y2. Outputs from the terminals Y0, Y1, Y2 of the decoder 513 are decoded signals UA1-4, UA5-8,
Output as UA9-12.

The AND gate 514 is connected to the “00” detector 5
12 and the output from the terminal Y0 of the decoder 513, and outputs the result of the AND operation to the decoded signal UA1.
Output as AND gate 515 receives the output from “00” detector 512 and the output from terminal Y 1 of decoder 513, and outputs the result of the AND operation to decode signal U.
Output as A5. The AND gate 516 outputs “00”
The output from the detector 512 and the terminal Y of the decoder 513
2 and outputs the result of the AND operation as a decoded signal UA9.

The 4-bit data input to the address decoder 302 is input to the adder 521 and added to "-2". The lower two bits of the result are input to a “00” detector 522. Inverter 525 inputs the four most significant bits of output data from adder 521. AND gate 526 outputs the output of inverter 525 and adder 52.
The second bit of the output 4 bits of 1 is input, and the result of the AND operation is output as a decode signal UA6-9. NO
R gate 523 receives the most significant bit and the second most significant bit of the four bits of output data from adder 521, and outputs NO.
The result of the R operation is output as decode signal UA2-5.

The AND gate 524 is connected to the “00” detector 5
22 and the output from NOR gate 523, and outputs the result of AND operation as decode signal UA2. The AND gate 527 is connected to the “00” detector 52
2 and the output from the AND gate 526, and outputs the result of the AND operation as a decoded signal UA6.

The 4-bit data input to the address decoder 302 is input to an adder 531 and added to "-3". The lower two bits of the result are input to a “00” detector 532, and the upper two bits are input to a “00” detector 533. The output from the “00” detector 533 is output as it is as a decode signal UA3-6. AND gate 53
4 is a “00” detector 532 and a “00” detector 53
3 and outputs the result of the AND operation as a decoded signal UA3.

FIG. 6 shows the RAS controller 304 of FIG.
FIG. RAS controller 304 AND
Gates 601 to 620, OR gates 621 to 624, inverters 630 to 633, EXOR (exclusive OR) gate 634, AND gates 635 to 638, O
R gates 639 and 640, AND gates 650 to 65
3, OR gate 654, 655, OR gate 660-6
63, and NAND gates 670-673.

Memory size bit B0 from memory size register 301 input to RAS controller 304
To B3 are input to inverters 630 to 633, respectively. The EXOR gate 634 has the memory size bit B0
And B1 are input and an EXOR operation is performed. Therefore,
The EXOR gate 634 is configured such that the 0th bank DB0 of the waveform memory 204 is a DRAM of 1M words and the 1st bank DB0
When 1 is a 4M word DRAM, or conversely, when the 0th bank DB0 is 4M and the first bank DB1 is 1M, it outputs "1".

The AND gate 635 inputs the memory size bits B0 and B1 and the output of the inverter 632, and inputs the result of the AND operation to the OR gate 639.
The output of the AND gate 635 becomes "1" because the 0th bank DB0 is 4M, the first bank DB1 is 4M, and the second bank DB1 is 4M.
This is when the bank DB2 is 1M. AND gate 636
Is the memory size bit B2 and the EXOR gate 63
4 and inputs the result of the AND operation to an OR gate 63
Enter 9 The output of the AND gate 636 becomes “1” because the 0th bank DB0 and the 1st bank DB1 are 4M
And 1M (which may be 4M) and the second
This is when the bank DB2 is 4M. OR gate 639
Performs an OR operation on the outputs of the AND gates 635 and 636.

The AND gate 601 outputs the decode signal UA
0-3 and the memory size bit B0 are input, and the result of the AND operation is output to the OR gate 621. AND gate 602 is connected to decode signal UA0 and inverter 63
0 is input and the result of the AND operation is input to an OR gate 62.
Output to 1. The OR gate 621 performs an OR operation on these input signals and outputs the operation result as the 0th bank selection signal S0.

The AND gate 603 outputs the decode signal UA
4-7 and memory size bits B0 and B1 are input, and the result of the AND operation is output to OR gate 622.
AND gate 604 receives decode signal UA4, memory size bit B0 and the output of inverter 631, and outputs the result of the AND operation to OR gate 622.
AND gate 605 receives decode signal UA1-4, output of inverter 630 and memory size bit B1, and outputs the result of the AND operation to OR gate 622. AND gate 606 receives decode signal UA1, the output of inverter 630 and the output of inverter 631, and outputs the result of the AND operation to OR gate 622. The OR gate 622 performs an OR operation on these input signals and outputs the operation result as a first bank selection signal S1.

The AND gate 607 outputs the decode signal UA
8-11 and the memory size bits B0, B1, B2 are input, and the result of the AND operation is output to the OR gate 623. AND gate 608 receives decode signal UA8, memory size bits B0 and B1 and the output of inverter 632, and outputs the result of the AND operation to OR gate 623. The AND gate 609 outputs the decode signal UA5-
8, inputs the output of the EXOR gate 634 and the memory size bit B2, and outputs the result of the AND operation to the OR gate 62
Output to 3.

The AND gate 610 outputs the decode signal UA
5. The outputs of the EXOR gate 634 and the inverter 632 are input, and the result of the AND operation is output to the OR gate 623. The AND gate 611 outputs the decode signal UA2-
5. The output of the inverter 630, the output of the inverter 631, and the memory size bit B2 are input, and the result of the AND operation is output to the OR gate 623. The AND gate 612 outputs the decode signal UA2, the output of the inverter 630, the output of the inverter 631, and the inverter 632.
And outputs the result of the AND operation to an OR gate 623
Output to The OR gate 623 performs an OR operation on these input signals, and outputs the operation result as a second bank selection signal S2.

The AND gate 613 outputs the decode signal UA
12-15 and memory size bits B0, B1, B
2 and B3, and outputs the result of the AND operation to an OR gate 62
4 is output. AND gate 614 outputs decode signal U
A12, the memory size bits B0, B1, B2 and the output of the inverter 633 are input, and the result of the AND operation is
Output to the R gate 624. AND gate 615 receives decode signal UA9-12, the output of OR gate 639 and memory size bit B3, and outputs the result of the AND operation to OR gate 624. AND gate 616
Inputs the decode signal UA9, the output of the OR gate 639, and the inverter 633, and outputs the result of the AND operation by OR.
Output to the gate 624.

The AND gate 617 outputs the decode signal UA
6-9, OR gate 640 and memory size bit B
3 and inputs the result of the AND operation to an OR gate 62
4 is output. AND gate 618 outputs decode signal U
A6, the outputs of the OR gate 640 and the inverter 633 are input, and the result of the AND operation is output to the OR gate 624. The AND gate 619 outputs the decode signal UA3-
6. The output of the inverter 630, the output of the inverter 631, the output of the inverter 632, and the memory size bit B3 are input, and the result of the AND operation is output to the OR gate 624. AND gate 620 outputs decode signal UA
3. The output of the inverter 630, the output of the inverter 631, the output of the inverter 632, and the output of the inverter 633 are input, and the result of the AND operation is output to the OR gate 624. The OR gate 624 outputs these input signals to O
R operation is performed, and the operation result is output as a third bank selection signal S3.

As will be described in detail later, the 0th bank selection signal S0, the first bank selection signal S1, the second bank selection signal S2, and the third bank selection signal S3 are stored in the memory space currently being accessed. The positions are the 0th bank, the 1st bank, the 2nd bank, and the 3rd bank, respectively.

AND gate 650 receives memory size bit B0 and 0th bank selection signal S0, and outputs the result of the AND operation to OR gate 654. AND gate 651 receives memory size bit B1 and first bank selection signal S1, and outputs the result of the AND operation to OR gate 654. AND gate 652 receives memory size bit B2 and second bank selection signal S2,
The result of the AND operation is output to OR gate 654. AN
The D gate 653 stores the memory size bit B3 and the third
The bank selection signal S3 is input, and the result of the AND operation is ORed.
Output to the gate 654. As a result, the OR gate 65
No. 4 outputs “1” when the n-th bank is 4M when accessing the n-th bank (n = 0 to 3), and outputs “0” when the n-th bank is not 4M (that is, 1M).

The OR gate 655 receives the output of the OR gate 654 and the refresh control signal φref, and outputs the result of the OR operation as a 4M word flag signal 4MF. Therefore, the 4M word flag signal 4MF becomes the nth
When accessing a bank (n = 0 to 3), if the n-th bank is 4M, it is “1”.
M) "0" is output, and "1" is also output at the timing of refresh.

OR gate 660 receives the 0th bank selection signal S0 and refresh control signal φref, and outputs the result of the OR operation to NAND gate 670. Also,
Row address selection clock φRAS is input to NAND gate 670. NAND gate 670
The result of the operation is stored in the 0th bank row address selection signal RAS0.
Output as Therefore, the 0th bank row address selection signal RAS0 (negative logic) is used when accessing the 0th bank or at the timing of refreshing.
Only when the row address selection clock φRAS (positive logic) is “1”, “0” is output. At this time, the 0th bank is selected.

The OR gates 661, 662, 663 are
It plays the same role as the R gate 660. Also, NAND
Gates 671, 672, 673 are also NAND gates 670
Plays the same role as. As a result, the n-th bank row address selection signal RASn (n = 1 to 3) is used only when accessing the n-th bank or at the timing of refreshing and when the row address selection clock φRAS is “1”. "0" will be output. At this time, the n-th bank is selected.

Next, the access operation of the waveform memory 204 in the present embodiment will be described in detail with reference to the detailed diagrams of the address conversion unit and the waveform memory of FIG. 3 and FIGS.

In this embodiment, the column address is directly input to all the banks. Therefore, when the column address selection clock φCAS is “1”, the DRAMs 305 to 305 of all of the 0th to third banks
At 308, a column address selection signal based on the column address clock φCAS is input, and the column address (the lower 11 bits of the input address) from the address multiplexer 303 is input. At the timing of row address selection, the row address selection signal RAS of negative logic is used.
By setting any one of n (n = 0 to 3) to “0”, one bank to be accessed is specified.

Next, the operation at the time of selecting a row address, particularly the operation of the address decoder 302 and the RAS controller 304 will be described.

Referring to FIG. 5, first, address decoder 3
02 inputs the upper 4 bits of the 24 bits of the input address. When these upper 4 bits are represented in decimal, "0" ~
It is an integer of “15”. Address decoder 302 outputs a decode signal UA corresponding to the input 4-bit data.

For example, when the input 4-bit data is "0" in decimal notation in FIG. 5, the decoder 502 outputs "1" to the terminal Y0, and the "00" detector 501 outputs "1". . Therefore, the decode signals UA0 and UA0-3 become "1", and the others become "0". When the input 4-bit data is “1” in decimal notation, the adder 511 outputs “0”, the decoder 513 outputs “1” to the terminal Y0, and the “00” detector 512 outputs “1”. 1 "is output. Therefore, the decode signals UA1 and UA1-4 become "1", and UA0-3 further becomes
It becomes "1" and the others become "0".

FIG. 8 shows 4-bit data input to address decoder 302 and decode signal UA output corresponding to the input. The column of “upper 4 bits” in FIG.
Indicates a value expressed in zeros. The column of “decode signal” indicates a decode signal output corresponding to the input data. For example, when the input 4 bits are “0”, the decode signal U
A0, UA0-3, the decoded signals UA0-3, UA1, UA1-4 when the input 4 bits are "1", and the decode signals UA0- when the input 4 bits are "2".
3, UA1-4, UA2, UA2-5 are decoded signal when the 4-bit input is "3" UA0-3, UA1
-4, UA2-5, UA3, UA3-6,... Output a decode signal corresponding to the input.

Here, the 4-bit data input to the address decoder 302 is the upper 4 bits of the input address 24 bits.
Since it is a bit, its value indicates which area of the waveform memory space divided into 1M words is to be accessed. In this embodiment, the maximum capacity is 16 M words using four 4 M word DRAMs. FIG. 7D is a diagram in which the 16 M words are divided in units of 1 M words. Address 0H to FFFFFH
To the 0th area, address 100000H to 1FFF
The area up to FFH is referred to as a first area,..., And the area from address F00000H to FFFFFFH is referred to as a fifteenth area. If the value of the 4-bit data input to the address decoder 302 is n (n = 0 to 15) in decimal notation, it means that the n-th area is to be accessed.

On the other hand, there are 16 combinations in which 1M or 4M DRAMs are provided in the four banks 0 to 3. FIG. 7A shows a list of these combinations. Each bit B0 to B3 of the memory size register indicates whether 1M or 4M is provided in each bank as described above. The column of “DRAM space” indicates which area in FIG. 7D each bank DB0 to DB3 corresponds to.

For example, the number (0) in FIG. 7A is a case where all four banks are 1M DRAM, and the column of “DRAM space” of this number (0) indicates that the 0th bank DB0 is (D), the first bank DB1 is in the first area, the second bank DB2 is in the second area, and the third bank DB3 is in the zero area.
Indicates that each hits the third region. For example, the connection example in FIG. 7C corresponds to the number (12) in FIG. 7A. Looking at the “DRAM space” column of the number (12), DB0 is “0” and DB1 is “0”. 1 "and DB2 is" 2
-5 "and DB3 are" 6-9 ", which means that the 0th bank DB0 is in the 0th area in FIG. 7D, the first bank DB1 is in the first area, and the second bank DB2 is The third bank DB3 extends from the sixth area to the ninth area from the second area to the fifth area.
It is shown that each hits by the area. Similarly, for other numbers, the column of “DRAM space” indicates to which area in FIG. 7D the banks DB0 to DB3 correspond.

FIG. 8 "Bank which may be accessed"
The column of FIG. 7 shows the correspondence between the bank having a possibility of access when each decode signal is output and the bank of which number in FIG. 7A.

For example, when the decode signal UA0 is output, the 0th area of FIG. 7D is accessed, but the 0th area is searched from the "DRAM space" column of FIG. 7A. Looking at the numbers (0) (2) (4) (6) (8)
The banks DB0 of (10), (12) and (14) correspond to this. This is because when the decode signal UA0 is output,
Number (0) (2) (4) (6) (8) (10) (12)
There is a possibility that the DRAM is set in any combination of (14). In this case, the bank DB0 is 1M, and it can be seen that the bank DB0 is about to be accessed at present. I have.

Similarly, the column of “banks that may be accessed” of decode signals UA0-3 in FIG.
(3) (5) (7) (9) (11) (13) (15) Bank DB0 (4M) "is described when the decode signal UA0-3 is output. , Numbers (1) (3) (5) (7) (9) (11) (13) (1
There is a possibility that the DRAM is set in any combination of 5), in which case the bank DB0 is 4M, which indicates that it can be seen that the bank DB0 is currently being accessed. . Hereinafter, the same applies to the column of “banks that may be accessed” of other decode signals.

Next, a method of generating the bank row address selection signals RAS0 to RAS3 according to the value of the upper 4 bits of the 24 bits of the input address will be described with reference to FIGS.

[When the upper 4 bits are "0"] When the upper 4 bits of the address input to the address decoder 302 are "0", the address decoder 302 of FIG. 5 outputs the decode signals UA0 and UA0-3. At this time, the banks that can be accessed are as follows, as shown in FIG. No. (0) (2) (4) (6) (8) (10) (1
2) Bank DB0 of (14). This bank is 1M words. Numbers (1) (3) (5) (7) (9) (11) (1
3) Bank DB0 of (15). This bank is 4M words.

Here, the case where the bank DB0 is 1M and the case where the bank DB0 is 4M are shown. In the RAS controller 304 of FIG. 6, the AND gate 602 ANDs the decode signal UA0 with a signal indicating that the bank DB0 is 1M (the value obtained by inverting the memory size bit B0 by the inverter 630). The gate 601 performs an AND operation on the decode signal UA0-3 and a signal (memory size bit B0) indicating that the bank DB0 is 4M, and performs an OR operation on these outputs with an OR gate 621 to generate a 0th bank selection signal S0. Has been generated. Then, the 0th bank row address selection signal RAS0 is generated from the selection signal S0.

[When the upper 4 bits are "1"] When the upper 4 bits of the address input to the address decoder 302 are "1", the address decoder 302 of FIG. 5 outputs the decode signals UA0-3, UA1, and UA1-4. Is output.
At this time, the banks that can be accessed are as follows, as shown in FIG. Numbers (1) (3) (5) (7) (9) (11) (1
3) Bank DB0 of (15). This bank is 4M words. Bank DB1 of number (0) (4) (8) (12). This bank is 1M words. Bank DB1 of numbers (2) (6) (10) (14).
This bank is 4M words.

Here, when the bank DB0 is 4M,
Indicates that the bank DB1 is 1M, and that the bank DB1 is 4M.
This is the case for M. Therefore, the RAS controller 3 shown in FIG.
04, the decode signal U
A0-3 is ANDed with a signal indicating that the bank DB0 is 4M (memory size bit B0), and the 0th bank selection signal S0 is generated via the OR gate 621. Further, the decode signal UA1 is output from the AND gate 606.
And a signal indicating that the bank DB1 is 1M (a value obtained by inverting the memory size bit B1 by the inverter 631)
The AND gate 605 outputs a decode signal UA1-4 and a signal indicating that the bank DB0 is 1M (a value obtained by inverting the memory size bit B0 by the inverter 630) and indicates that the bank DB1 is 4M. An AND operation with a signal (memory size bit B1) is performed, and these outputs are OR-operated by an OR gate 622 to generate a first bank selection signal S1. Then, the first bank row address selection signal RAS1 is generated from the selection signal S1.

Hereinafter, the upper 4 bits of the address are "2" to
The same applies to the case of “15”. The address decoder 302 generates a decode signal as shown in FIG. 8 using the upper 4 bits of the 24 bits of the input address, and uses the decode signal and the value of the memory size register. A
ND gates 601 to 620 and OR gates 621 to 6
24, the selection signals S0 to S3 are generated. Then, based on the selection signals S0 to S3, the bank selection signal RA
S0 to RAS3 are generated.

FIG. 9 is a flow chart for explaining the operation of the electronic musical instrument of this embodiment. When the operation starts with this electronic musical instrument, first, in step 91, initial settings are made. Next, at step 92, the memory configuration is detected. The detection of the memory configuration is a process of detecting which DRAM of 1M or 4M is set in the four banks constituting the waveform memory 204. The detection result is written into the memory size register 301 in step 93. Next, key processing is performed in step 94, panel switch processing is performed in step 95, and other processing is performed in step 96. Thereafter, the flow returns to step 94.

Note that the detection of the memory configuration in step 92 is specifically performed as follows. First, assuming that all 4M DRAMs are connected, the entire memory space is divided into 16, and different data is written for each 1M area. When the data is read, if it is different from the written data, it is because an alias has been read, and it is determined that a 1M DRAM is connected to this area.
Thus, the combination of the memory sizes is determined. The result may be set in the memory size register 301.

Instead of detecting the memory configuration and setting the memory size register 301 by the CPU as described above, the state of the memory size may be set by a switch such as a dip switch. The set value may be stored in the memory size register from the beginning, or when a memory unit is inserted and used, the data indicating the configuration of the unit is stored in the unit so that the data can be read out. Alternatively, the data may be read and set in the memory size register. Further, the operator who has set the memory may manually input the setting.

In the above embodiment, a 1M word memory IC
And an example of combining a 4M word memory IC,
The capacity is not limited to this. Also, an example in which two types of ICs are combined has been described, but three or more types may be used.

[0081]

As described above, according to the present invention, information indicating the capacity of the memory IC is set in advance from the lowest address of the storage area, and the information is stored in advance. And a memory IC to be accessed by the address data is specified based on the upper predetermined bits of the address data and a selection signal for selecting the memory IC is output. The entire memory space configured by using can be mapped by continuous addresses, so that the effect of simplifying the configuration and simplifying the design can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic musical instrument to which a memory control circuit according to an embodiment of the present invention is applied.

FIG. 2 is a detailed block diagram of a sound source.

FIG. 3 is a detailed block configuration diagram of an address conversion unit and a waveform memory.

FIG. 4 is a configuration diagram of a timing generator and an address multiplexer.

FIG. 5 is a circuit diagram of an address decoder.

FIG. 6 is a circuit diagram of a RAS controller.

FIG. 7 is a diagram showing a DRAM combination table of each bank, an arrangement of banks, a DRAM connection example, and a memory space area;

FIG. 8 is a diagram showing a list of decode signals output by an address decoder;

FIG. 9 is a flowchart for explaining the operation of the electronic musical instrument of this embodiment.

FIG. 10 shows a conventional memory map of a memory space.

[Description of References] 101: keyboard, 102: waveform input unit, 103: microphone,
104: display, 105: panel switch, 10
6 central processing unit (CPU), 107 read-only memory (ROM), 108 random access memory (R)
AM), 109: sound source, 110: sound system, 1
11 bus line, 201 interface, 202
... Address generation unit, 203 ... Address conversion unit, 204 ...
Waveform memory, 205: direct write / read unit, 206 ...
Envelope generator, 207 multiplier, 208 digital-analog (D / A) converter, 301 memory size register, 302 address decoder, 303 address multiplexer, 304 RAS controller, 3
05 to 308 DRAM, DB0 Bank 0, DB1
... First bank, DB2 ... Second bank, DB3 ... Third bank.

Claims (1)

(57) [Claims] 1. A memory control circuit for accessing a storage area configured by mixing a plurality of memories having at least two or more different capacities with continuous address data, wherein an address of the storage area is Storage means for storing information indicating what capacity of memory is set in order from the lowest position, and a plurality of upper units related to memory selection of input address data
Multiple predetermined values are calculated separately for bits to perform multiple operations.
Calculation result, and the lower-order bits of the plurality of calculation results are set to zero.
The detection result, the plurality of calculation results
On the basis of the low-order bits other than the bit values, and the information stored in the storage means, identifies the memory to be accessed by the address data, generating selection signal for outputting a selection signal for selecting the memory And a memory control circuit.