JPS63188250A - Memory circuit for optional word length - Google Patents

Abstract

PURPOSE:To obtain a memory IC which can read and write the data of the optional word length by selecting the corresponding memory means for each bit out of those memory means in the number corresponding to the number of bits of the data based on the signal and the address to which the word length is designated. CONSTITUTION:The memory means 400-403 are provided in response to the number of bits of data. The write selecting means 200-204 select the corresponding memory means for each bit based on the word length designating signals W0 and W1 and an address and write data for each bit. While the read selecting means 500 and 501 select the corresponding memory means for each bit out of those memory means based on the word length designating signal and the address and read data for each bit. Thus it is not required to prepare plural types of products of different word lengths of data. Then a single memory IC can store the data of the optional word length.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a memory IC (integrated circuit), and in particular to an arbitrary word length memory that can store data of arbitrary and multiple types of word lengths in a single memory IC. Regarding circuits.

(Prior Art) In conventional memory ICs, the word length (number of bits of data) that can be read and written is determined for each IC product 1rI (lli type product), and memory IC users are required to use multiple types of products. Various circuits are designed by selecting a memory IC with the required word length from the series.

(Problems to be Solved by the Invention) Therefore, memory IC suppliers are required to supply multiple types of memory ICs with different memory word lengths.

Furthermore, if the word length of data that can be stored has to be changed due to various changes made after circuit design, memory IC users must replace the memory IC with another memory IC.

In order to solve the above problems, the present invention provides a memory I that can read and write data of any word length designated by a word length designation signal.
The purpose is to provide C.

(Means for Solving the Problems) In order to solve the above-mentioned problems and achieve the above objects, the arbitrary word length storage circuit provided by the present invention is capable of storing data that can be formed by one or more bits and the bits of the data. a buffer memory into which a word length designation signal for specifying the number of bits per word of the number and the address of the data are input; storage means whose number corresponds to the number of bits of the data; write selection means for selecting a corresponding storage means for each bit based on the word length designation signal and the address and writing the data bit by bit; The present invention is characterized in that a reading selection means is provided for selecting a storage means corresponding to each bit and reading out the data bit by bit.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows the arbitrary word length storage circuit of the present invention as an IC (integrated circuit).
FIG. In this embodiment, in order to simplify the explanation, there are three types of word lengths that can be specified: 1, 2, and 4 bits (=1 word).

Data IO, Il, I2 . I3 is input to input buffer 100. The input buffer 100 receives the data I
It performs ink face matching and input protection for O to I3. The four pieces of data 10 to 3 converted into IC internal signals via the input buffer 100 are guided to four write selection sections (DMX) 200 to 203, respectively.

On the other hand, address signals AO to A(n-1)c7>partially inputted into the IC via the input buffer 100 (two in this embodiment), AO (LSB: least significant bit), AI and the two word length designation signals wo and wt become input signals to the write selection sections 200 to 203.

Each write selection unit 200 to 203 receives a word length designation signal WO.
, Wl, the address signals AO and A1 are recognized as the lower two bits of the address, and the address signals AO and A are
One of the storage units MEMO to MEM3 is selected from the value of I. Further, if the number of bits of one word specified by the word length designation signals WO and Wl is 2, the write selection units 200 to 203 set the address signal A1 to the least significant bit of the address and set it to "0". ’ or “1”, the memory units MEMO and MEMI, or the memory unit MEM
2 and MEM3, that is, select one of the two storage units as a set. 0 Word length specification If the word length specified by store numbers WO and Wl is 4 bits, the address signal AO
, regardless of the value of Al, the four storage units MEMO to MEM3
Data 10 to data 3 are written in parallel. That is, each write selection section 200 to 203 is connected to a plurality of storage sections 400.
word length designation signals wo, wt and address signal AO from among .about.403.

A storage unit for storing each bit is selected based on A1. The remaining address signals A(n-1) to A2 of the n-2 (excluding address signals AO and AI) tree can be input to the address decoder 300 through the input buffer 100.

The result decoded by this address decoder 300 is
The data is input to each of the storage units 400 to 403 (MEMO to MEM3), and an address (only one storage element) for each bit in each of the storage units 400 to 403 is selected.

Through the above process, each data item (1)0 to
1 to each storage unit 400 to 403 selected according to the output of
It can be output bit by bit. The data that has been stored in each of the storage units 400 to 403 is stored in the lower two bits AO and AI of the address signal and the word length designation signal w, as in the case of data writing described above.
o, wt. The lower two bits AO and AI of these address signals and word length designation signals WO and Wl are applied to read selection sections 500 and 501. The data selected by the read selection units 500 and 501 is
C is outputted as an output signal 00, Of via an output buffer 600 that performs ink face matching with the outside.

Also, as is clear from Figure 1, the remaining two output signals are 0.
2 and 03 are connected to the corresponding storage unit 402 via the output buffer 600 without passing through the read selection units 500 and 501.
, 403 directly. Therefore, in this embodiment, each data can be written and read according to the word length of the data as shown in the following table.

Word length Input data Output data 2 IO
,1100,01 4IO,11,I2. I3 00.01.02.03
In the embodiment shown in FIG. 1, the word length of the data is 1 bit,
Although 2-bit and 4-bit type 3i type circuits are shown as examples, the present invention is not limited thereto, and can be applied as a data storage circuit having an appropriate number of pits of 4 bits or more.

Next, a case where the data has a word length of 1 bit will be explained with reference to FIG. Address AO as shown in Figure 2
, l and the word length designation signals WO, Wl, a signal DMXC indicating that the word length is 1 is sent to each write selection unit (DMXO to D
MX3) 200-203. As a result, data E0 is inputted sequentially. That is, the first 1st bit data is stored in MEMO via DMXO, the next 2nd bit data is stored in MEMI via DMXI, and the 3rd bit data is stored in MEM2 via DMX2. , the 4th bit data is sent to MEM via DMX3.
3 is stored. In addition, the read selection unit 500 (SE
LO) is the address AO, At and the word length designation signal WO,
A signal 5ELC indicating that the word length is 1 is given based on Wl, and each memory! 400 to 403 are selected, and the data in the selected storage units 400 to 403 (MEMO to MEM3) is output to the output buffer 760 as output data OO to 03.
Give to 0. Specifically, as shown in FIG. 2, 5ELO outputs the data stored in MEMO as output data OO, the data stored in MEMI as output data o1,
The memory data of MEM2 is output data 02, and the MEM
3 are respectively selected as output data 03.

In addition, in FIG. 2, H2 indicates high impedance.

Next, a case where the data has a word length of 2 bits will be explained with reference to FIG. Address AO as shown in Figure 3
, At and the word length designation signals WO, Wl, the signal DMXC indicating that the word length is 2 is selected for each write! 200-20
3 (DMXO-DMX3). As a result, the memory sections MEMO and MEMI, and the memory sections MEM2 and ME
Each M3 forms a pair and stores data. That is, the 1st bit of data IO is stored in MEMO, the 1st bit of data 1 is stored in MEM2, and then the 2nd bit of data IO is stored in MEMI, and the 2nd bit of data 11 is stored in MEMI. is stored in MEM3.

Next, the read operation will be explained. 5ELO and 5ELL select the corresponding storage units MEMO-MEM3 based on the signal 5ELC indicating that the word length is 2. That is, 5ELO selects MEMO as the first bit of the first data and MEMI as the second bit of data. 5
ELL is MEM as the 1st bit data of the next data.
2 and selects MEM3 as the second bit data. Therefore, MEMO and MEM2 are output as output data 00 and 01 at the first timing, and MEM2 and MEM2 are output at the next timing as output data 00 and 01.
The storage contents of EM1 and MEM3 are output.

Next, a case where the data has a word length of 4 pits will be explained with reference to FIG. As shown in FIG.
(DMXO to DMX3), data IO goes to MEMO, data 11 goes to MEMl, and data I2 goes to M
Data 3 is stored in EM2 and MEM3.

Next, when reading these data, output data 0
MEMO data is set as 0, and M is set as output data 01.
EMI data, MEM2 data can be output as output data 02, and MEM3 data can be output as output data o3.

(Effects of the Invention) As explained above, by applying the present invention, memory IC suppliers do not need to prepare multiple types of data with different word lengths, and can easily process data of any word length. It can be stored in one memory IC. Furthermore, the user of the IC memory also has the advantage of increased freedom in circuit design.

Furthermore, by switching the word length designation signal, the arbitrary word length storage circuit of the present invention can be used not only as a memory but also as a multi-purpose memory.
It can also function as a plexer and demultiplexer.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation when the word length is 1 bit, Fig. 3 is an explanatory diagram of the operation when the word length is 2 pits, and Fig. 4 is an illustration of the operation when the word length is 2 pits. The figure is an explanatory diagram of the operation when the word length is 4 bits. 100... Input buffer, 200-203... Write selection unit, 300... Address decoder, 400-
403...Storage unit, 500, 501...Read selection unit, 600...Output buffer.

Claims (1)

[Claims] a buffer memory for inputting data formed of one or more bits, a word length designation signal specifying the number of bits per word among the number of bits of the data, and an address of the data; and a buffer memory corresponding to the number of bits of the data. write selection means for selecting a corresponding storage means for each bit from among the storage means based on the word length designation signal and the address and writing the data for each bit; An arbitrary word length memory, characterized in that it is provided with readout selection means for selecting a corresponding storage means for each bit from among the storage means based on the word length designation signal and the address, and reading out the data bit by bit. circuit.