JP3309458B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device in a digital signal processor for performing various operations using a data memory.

[0002]

2. Description of the Related Art FIG. 6 shows a storage device used in a conventional digital signal processor. Conventionally, in a logical memory configuration, for example, as shown in FIG. 5A, when there are a plurality of data tables in which corresponding data contents between the data tables are different according to rules. , The 5th bit (LSB is counted as the 0th bit; hereinafter, the counting of the number of bits is the same as above) is different, but the other data are equal. (Fig. 7). In FIG. 6, 51
Is an input terminal, 52 is a data memory unit, and 53 is an output terminal.

The operation of the above conventional example will be described. FIG.
First, when a data memory designated address is input from the input terminal 51, the data memory unit 52 is accessed at the designated address, and the contents of the designated address are output to the output terminal 53.

[0004]

However, in the above-mentioned conventional storage device, even if the corresponding data contents among the plurality of data memories are different only by rules,
Since the memory configuration is used as it is, the memory area becomes large, and there is a problem that miniaturization cannot be achieved.

The present invention solves such a conventional problem. When the data contents corresponding to a plurality of data memories differ according to rules, the tables can be shared by simple control, and the data memories can be shared. It is an object of the present invention to provide an excellent storage device which can reduce the size of the device.

[0006]

In order to achieve the above object, the present invention achieves the above object by providing a corresponding address between a plurality of data tables.
Some bits data only different data tables of the data data according to a certain rule in the scan
Data converting unit for converting a data memory unit for storing and sharing, the corresponding data contents of the data memory storing shared the data content when accessing different data in a plurality of data tables in the data memory section It is provided with.

[0007]

The present invention has the following operation by the above configuration. First, when a designated address is input to a data memory configuration in which a corresponding data content has a plurality of data memory tables having different rules according to a rule, and the table is shared, a designated address is input. The contents are read from the data memory unit. Then, the data conversion unit converts the data content read from the data memory using a part of the designated address and a part of the output data from the data memory, and outputs a correct data content. By performing such simple control, the size of the data memory can be reduced.

[0008]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes an input terminal for receiving a designated address of a data memory, and reference numeral 12 denotes a data memory unit connected to the input terminal 11, which is miniaturized by sharing a table. Reference numeral 13 denotes a data conversion unit connected to the data memory unit 12. Since the data memory unit 11 shares a table, the data conversion is performed depending on the designated address. Reference numeral 14 denotes an output terminal connected to the data memory unit 12 and the data conversion unit 13, and sends out output data.

Next, the operation of the above embodiment will be described.
In the above embodiment, for example, a logical memory configuration as shown in FIG. 5A is used, and the data contents of the data table 1 and the data table 2 are different by one bit of the fifth bit (“0” in the data table 1, In the case of "1" in the data table 2, the tables of the data table 1 and the data table 2 are shared (see FIG. 5B), and
The data memory unit 12 has a physical memory as shown in FIG. First, the designated address is input to the input terminal 11 and accesses the data memory unit 12. The data output from the data memory unit 12 is converted in the data conversion unit 13 by a common external address and a part of the data output (data different between the shared data tables). Here, the input address “x′40” of the input terminal 11
When "0 '" is expressed in binary notation, "010000000000"
In this embodiment, the 0th bit to the 9th bit are set as a common address, and the 10th bit is set as a non-common address.
That is, the input address of the input terminal 11 is "x'40
0 '", the common address is" 0000000000000 ",
The common external address becomes "1".

FIG. 2 is a diagram showing a specific configuration and a processing state when the fifth bit is always "0" in the data table 1 and "1" in the data table 2, and da in FIG.
ta [5] is output data d from the data memory unit 12
The fifth bit in data [9: 0], that is, "0" for data table 1 and "1" for data table 2. Also, data [9: 6,4: 0] is 0 in the output data data [9: 0] from the data memory unit 12.
A data string of the fourth to fourth bits and the sixth to ninth bits indicates, for example, the data of the address “x'000 '” in the data table 1 is “00001”.
The address [10] indicates the 10th bit in the address, for example, “1” if the input address “x′400” of the input terminal 11.
The address [9: 0] indicates a column of the 0th to 9th bits in the input address of the input terminal 11, and for example, if the input address of the input terminal 11 is "x'400", "0"
0000000000 ". At this time, if the data memory configuration is as shown in FIG.
Using ss [10] and a part of data [5] of the data output, the data converter 13 can be configured with one AND gate, and the output data is output from the output terminal 14.

It should be noted that the range of data in the address or the range of data in the data table to be moved is determined in advance based on the configuration of the data memory, and this may be performed under the control of software or the like. It is.

FIG. 4 is a diagram showing the configuration of a second embodiment having a function of addressing a data memory unit in the above embodiment. In FIG. 4, 21 is an input terminal for receiving a designated address, 22 is a multiplexer / latch unit connected to the input terminal 21, and data to be accessed next which is data from the input terminal 21 or output from the latch unit 24. Select and hold a memory address. Reference numeral 23 denotes an address updating unit connected to the multiplexer / latch unit 22, which updates the address to the next designated address. In this example, 1
Add each time. Reference numeral 24 denotes a latch unit that holds the address updated by the address updating unit 23. 25 is a data memory unit, 2
Reference numeral 6 denotes a data conversion unit, which is equivalent to the data memory unit 12 and the data conversion unit 13 shown in FIG. 27
Is an output terminal.

Next, the operation relating to the data memory addressing function of the second embodiment will be described. First, the designated address of the data memory is received from the input terminal 21, and the multiplexer / latch unit 22 selects and holds either the data from the input terminal 21 or the data held in the latch unit 24. Specifically, this operation is performed based on an instruction from a control unit (not shown) which has previously programmed which data is to be selected. The data selected and held by the multiplexer / latch unit 22 is output to the data memory unit 25, and at the same time, the common address (the address is “x′40”).
In the case of 0 '"," 000000000000 "is output to the address updating unit 23, and after being updated (specifically, only 1 is added) for the next address designation, the updated data is latched by the latch unit 2.
Hold at 4. The multiplexer / latch unit 22
Selects the next designated address and outputs it to the data memory unit 25. At the same time, a series of operations in which the common address is passed to the address updating unit 23 are repeated. The operations of the data memory unit 25, the data conversion unit 26, and the output terminal 27 are the same as in the first embodiment.

As described above, according to the first and second embodiments, when the corresponding data contents differ among a plurality of data tables according to rules, these data are stored in an overlapped manner and shared. When the data is output as it is and different data is read between a plurality of tables, the data table can be shared by performing data conversion so that the desired data can be read, thereby reducing the size of the data memory. Can be achieved.

[0015]

As is clear from the above embodiment, when the corresponding data contents differ among a plurality of data tables according to rules, the present invention stores these data in a superimposed manner and stores the common data. Is output as it is, and when reading different data among a plurality of tables, data conversion can be performed so that desired data can be read, so that the data tables can be shared and the size of the data memory can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation in the first embodiment.

FIG. 3 is a diagram illustrating an example of a configuration of a physical memory according to the embodiment;

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5A is a diagram illustrating an example of a logical memory configuration. FIG. 5B is a diagram illustrating a main part of a physical memory configuration in the present embodiment.

FIG. 6 is a block diagram illustrating a configuration of a conventional storage device.

FIG. 7 is a diagram showing an example of a conventional logical memory configuration;

[Explanation of symbols]

 12, 25 data memory unit 13, 26 data conversion unit 22 multiplexer / latch unit 23 address update unit 24 latch unit

────────────────────────────────────────────────── (5) References JP-A-3-65097 (JP, A) JP-A-62-284444 (JP, A) JP-A-2-168498 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) G06F 12/00-12/06

Claims (2)

(57) [Claims] 1. An address corresponding to a plurality of data tables.
A data memory unit only <br/> part of bit data of the data is stored in common the plurality of different data tables according to the data is constant law in less varies in a plurality of data tables in the data memory section A data conversion unit that, when accessing data, shares the data content and converts the data content into a corresponding data content of a stored data memory. 2. An address updating unit for updating a designated address of a currently accessed data table to a designated address to be accessed next, and a designated address updated by the address updating unit and an arbitrary designation inputted from an input terminal. 2. The storage device according to claim 1, further comprising a multiplexer / latch unit for selecting an address and outputting the selected address to a data memory unit.