JPH06187236A - Storage device - Google Patents

Abstract

PURPOSE:To reduce the size of a data memory when corresponding data contents of plural data memories are regularly different by converting different data contents into corresponding data contents of the data memory when the different data in plural data tables at a data memory part are accessed. CONSTITUTION:A specific address is inputted to an input terminal 11 and the data memory part 12 is accessed. A data conversion part 13 converts the data contents of the data output from the data memory part 12 by using noncommon addresses and part of the data output and the output data are outputted from an output terminal 14. When the specific address is inputted to the data memory part 12 which is reduced in size by making the tables common in data memory constitution having plural data memory table whose corresponding data contents are regularly different, the contents of the address are outputted from the data memory part 12 and converted by the data conversion part 13 by using part of the specific address and the output data from the data memory, and the converted data contents are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device in a digital signal processor for performing various calculations using a data memory.

[0002]

2. Description of the Related Art FIG. 6 shows a storage device used by being incorporated in a conventional digital signal processor. Conventionally, in a logical memory configuration, for example, as shown in FIG. 5A, when there are a plurality of different data tables with corresponding data contents having a rule (in this example, the data tables 1, 2 are In 5th bit (counting the LSB as 0th bit, the same applies to the counting of the number of bits below), but other data are the same} I was taking it (Fig. 7). In FIG. 6, 51
Is an input terminal, 52 is a data memory unit, and 53 is an output terminal.

The operation of the above conventional example will be described. Figure 6
First, when a designated address of the data memory is input from the input terminal 51, the data memory unit 52 is accessed at the designated address and the contents of the designated address are output to the output terminal 53.

[0004]

However, in the above-mentioned conventional storage device, even when the corresponding data contents among a plurality of data memories only differ according to rules,
Since the memory configuration is used as it is, the memory area becomes large, and there is a problem that miniaturization cannot be achieved.

The present invention solves such a conventional problem, and when a plurality of data memories have different corresponding data contents according to a rule, a table is shared by simple control so that the data memories can be shared. It is an object of the present invention to provide an excellent storage device that is downsized.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides data in which a plurality of data tables that differ only in some data are physically overlapped and stored according to a certain rule among a plurality of data tables. A memory unit and a data conversion unit for converting different data in the plurality of data tables of the data memory unit into corresponding data contents of the data memory in which the data contents are physically overlapped and stored. It is a thing.

[0007]

The present invention has the following functions due to the above-mentioned structure. First, when the specified address is input to the data memory part that has a data memory configuration that has multiple data memory tables with different corresponding data contents according to rules, which is downsized by sharing the table, The contents are read from the data memory unit. Then, in the data conversion unit, the data content read from the data memory is converted using a part of the designated address and a part of the output data from the data memory, and the correct data content is output. By performing such simple control, the data memory can be downsized.

[0008]

1 is a diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, 11 is an input terminal for receiving a specified address of the data memory, and 12 is a data memory unit connected to the input terminal 11, which is miniaturized by sharing a table. Reference numeral 13 is a data conversion unit connected to the data memory unit 12. Since the data memory unit 11 shares a table, the data contents are converted depending on the designated address. An output terminal 14 is connected to the data memory unit 12 and the data conversion unit 13, and outputs output data.

Next, the operation of the above embodiment will be described.
In the above embodiment, for example, the logical memory structure as shown in FIG. 5A is used, and the data contents of the data table 1 and the data table 2 are different from each other by one bit of the fifth bit (“0” in the data table 1, In the case of "1" in the data table 2, the tables of the data table 1 and the data table 2 are shared (see FIG. 5B),
The data memory unit 12 has a physical memory as shown in FIG. First, the designated address is input to the input terminal 11 to access the data memory unit 12. The data output from the data memory unit 12 is converted in the data conversion unit 13 by the common external address and a part of the data output (data different between the shared data tables). Here, the input address "x'40 of the input terminal 11"
If 0 '"is written in binary," 0100000000 "
However, in the present embodiment, the 0th bit to the 9th bit are the common address, and the 10th bit is the common external address.
That is, the input address of the input terminal 11 is "x'40".
In case of 0 '", the common address is" 000000000000 ",
The common external address is "1".

Further, FIG. 2 is a diagram showing a specific configuration and a processing state when the fifth bit is always "0" in the data table 1 and "1" in the data table 2, and da in the figure
ta [5] is the output data d from the data memory unit 12.
The fifth bit in ATA [9: 0], that is, "0" for data table 1 and "1" for data table 2 is indicated. Further, data [9: 6,4: 0] is 0 in the output data data [9: 0] from the data memory unit 12.
The data string of the 4th bit to the 4th bit and the 6th bit to the 9th bit is shown. For example, in the case of data at the address "x'000 '" in the data table 1, "00001"
1111 ″. Further, address [10] indicates the 10th bit in the address, for example, “1” if the input address “x′400 ′” of the input terminal 11 is present.
address [9: 0] indicates a sequence of 0th bit to 9th bit in the input address of the input terminal 11, and, for example, if the input address of the input terminal 11 is "x'400 '", it is "0".
5000000 ″. At this time, if the data memory configuration is as shown in FIG.
By using ss [10] and a part of data output data [5], the data conversion unit 13 can be configured with one AND gate, and the output data is output from the output terminal 14.

The range of data in the address or the range of data in the data table to be moved may be determined in advance based on the configuration of the data memory and controlled by software or the like. Is.

FIG. 4 is a diagram showing the structure of the second embodiment having the function of addressing the data memory section in the above embodiment. In FIG. 4, reference numeral 21 is an input terminal for receiving a designated address, 22 is a multiplexer / latch unit connected to the input terminal 21, and the data from the input terminal 21 or the output from the latch unit 24 is the data to be accessed next. Select and hold the memory address. An address updating unit 23 is connected to the multiplexer / latch unit 22 and updates the address to be specified next. In this example, 1
Add one by one. Reference numeral 24 is a latch unit that holds the address updated by the address updating unit 23. 25 is a data memory unit, 2
Reference numeral 6 denotes a data conversion unit, which is equivalent to the data memory unit 12 and the data conversion unit 13 shown in FIG. 1, respectively. 27
Is an output terminal.

The operation relating to the data memory addressing function of the second embodiment will be described next. First, the designated address of the data memory is received from the input terminal 21, and the multiplexer / latch unit 22 selects and holds either the data from the input terminal 21 or the data held in the latch unit 24. Specifically, this operation is performed based on an instruction from a control unit (not shown) in which which data is selected is programmed in advance. The data selected and held by the multiplexer / latch unit 22 is output to the data memory unit 25, and at the same time, the common address (address is "x'40"
In the case of 0 ′ ″, “0000000000”) is output to the address updating unit 23, and after updating (specifically, adding 1) for the next address designation, the updated data is latched by the latch unit 2
Hold at 4. Then, the multiplexer / latch unit 22
Then, the next designated address is selected and output to the data memory unit 25. At the same time, the series of operations of passing the common address to the address updating unit 23 is repeated. The operations of the data memory unit 25, the data conversion unit 26, and the output terminal 27 are the same as those in the first embodiment.

As described above, according to the first and second embodiments, when the corresponding data contents among the plurality of data tables differ according to the rules, these data are overlaid and stored to be common. The output data is output as it is, and when different data is read between multiple tables, the data table can be shared by converting the data so that the desired data can be read, and the size of the data memory can be reduced. Can be achieved.

[0015]

As is apparent from the above-described embodiment, the present invention stores common data when a plurality of data tables have different corresponding data contents due to rules. Is output as it is, and when different data is read between a plurality of tables, the data table can be shared by converting the data so that desired data can be read, and the size of the data memory can be reduced. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation in the first embodiment.

FIG. 3 is a diagram showing an example of a configuration of a physical memory of this embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5A is a diagram showing an example of a logical memory configuration. FIG. 5B is a diagram showing a main part of a physical memory configuration according to the present embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional storage device.

FIG. 7 is a diagram showing an example of a conventional logical memory configuration.

[Explanation of symbols]

 12, 25 Data memory section 13, 26 Data conversion section 22 Multiplexer / latch section 23 Address updating section 24 Latch section

Claims (2)

[Claims] 1. A data memory unit in which a plurality of data tables in which only some data differ according to a certain rule are physically overlapped and stored between a plurality of data tables, and in the plurality of data tables of the data memory unit. A storage device comprising a data conversion unit that converts different data contents into corresponding data contents of a data memory that is physically overlapped and stored when different data is accessed. 2. An address updating unit for updating the specified address of the currently accessed data table to a specified address to be accessed next, and the specified address updated by this address updating unit and any specification input from the input terminal. The storage device according to claim 1, further comprising a multiplexer / latch unit for selecting an address and outputting the selected address to the data memory unit.