JPH0266652A - Cache memory - Google Patents

Cache memory

Info

Publication number
JPH0266652A
JPH0266652A JP63219326A JP21932688A JPH0266652A JP H0266652 A JPH0266652 A JP H0266652A JP 63219326 A JP63219326 A JP 63219326A JP 21932688 A JP21932688 A JP 21932688A JP H0266652 A JPH0266652 A JP H0266652A
Authority
JP
Japan
Prior art keywords
memory
array
address
cache
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63219326A
Other languages
Japanese (ja)
Inventor
Takashi Yamazaki
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP63219326A priority Critical patent/JPH0266652A/en
Publication of JPH0266652A publication Critical patent/JPH0266652A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To attain the process continuation of a cache memory by updating the contents of an address array and a data array after detection of a memory error and setting a 2nd additional bit to inhibit the replacement of the address array of the corresponding cache.
CONSTITUTION: If an external memory has its abnormality when it receives an access in a memory reading state, the access address is written into an address array 2 together with 'F' set. When the memory receives the second writing action in the same address, a writing action is carried out to a data array 3 of a cache memory since 'F' is set up in the array 2. At the same time, a memory error signal 16 is inhibited by a GT 7 with a memory access given for writing the external memory and therefore never reported to an MPU 100. In the same way, a cache hit state is always kept when the memory is read via the same address since 'F' is set in the array 2. Hereafter the process continues with an access given to a cache memory 1 only.
COPYRIGHT: (C)1990,JPO&Japio
JP63219326A 1988-08-31 1988-08-31 Cache memory Pending JPH0266652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63219326A JPH0266652A (en) 1988-08-31 1988-08-31 Cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63219326A JPH0266652A (en) 1988-08-31 1988-08-31 Cache memory

Publications (1)

Publication Number Publication Date
JPH0266652A true JPH0266652A (en) 1990-03-06

Family

ID=16733712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63219326A Pending JPH0266652A (en) 1988-08-31 1988-08-31 Cache memory

Country Status (1)

Country Link
JP (1) JPH0266652A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381544A (en) * 1991-01-22 1995-01-10 Hitachi, Ltd. Copyback memory system and cache memory controller which permits access while error recovery operations are performed
US5564034A (en) * 1992-09-24 1996-10-08 Matsushita Electric Industrial Co., Ltd. Cache memory with a write buffer indicating way selection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381544A (en) * 1991-01-22 1995-01-10 Hitachi, Ltd. Copyback memory system and cache memory controller which permits access while error recovery operations are performed
US5564034A (en) * 1992-09-24 1996-10-08 Matsushita Electric Industrial Co., Ltd. Cache memory with a write buffer indicating way selection

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