JPH02268351A - Error processing system for store cache part - Google Patents

Abstract

PURPOSE:To reduce the error processing and to improve the reliability by constituting a buffer storage device for data storage, namely, a store cache part of a main storage device so that error is not reported regardless of error of store data when its entry is not used. CONSTITUTION:When parity error is detected by a parity check circuit 2-1 of a cache address part 2 or a parity check circuit 3-1 of a valid bit part 3 and error and a flip bit are '0' and '1' respectively or they are '1' and '0' respectively, an error control part 8 inhibits the error report. That is, an error signal (b) is not generated for the error which is not directly related to current registration of constituting elements in the cache address part 2 and the valid bit part 3. The generation of a hit signal (a) in a hit control part 6 is suppressed, and the error is handled as mishit and a recoverable error.

Description

[Detailed Description of the Invention] [Summary] Regarding the error handling method in the buffer storage device (store cache section) for storing data in the main storage device, conventionally, all errors in the store cache section are errors that cannot be retried. The purpose of this is to solve the problem that could cause a system down even for less important errors.If an error occurs in the address register or valid bit part when accessing a store, it is processed as a cache. a first means for suppressing the hit signal of the error, and generating an error signal if the error occurred in the entry indexed by the flip bit, and generating an error signal if the error occurred in the entry indexed by the flip bit; A second means for suppressing generation of an error signal is provided.

[Industrial Application Field] The present invention relates to a store cache unit in a case where a main storage device includes a buffer storage device for storing data (hereinafter, the buffer storage device is also referred to as a “store cache unit”). Regarding the handling method for malfunctions (errors).

[Prior Art] Figure 2 shows a buffer storage device for storing data in the main memory! i! (store cache unit). In the example shown in the figure, two main storage units (MSU) are each connected to a main storage control unit (MCU), and each main storage control unit (MCU) This is an example of a multiprocessor system consisting of a total of four central processing units (CPUO to CPU3), in which two central processing units (CPUs) are connected to each of the CPUs.

As shown in the figure, each main memory unit (MCU) is provided with a store cache unit for storing data.
Central processing unit (CPU) or channel control unit (CHP)
), the stored data (hereinafter also referred to as "store data") is registered in the store cache section, and
In the case of partial store (partial write), the data in the store cache section is read, thereby improving the processing speed of the entire system.

FIG. 3 is a diagram showing the configuration of a conventional store cache section, and this figure shows only the portions related to processing of address data in the store cache section. Note that the part where the store data is registered is omitted for the sake of clarity in this drawing.

In FIG. 3, 1 is an address register (ADH) for temporarily holding the address of store data (hereinafter also referred to as "store address") sent from the main memory control unit (MCU) to the main memory unit (MSU). , 2 is a cache address section for registering the address of store data (store address), and 2a is "0" provided corresponding to CPU0.
1 side cache address register, 2b are the same <CP
b side cache address register provided corresponding to U0, 2C is "0" side cache address register provided corresponding to CPU1, 2d is same < CPU
2e is the cache core address register on the "1" side provided corresponding to CPU3, and "0" is provided corresponding to CPU3.
″ side cache address register, 2f is the same <CP
1" side cashier address register provided corresponding to U3, 2g is "0" provided corresponding to CPU3
The side cache address register, 2h, is also the CPU
The "1" side cache address register is provided corresponding to 3, and 2-1 is the parity register of the cache address section.
Parity check circuit (PC) for checking
, 3 is the entire valid bit section for indicating whether the cache is valid or invalid, and 3a is "0" provided corresponding to CPU0.
Valid bit on the side, 3b is the same < Valid bit on the “1” side provided corresponding to CPU0, 3c is the CPUI
Valid bit on the “0” side provided corresponding to 3
d is the same <valid bit on the "1" side provided corresponding to CPUI, 3e is 1 provided corresponding to CPU2
0" side valid bit, 3f is the same <'1" side valid bit provided corresponding to CPU2, 3g is CP
Valid bit on the “θ” side provided corresponding to U3,
3h is a valid pit on the "1" side provided corresponding to the same CPU 3, and 3-1 is a parity check circuit (PC) for checking the parity of the valid pit section 3.
, 4 is the entire flip pit section consisting of a plurality of flip-flops that select the two sets of cache address registers ``0'' side and ``1'' side in the cache address section 2, 4a
is a flip pit provided corresponding to CPU0, 4b
is a flip pit installed in accordance with CPIJ 1,
4C is a flip pit provided corresponding to CPU2,
4d is a flip pit provided corresponding to CPU3,
Reference numeral 5 indicates a comparison circuit provided for each CPU 0 to 3 that compares the contents of the address register 1 and the cache address section 2 and generates a match signal. 6 indicates a match signal of the comparison circuit 5 and a parity error of the parity check circuit 2-1. A signal parity check circuit and a circuit 3-1 create a hit signal from the parity error signal. ) is a circuit that reports errors to

In the example shown in the figure, the store cache section in the main memory (MSIJ) has a cache address register (for example, 2'a for CPU0) that holds two winter door addresses for each of CPU0~3. , 2b).

Store data from the main memory control unit (MCU) is held in the address register (ADR) 1, and the contents of the address register (ADH) 1 and each CPU
The content of the cache address register in the cache address section 2 corresponding to . Then, a hit signal a indicating that the corresponding data is present is generated.

At the same time, cache address 'F! When A2 and valid bit section 3 are accessed, "error detection" is performed by the parity check circuits 2-1 and 3-1, respectively, and if an error occurs, the occurrence of No. 48a is detected. At the same time, it outputs an error signal via the OR circuit 7, and the error is notified to the main memory control unit (MCU) as a hardware failure error.

In this way, by providing a store cache unit in the main storage unit (MSU), data is efficiently stored in the main storage unit (MSU), the processing speed of the entire system is improved, and the store cache unit If an error occurs, an error signal is notified to the main memory control unit (MCU).

[Problem to be solved by the invention] In the conventional example described above, errors in the data storage system are treated as hardware failures and cannot be retried due to their importance. It is treated as an error.

By the way, as mentioned above, the data held in the store cache section in the main storage unit (MSU) consists of store data and store addresses, but if an error occurs in the store address, the error occurs in the store data. The extent of the failure is milder than the error, and the error occurred in the store cache unit, and the main storage unit (MSU)
Considering that the error did not occur in the internal main memory, it is not necessarily appropriate to immediately treat an error that occurs in the address section as an error that cannot be retried, and unnecessarily increases the possibility of system failure. This resulted in an increase in the burden of error handling and a decline in the ability to apply for multiple applications.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an error processing method for a store cache unit that can handle errors in the store cache unit as errors that allow processing to continue.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention provides a cache address register section that holds a store address, a cache data register section that holds store data, a valid bit section that indicates the valid state of the cache, and a cache address register section that stores the store address and store data. A store cache for store data, which is composed of a flip pit section that indicates which entry in an entry section that can be registered, and an error check circuit for the address register section, data register section, and valid bit section. If an error is detected in the address register section or valid bit section during a store access in the store cache section, a hit signal to the cache due to the store access is sent. a first means for suppressing, and generating an error signal if the error occurs in the entry indexed by the flip pit;
If the error does not occur in the entry indexed by the flip pit, a second
If an error that occurs in the address register section or valid bit section in the store cache section does not occur in the entry indexed by the flip pit, the generation of the error signal is suppressed and processing can continue. [Function] Conventionally, when an error is detected during data storage in the buffer device (store cache section) for storing data in the main storage device, these errors are handled as errors. Retry all errors (retry)
This is treated as an impossible error, which increases the burden of error processing and reduces reliability.

In the present invention, errors in the part that processes store addresses in the store cache section are handled as follows, since the degree of the error is light.

(1) If an error occurs when attempting to register a store address in the store cache section, and if the error occurs in the entry section of the register, etc. where the store address is currently being registered, , generate an error signal as usual and notify the main memory control unit (MCU). 2) If the above error does not occur in the entry part of the register etc. where the store address is currently being registered, Suppress generation of error signals.

In this way, generation of an error signal is suppressed for specific errors occurring in the store cache section, thereby reducing the burden of error processing.

[Embodiment] FIG. 1 is a diagram showing an embodiment of the present invention, and 8 represents an error control unit, which reports an error occurring in the store cache unit as an error to the main memory control unit (MCU). The other symbols are the same as those in the conventional example shown in FIG.

As in the case of the conventional example shown in Fig. 3, the cashier address afs
Two sets of valid bit section 2 and valid bit section 3 are prepared for each CPU 0 to 3 (indicated by "0" side and "1'" side, respectively), and when registering store data in this store cache section, The flip-pit section 4 controls whether the address of the store data is registered in the "O" side register or the '1'' side register in the cache address section 2.

That is, when the flip pit in the flip bit section 4 corresponding to each CPU 0 to 3 is "0", the "0" side is set to "1".
At the time of °, control is performed to register in the cache address register on the "1'" side.

Next, the operation of the error control section 8, which is directly related to the error processing method of the present invention, will be described below.

In this error control section 8, when a parity error is detected in the parity check circuit (PC) 2-1 of the cashier address section 2 or the parity check circuit (PC) 3-1 of the valid bit section 3, the error is set to 0. ’ side, the flip bit is 1°, or the error is “1” side, the flip bit is “0”.
゜The configuration is configured to prohibit error reporting.

The above operations in the error control section 8 are summarized as shown in the table below.

That is, for errors in components in the cache address section 2 and valid pit section 3 that are not directly related to the current registration, the error signal is not generated, and the hit signal in the hit control section 6 is The configuration is configured so that the occurrence of "a" is also suppressed, and it is treated as a non-hit, so that it can be treated as an error that can be retried.

[Effects of the Invention] As explained above, according to the present invention, even if there is an error in the stored data in the store cache section when storing data to the main memory, the entry is not used with a relatively small amount of hardware. By not sometimes reporting errors, it is possible to reduce error processing during data storage and improve reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the store cache section of the present invention, FIG. 2 is a diagram explaining the store cache section in the main memory, and FIG. 3 is a diagram showing the configuration of a conventional store cache section. be. 1... Address register (ADR,), 2...
Cache address section, 2a to 2h... Cache address register, 2-1... Parity check circuit (
PC), 3... Valid bit part, 3a to 3h...
Valid pit, 3-1... Parity checker circuit (PC) 4... Flip bit tl, 4a to 4d
...Flip bit, 5.Comparison circuit, 6.Hit control section, 7.OR circuit, 8.Error control section

Claims (1)

[Scope of Claims] A cache address register section that holds a store address, a cache data register section that holds store data, a valid bit section that indicates the valid state of the cache, and a cache address register section that holds the store address and the store data. A store cache for store data, which is comprised of a flip bit section that indicates which entry in an entry section that can be registered, and an error check circuit for the address register section, data register section, and valid bit section. If an error is detected in the address register section or valid bit section during a store access in the store cache section, a hit signal to the cache due to the store access is sent. a first means for inhibiting; generating an error signal if the error occurs in the entry indexed by the flip bit; and if the error does not occur in the entry indexed by the flip bit; A second means for suppressing the generation of an error signal is provided, and if an error that occurs in the address register section or valid bit section in the store cache section does not occur in the entry indexed by the flip bit, the error signal is suppressed. An error handling method for a store cache section that is characterized by suppressing the occurrence of an error and treating it as an error that allows processing to continue.