JPH01222351A - Check system for cache memory - Google Patents

Abstract

PURPOSE:To improve reliability without reducing an access speed by checking a cache memory by means of using the idle time of the action of the cache memory. CONSTITUTION:When the copy of data of a main storage device 4 which a CPU 1 accesses does not exist on the cache memory, data is accessed from the main storage device 4. At that time, data accessed from the main storage device 4 and the high order bits of the address of data are respectively written in a BS (Buffer Strage) 3 and AA (Address Array) 2 in the cache memory and the writing terminates at a short time since memory elements used for AA2 and BS3 are at high speed. Since the main storage device is in a low speed on the other hand, the cache memory comes to wait for the access termination of the main storage, and the cache memory is checked by using the wait time. Thus, the reliability of AA2 and BS3 consisting the cache memory can easily be improved without reducing the access speed of the cache memory.

Description

[Detailed description of the invention]

1. Field of the Invention The present invention relates to a storage device in an information processing device, and more particularly to a memory check method suitable for a hierarchical structure using cache memory.

[Conventional technology]

A high-speed cache memory is generally used as a means to apparently speed up data access from a central processing unit (CPU) to a slow main memory. In this method, data access by the CPU is first performed to the cache memory to which part of the main memory data has been copied, and the main memory is accessed only if the desired data does not exist in the cache memory. 0In a normal program, data access has locality, so by copying appropriate data to the cache memory, most data accesses from the CPU can be completed by accessing the high-speed cache memory only. can. An example of the configuration of the cache memory method is shown in FIG. 2. The cache memory includes a BS (Buffer Storage) 3 in which a copy of the data in the main memory 4 is stored, and information indicating the address of the main memory 4 copied to the BS 3. AA (Address Array) where is stored
2 and a comparator 5 that checks whether a copy of the desired data exists in the cache memory. BS3 and AA2 are addressed using the lower bits of the value of address bus 8 output by CPU1,
The remaining upper bits are written to AA2 when copying data to BS3, and are compared by comparator 5 with the value read from AA2 when accessing the cache memory. If the outputs from the comparator 5 match (hereinafter referred to as hits), the selector 7 selects the data read from the BS 3 and sends it to the CPUI via the data bus 9. On the other hand, if the result is that they do not match (hereinafter referred to as a miss), the selector selects the data read from the main memory 4 and sends it to the CPU 1 via the data bus 9. When a miss occurs, the contents of AA2 and BS3 are updated through buffer 6. The time chart in Figure 3 shows the operation when a mishit occurs.
10 is the value of address bus 8, 11 is read from AA2,
12 is writing to AA2, 13 is reading from BS3, 14
15 is a write to the BS3, and 15 is a read from the main memory 4. Here, the data used for writing 12 to AA2 is the upper bit of value 10 of address bus 8. Further, the data used for writing 14 to the BS 3 is the data obtained by reading 15 from the main memory 4. Conventionally, as a method for improving the reliability of cache memory, it has been common to provide parity bits in AA2 and BS3 and perform a parity check, as described in Japanese Patent Laid-Open No. 117348/1983. Note that the parity bit reflects the number of "l"s included in the data, and by generating and checking the parity bit so that the number of "l"s included in the data and parity bits is an odd or even number. 1 bit errors can be detected. FIG. 4 shows the configuration of a cache memory with a parity check function. When reading from AA2 or BS3, parity check is performed by parity checker 16. If an error is detected, parity check is performed by parity checker 16. The output error signal causes the data from the main memory 4 to be sent to the CPUI as a miss. By employing this parity check method, it is possible to eliminate 1-bit errors occurring in AA2 and BS3. ■Problems to be Solved by the Invention] By the way, storage devices are required to be highly reliable in response to increased capacity and higher integration of memory elements, and main storage devices are equipped with ECC (Error Correcting C
It is common to provide a 2-bit error detection and 1-bit error correction function using the . However, E.C.
In the C method, creation of inspection information and error checking,
It takes a long time to make corrections, making it difficult to apply it to cache memories that require particularly high speed. For this reason,
Generally, as in the prior art described above, a parity check method is adopted for the AA2 and BS3 that constitute the cache memory. Parity check method is AA2 or BS3
If a 1-bit error occurs, data in the main memory 4 is used, so the CPUI is superior in that it can continue processing without stopping the program being executed. However, if a 2-bit error occurs in AA2 or BS3, it cannot be detected, so there is a problem in that reliability is lower than in the ECC method. An object of the present invention is to easily improve the reliability of AA2 or BS3 constituting a cache memory without reducing the access speed of the cache memory. 1. Means for Solving the Problems In order to achieve the above object, a memory check method according to the present invention provides an information processing apparatus that includes a storage device having a hierarchical structure of at least a main memory and a cache memory. The memory check of the cache memory is performed using idle time during operation. As the free time, for example, when accessing the main memory at the time of a miss, the time generated due to the difference in access time between the main memory and the cache memory can be used. ] Effect 1' As described above, if a copy of the data in the main memory 4 accessed by the CPUI does not exist in the cache memory, that is, in the case of a miss, the data is accessed from the main memory 4. At this time, B-S 3 of the cache memory
The data accessed from the main memory and the upper bits of the address of the data are respectively written to AA2. This writing can be completed in a short time because the memory elements used for AA2 and BS3 are high speed. On the other hand, since the main memory is slow, the cache memory must wait for the access to the main memory to end. This waiting time can be used to check the cache memory. As a method of checking, for example, if the content you have just written is
This can be done by reading data from A2 or BS3 and comparing it with the written data, or by writing normal data into AA2 or BS3, reading it out continuously, and comparing the read data with the written data. This check makes it possible to detect a failure occurring in AA2 or BS3.

【Example】

An embodiment of the present invention is shown in FIG. 1 and will be described below. The feature of this embodiment is that the check read 17 is performed after data is written to AA2 at the time of a miss. To describe the operation in order, when a data access occurs from CPU 1, data is first read 11 from AA2 and compared with the upper bit of value 10 of address bus 8 by comparator 5. When there is a mishit, the output of the comparator 5 indicates a mismatch. At this time, data read 13 from BS3 as well.
However, this data is not used. On the other hand, since the output of the comparator 5 indicates a mismatch, the data is stored in the main memory 4.
Reading 15 from is started. Before this reading 15 from the main memory 4 is completed, the upper bit of the value 10 of the address bus 8 is written to AA2 as data, and the check reading 17 is performed from AA2.
The comparator 5 compares the data read out with the upper bit of the value lO of the address bus 8, and if they do not match, it is determined that AA2 is faulty, and the cache memory is bypassed in subsequent accesses. If the comparison results match, the read data from the main memory 4 is sent to cput, and the data is written 14 to the BS 3 as data, thereby ending the access. In this embodiment, the check circuit uses a
The comparator used for mishit judgment can be used as is, and A can be achieved without increasing the amount of hardware.
This has the effect of being able to check A2. FIG. 5 shows another embodiment of the present invention. This embodiment is characterized in that a check write 18 and a check read 19 are performed to the BS 3 during a check when a cache miss occurs. Namely. Normal read 1 of BS3 when cache miss occurs
Between 3 and normal write 14, check data is written to BS3 by check write 18, and then data is read from BS3 by check read 19, and this read data is compared with the check data. By doing so,
Detects failure of BS3. The value used as the check data is arbitrary, but if a value that is the inversion of "1" and "0" of the data read in the normal reading 13 is used,
The check is very effective because it can be confirmed that both "1" and "0" can be read and written to each bit of BS3. In the above embodiment, an example was given in which only one of AA2 and BS3 is checked, but both can be checked at the same time. It is also possible to use it in conjunction with a parity check method.

【Effect of the invention】

According to the present invention, 1-bit or multi-bit failures in the AA and BS that constitute the cache memory can be easily checked by using the free time of the cache memory while the system is operating, thereby reducing the access speed. reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a time chart of an embodiment of the present invention, FIG. 2 is a block diagram of a configuration example of a cache memory to which the present invention can be applied, FIG. 3 is a time chart of a conventional cache memory, and FIG. 4 is a conventional cache memory. FIG. 5 is a block diagram of a configuration example of the parity check method, and FIG. 5 is a time chart of another embodiment of the present invention. l... CPU 2... AA 3... BS 4... Main memory 5... Comparator 11... AA reading 12... AA writing 13... BS reading 14... ...Write BS 15...Read main memory 17 -A Read for check of A 18...Write for BS check 19 -Read for check of BS

Claims (1)

[Claims] 1. In an information processing device equipped with a storage device having a hierarchical structure consisting of at least a main memory and a cache memory,
A memory check method for a cache memory, characterized in that a memory check of the cache memory is performed using idle time during operation of the cache memory.