JP2546411B2 - Cache memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly to control processing of an error that occurs during indexing of a cache memory.

Conventional Technology Generally, a cache memory is a high-speed, highly integrated RAM (R
andom Access Memory), but this type of R
AM has a high frequency of failures such as intermittent errors during reading and bit value inversion (soft error) of memory due to radiation.

In the case of an intermittent error, it may be possible to normally read by reading again, and when the bit value of the memory is inverted, it is possible to recover by writing again.

Conventionally, in this type of cache memory device, even if an error is detected at the time of indexing the cache memory, the index result of the cache memory is forcibly forced until the error is repaired by rewriting or the like without immediately causing a failure. In some cases, the requested data does not exist in the cache memory, and the data in the main storage device is controlled to be used as a so-called cache mishit.

On the other hand, when the store data is written in the cache memory by the store request, the cache memory is indexed by the store address and whether or not the data in the main memory at the address is stored in the cache memory, that is, whether or not the cache is hit. Check if there is a mishit, and if it is stored in the cache memory, write the store data to both the cache memory and the main memory, and if it is not stored in the cache memory, write the store data only to the main memory and write it to the cache memory. Often uses a so-called store-through method, in which store data is not written.

In the above-described store-through type cache memory device, if an intermittent error is detected by the index of the cache memory due to a store request and the index result of the cache memory is forced to be a cache mishit, the store address Even if the data of the main storage device for the above is stored in the cache memory, the store data is only reflected in the main storage device and is not reflected in the cache memory.

Therefore, in this state, when the cache memory is indexed by the subsequent memory read request at the same address as the store request, assuming that the intermittent error is corrected and the data is normally read, the data in the main memory device at that address is cached. Since the data is stored in the memory, the data that does not reflect the above-mentioned store data is read, and the data causes a malfunction.

Therefore, if an error is detected when the cache memory is indexed by a store request, use of the entire cache memory (or the entire level where the error is detected if the cache memory is configured with multiple levels) Was supposed to be banned.

After that, for example, an interrupt request is output to the fault handling firmware or software at the breaks between instructions, the cache memory is initialized, the cache memory is restored, and then the instructions are retried to ensure continuous operation of the system. Was running.

In such a conventional cache memory device, when an error is detected in the cache memory index by a store request, the entire cache memory or the entire level in which the error is detected when the cache memory is composed of multiple levels Since the use of the cache memory is prohibited and the initialization of the entire cache memory is executed thereafter, there is a drawback that the system performance is significantly reduced while the use of the cache memory is prohibited.

In addition, since the entire cache memory is initialized and the cache memory failure is restored, all the cache memory data that has been accumulated up to that point is lost, resulting in a significant decrease in system performance. There is.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and provides a cache memory device capable of performing continuous operation of a system while minimizing performance degradation of the system when an error is detected. With the goal.

According to the present invention, a cache memory device according to the present invention includes a detection unit that detects an error in an index of a cache memory that stores a part of data in a main storage device, and the cache memory when the error is detected by the detection unit. A first deterrent means for making the result of the index to be a mishit,
When an error in the index to the cache memory due to a store request is detected by the detection unit, an error is found in the address holding unit that holds the index address of the cache memory, and the index to the cache memory due to the store request by the detection unit. Error information storage means for storing error information indicating whether or not detected, corresponding to an address of the cache memory; and the index according to the error information read from the error information storage means at the time of indexing the cache memory. Second deterring means for making the result of the above as a mishit, and the index holding address of the index of the cache memory that is continuous with the index for the cache memory by the store request in which the error is detected by the detecting means, and held in the address holding means. Was done A comparison means for comparing the reference address with the reference address, a third suppressing means for making the result of the index a mishit when a match is detected by the comparison means, and the data of the main memory device is registered in the cache memory. And a means for updating the contents of the error information storage means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the configuration of the address array unit of the data array unit and the address array unit that constitute the cache memory according to the embodiment of the present invention is shown.

Here, the data array unit holds a part of the data in the main storage device in block units (64-byte units) and holds a plurality of block data, and the address array unit manages the block addresses of these block data.

The address array unit is indexed by the address width corresponding to the size of the cache memory, that is, the number of all block data registered in the cache memory.

The lower part of the block address of the main memory is used as this cache index address (hereinafter referred to as the index address), and the upper part of the block address corresponds to the index address as the cache key address part (hereinafter referred to as the key address part). Stored in position.

When indexing the cache memory, the key address part in the address array part is read by the index address and this key address part is compared with the part corresponding to the key address part of the block address of the main memory.

If the comparison result shows a match, there is a cache hit, and the block data of the main memory device at this address also exists in the cache memory.

On the other hand, if the comparison result shows a non-coincidence, it means a cache miss, and the block data of the main memory at this address does not exist in the cache memory.

The data array section is indexed by an address that is the index address used in the index of the address array section plus the address within the block determined by the requested data width from the data request source,
The data read by this index is returned to the data request source as valid data when a cache hit is detected in the address array section.

Here, for example, if the data request width is 8 bytes,
The block address is 3 bits.

When the store is executed, the address array section is indexed in the same manner as the above-mentioned processing, and when the cache hit is detected, the store data is written to the data array section.

In other words, the error that occurs when the cache memory is indexed by the store request is generated only by the index of the address array section.

In FIG. 1, an address array address register (AAA) (hereinafter referred to as an address register) 1 holds an index address of an address array (AA) 4, and an address array write register (AAW) (hereinafter referred to as a write register) 2 The upper part of the block address corresponding to the key address part of the address array 4 which becomes the write data of the address array (AA) 4 is held.

The address array write enable register (WE) (hereinafter referred to as the write enable register) 3 stores the key address part of the memory read request held in the write register 2 when a cache miss hit occurs in the cache memory index by the memory read request. When writing to a corresponding address position of the address array 4, a logic "1" for instructing writing, that is, a cache registration instruction is set.

The address array 4 manages the registered block address of the cache memory.

The comparator 5 compares the key address portion of the block address set in the write register 2 with the key address portion read from the address array 4, and outputs the comparison result to the AND gate 21.

The error detection circuit 6 checks the parity of the key address portion read from the address array 4, and the detection result is used as a logic inversion gate 16, a NAND gate 17, and an AND gate 18.
And output respectively.

The flip-flop (hereinafter referred to as F / F) 7 holds a store request representative indicating a store request.

An error store address register (hereinafter referred to as an address register) 8 holds the index address set in the address register 1 when an error is detected by the error detection circuit 6 in the index of the address array 4 by the store request.

A store error flag write register (hereinafter referred to as a store error flag) 9 is set to a logic "1" when an error is detected by the error detection circuit 6 in the index of the address array 4 by the store request, and the address array 4 is newly added. A logical "0" is set when the key address part of the block data is registered.

When the logical "1" is set in the store error flag 9, it indicates that the index address of the store request in which the error is detected is set in the address register 8.

Error flag register file Write enable register (WE) (hereafter referred to as write enable register) 10
When writing the contents of the store error flag 9 to the error flag register file (hereinafter referred to as a file) 12, a logic "1" is set.

The comparator 11 compares the index address set in the address register 1 with the index address set in the address register 8 and outputs the comparison result to the NAND gate 19.

The file 12 is composed of a register file that can be read and written at the same time, and corresponds to each word of the address array 4 with flag information indicating whether or not an error has occurred in the index by the store request of the address array 4 of that entry. To store.

The logic inversion gate 13 inverts the cache registration instruction to the write enable register 3 and outputs the inversion value to the AND gate 14 and the NAND gate 15.

The AND gate 14 takes the logical product of the inverted value of the logical inversion gate 13 and the operation result of the AND gate 18, and outputs the operation result to the store error flag 9.

The NAND gate 15 performs a NAND operation of the inverted value of the logic inversion gate 13 and the operation result of the NAND gate 17, and outputs the operation result to the write enable register 10.

The logic inversion gate 16 inverts the detection result of the error detection circuit 6 and outputs the inverted value to the AND gate 21.

The NAND gate 17 detects the detection result of the error detection circuit 6 and F / F7.
And a NAND operation with the store request representative of (1) and output the operation result to the NAND gate 15.

AND gate 18 detects the result of error detection circuit 6 and F / F7.
And the result of the operation is output to the AND gate 14.

The NAND gate 19 calculates the NAND of the flag information of the store error flag 9 and the comparison result of the comparator 11 and outputs the operation result to the AND gate 21.

The logic inversion gate 20 inverts the flag information of the file 12 and outputs the inverted value to the AND gate 21.

The AND gate 21 takes the logical product of the comparison result of the comparator 5, the inverted values of the logic inversion gates 16 and 20, and the operation result of the NAND gate 19, and outputs the operation result as the index result of the address array 4.

The operation of one embodiment of the present invention will be described with reference to FIG.

When the store request is issued, the index address is set in the address register 1, the key address part is set in the write register 2, and the store request representative (logical "1") is set in the F / F7.

After that, the key address part held in the address array 4 is read according to the index address set in the address register 1, and the key address part is compared with the key address part set in the write register 2 by the comparator 5. To be done.

The comparator 5 outputs a logic "1" to the AND gate 21 when it detects a match and a logic "0" when it detects a mismatch.

At the same time, the key address portion read from the address array 4 is checked for correctness of parity by the error detection circuit 6.

When the error detection circuit 6 detects a parity error in the key address portion read from the address array 4, it outputs a logical "1".
If a parity error is not detected, a logic "0" is output to the logic inversion gate 16, the NAND gate 17, and the AND gate 18, respectively.

The error detection circuit 6 detects a parity error in the key address portion read from the address array 4 and outputs a logic "1".
When this is output, this detection signal is inverted by the logic inversion gate 16 and the signal inverted to the logic “0” is supplied to the AND gate 21, so that the logic “0”, that is, the cache miss hit, is obtained as the index result. Is output.

In other words, even if the comparator 5 detects a match, if the error detection circuit 6 detects a parity error, the comparison result of the comparator 5 is forcibly cache-missed by the AND gate 21.

Further, when a parity error is detected by the error detection circuit 6 in the index of the address array 4 by the store request and a logic "1" is output, this detection result (logic "1") and the store request representative of the F / F7 ( ANDed with the logical "1") by AND gate 18, and as a result logical "1"
, That is, flag information indicating that an error has been detected in the index of the address array 4 by the store request is output to the AND gate 14.

Normally, when the cache memory is indexed, the cache registration instruction is always a logical "0".
The output of 13 always becomes logic "1", and the AND gate 14 stores the operation result of the AND gate 18 as it is in the error flag 9
Therefore, the flag information indicating that an error is detected in the index of the address array 4 by the store request is set in the store error flag 9 via the AND gate 14.

On the other hand, the detection result of the error detection circuit 6 (logic “1”) and F /
The NAND gate with the store request representative of F7 (logic "1") is taken by the NAND gate 17, and as a result, the logic "0" is output to the NAND gate 15.

In the NAND gate 15, the output of the logic inverting gate 13 (logic “1”) and the operation result of the NAND gate 17 (logic “0”) are NANDed, and as a result, the logic “1” is set in the write enable register 10. It That is, the write enable register 10 is set with the content instructing the writing of the flag information of the store error flag 9 into the file 12.

Simultaneously with the above processing, the index address of the store request used for the index of the address array 4 is output from the address register 1 to the address register 8 and set.

In the file 12, the write enable register 10 is set with the content for instructing the writing of the flag information of the store error flag 9 to the file 12, so that the address position indicated by the index address of the address register 8, that is, the index of the address array 4 is set. The flag information (logical “1”) of the store error flag 9 indicating that an error is detected in the index of the address array 4 by the store request is written in the address position corresponding to the index address of the store request in which the error is detected in Get caught.

In this way, the file 12 holds flag information corresponding to the index address of the address array 4 indicating whether or not an error has been detected in the index of the address array 4 by the store request. Become.

Therefore, when indexing the address array 4 and indexing the file 12 at the same time with the index address, whether an error was previously detected in the index of the address array 4 due to a store request of the same index address as the index address. Can be inspected.

If this inspection shows that an error has been detected, the flag information (logic "1") read from the file 12 is inverted by the logic inversion gate 20, and the signal inverted to logic "0" is output. Since it is supplied to the AND gate 21, a logical "0", that is, a cache mishit is output as the index result.

Therefore, if an error was previously detected in the index of the address array 4 due to a store request of the same index address as that index address, even if a match is detected in the comparator 5, the comparison result of the comparator 5 is AND gated. Since it is possible to forcibly cause a cache miss hit at 21, it is possible to prevent data that does not reflect the store data from being read from the data array section and causing a malfunction due to the data.

When a memory read request is issued consecutively to a store request in which an error is detected, the index when the error is detected in the index of the address array 4 by the immediately preceding store request when the address array 4 is indexed by this memory read request. The address and flag information remains set in the address register 8 and the store error flag 9.

Therefore, when the address array 4 is indexed by the memory read request, the file 12 must be indexed and the contents of the address register 8 and the store error flag 9 must be searched at the same time.

Therefore, when the index address of this memory read request is set in the address register 1, the address array 4 is indexed by this index address, and at the same time, this index address is input to the comparator 11 and stored in the file 12. It is supplied as a read address.

In the comparator 11, this index address and the address register 8
Is compared with the index address of the immediately preceding store request held in, and if a match is detected, a logical “1” is output to the NAND gate 19.

In the NAND gate 19, the NAND information of the flag information (logic “1”) of the store error flag 9 and the comparison result (logic “1”) of the comparator 11 is obtained, and the logic “0” is obtained as the operation result of the AND operation. , A logical "0", that is, a cache mishit is output as the index result.

Therefore, even if the memory read request is issued following the store request in which the error is detected, if the index address of the memory read request is the same as the index address of the immediately preceding store request, the comparator 5 determines that a match is found. Even if it is detected, the comparison result of the comparator 5 can be forced to be a cache mishit by the AND gate 21, so that the data in which the store data is not reflected is read from the data array section and the malfunction is caused by the data. It can be prevented from occurring.

On the other hand, when the flag information indicating that an error is detected in the index of the address array 4 by the store request of the same index address as the index address of the memory read request is read from the file 12 by the index address of the memory read request, The flag information (logic "1") read from 12 is inverted by the logic inversion gate 20, and the signal inverted to logic "0" is supplied to the AND gate 21, so that the logic "0" is obtained as the index result. That is, a cache mishit is output.

Therefore, if an error was previously detected in the index of the address array 4 due to a store request of the same index address as that index address, even if a match is detected in the comparator 5, the comparison result of the comparator 5 is AND gated. Since it is possible to forcibly cause a cache miss hit at 21, it is possible to prevent data that does not reflect the store data from being read from the data array section and causing a malfunction due to the data.

Further, it is assumed that an error is detected in the index of the address array 4 due to the store request at a certain timing, the index address at that time is set in the address register 8, and the flag information indicating the occurrence of the error is set in the store error flag 9. .

Then, the flag information is written at the address position of the file 12 indicating the address register 8 at the next timing, but when the writing of the flag information to the file 12 and the index of the file 12 due to the subsequent request overlap,
If the write address and the read address to the file 12 are different, the writing of the flag information to the file 12 and the index of the file 12 are simultaneously performed in parallel, and the file 12
If the write address and the read address to the file 12 match, the flag information is written to the file 12 with priority.

However, when the logical "0" is set in the write enable register 10, the flag information is not written to the file 12 and the file 12 is indexed.

That is, when the write address and the read address to the file 12 match and the flag information is written to the file 12, only the search of the address register 8 and the store error flag 9 is performed as described above. Then, it is detected that an error has occurred in the index of the address array 4 due to the store request having the same index address as that index address previously.

Therefore, once an error is detected in the index of the address array 4 due to a store request, all subsequent indexes of the cache memory with the same address result in a cache miss, and data that does not reflect the store data becomes data array section. It is possible to prevent an erroneous operation due to the data being read from the memory.

Here, if a memory read request is executed at the same index address as the index address where an error was previously detected in the index of the address array 4 by the store request, this memory read request results in a cache mishit as described above. .

At this time, the key address portion held in the write register 2 is registered in the storage position of the address array 4 corresponding to the index address held in the address register 1.

Therefore, if the error detected by the index of the address array 4 due to the previous store request is an intermittent failure, the block data from the main memory device to the cache memory by the memory read request resulting in this cache mishit is transferred to the cache memory. By writing, the failure of the address array 4 is recovered.

When the control circuit (not shown) of the higher-level device is notified of the occurrence of the cache mishit by this memory read request via the AND gate 21, the cache enable instruction causes the write enable register 3 to be logically "1". Is set, and the write operation of the address array 4 is executed.

On the other hand, at the same time when the cache mishit is notified to the control circuit, the index address held in the address register 1 is set in the address register 8.

The cache registration instruction from the control circuit is a logic inversion gate
The logic "0" is inverted by 13 and this logic "0" is set to the store error flag 9 through the AND gate 14 and the write enable register 10 through the NAND gate 15.
Is set to logic "1".

As a result, a logical "0" is written in the file 12 at the storage position corresponding to the index address of the memory read request that resulted in the cache miss, and a new error is detected in the index of the address array 4 by the index address thereafter. Until this is done, the index result of the address array 4 is not forced to be a cache miss by the index of the file 12.

Therefore, when the intermittent failure of the address array is recovered by the write operation of the address array 4, it becomes possible to use the cache memory for the index by the index address thereafter without any trouble.

In this way, when an error is detected in the index of the address array 4 due to the store request, use of the cache memory is permitted in the entry unit for managing the block data of the cache memory, that is, in the index address unit registered in the address array 4. The index of the address array 4 by the store request is controlled by canceling the prohibition of the index address of the address array 4 in which the error is detected and rewriting the index address of the address array 4 when the error is detected. Even if an error is detected in, the use of the entire cache memory or the entire level will not be prohibited, so that the system performance can be minimized and the system can be continuously operated.

Further, since the cache memory is restored without being initialized, all the data in the cache memory accumulated up to that point is not lost, and it is possible to prevent a significant decrease in system performance.

As described above, according to the present invention, when an error is detected in a cache memory index due to a store request, permission and prohibition of use of the cache memory are controlled for each entry that manages block data of the cache memory. In addition, when the entry of the cache memory in which the error is detected is rewritten, the use prohibition of the entry is released to minimize the system performance degradation when the error is detected. The effect is that continuous operation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Description of symbols of main part 1 ... Address array address register 2 ... Address array write register 3 ... Address array write enable register 4 ... Address array 5,11 ... Comparator 6 ... Error detection circuit 7 ... Flip floc P 8 …… Error store address register 9 …… Store error flag write register 10 …… Error flag register file write enable register 12 …… Error flag register file 13,16,20 …… Logic inversion gate 14,18,21 …… AND gate 15,17,19 …… Nand gate

Claims (1)

(57) [Claims] 1. A detecting means for detecting an error of an index to a cache memory storing a part of data of a main memory; and a detecting means for detecting the error,
First deterring means for making the result of the index for the cache memory a mishit, and address holding for holding the index address of the cache memory when an error of the index for the cache memory due to a store request is detected by the detecting means. Means, error information storage means for storing error information indicating whether or not an error is detected by the detection means in the index for the cache memory by the store request, corresponding to an address of the cache memory; Second deterring means for making the result of the index as a mishit according to the error information read from the error information storing means at the time of indexing, and cache memory by the store request in which the error is detected by the detecting means. Consecutive in index Serial third to the comparing means for comparing the index address and the index address held in the address holding unit of the cache memory index, and miss the results of the index when the match is detected by said comparing means
And a means for updating the contents of the error information storage means when registering the data of the main storage device in the cache memory.