JP3222218B2 - Control method of associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a control method for an associative memory device, and more particularly to a control method at the time of error in a set associative or full associative memory such as a cache memory or a TLB having a plurality of ways. About the method.

[0002]

2. Description of the Related Art In order to speed up data access of a data processing apparatus, cache memories, associative memories such as TLBs, and the like are often used. These associative memories often use a set associative method or a full associative method having a plurality of ways to improve the hit rate. In order to further improve the reliability, error detecting means for the content of the memory of the associative memory system may be provided. By the way, the memory element used for the associative memory type memory (hereinafter referred to as associative memory device) has a higher probability of occurrence of soft error as the capacity and the integration are increased year by year. Unlike a hard error, a soft error is almost always corrected by rewriting an error location. In consideration of this point, the main memory is provided with an ECC and a patrol mechanism to deal with the soft error. However, in an associative memory device requiring high-speed operation and having a high-speed and expensive memory itself, such a method cannot be adopted. Therefore, there is a demand for a control method for performing an efficient recovery with a small amount of hardware when a soft error occurs in the associative memory.

[0003]

2. Description of the Related Art Conventionally, in an associative memory device as described above,
If an error is detected in the data that is the content of the associative memory, it is assumed that an irreversible failure has occurred in the associative memory, regardless of the tag data of any way, and the system goes down or the associative memory is immediately stopped. By separating, re-execution processing was performed when possible.

[0004] As shown in FIG. 14, when no error occurs at the stage of accessing the associative storage device, hit processing (ST4) or mishit processing (S4) is performed.
T5) is performed, but if an error occurs (ST1),
The error processing (ST2) is performed without judging a hit or a mishit (ST3).

[0005]

In the above-described conventional method of controlling an associative storage device, even if an error is detected in any of the data of a plurality of ways, the error is uniformly regarded as an error and the access source determines the error. An error was notified to a certain processor, which caused the system to go down or to immediately disconnect the associative memory.
The system availability (ability to continue operation even if a failure occurs) has been degraded. For example, the error is caused by a soft error of the memory element, and the system is down even though it can be recovered by means such as rewrite, and the failure rate of the system is deteriorated.

The present invention has been made in view of the above problems, and when an error is detected in any one of a plurality of ways due to an intermittent failure such as a soft error in a memory element, the error is uniformly regarded as an error. The purpose of the present invention is to improve the availability of the system by keeping the operation as continuous as possible without impairing the reliability and minimizing the influence of errors as a whole system.

[0007]

According to the present invention, a means for solving the above-mentioned problem is a set associative method or a full associative method having a plurality of ways, and an error of data output to each way. Error-detecting means for performing error processing when an error is detected. In an associative memory device, when one way is hit and an error is detected in another way, the processing is continued without performing the error processing. That is to control.

Further, the second means of the present invention is a set associative method or a full associative method having a plurality of ways, and comprises an error detecting means for detecting an error of data output to each way. In the content addressable storage device, when an error is detected, an error is detected in one of the ways, and when an error is detected in the other way, the data in the area where the error occurred is invalidated. And overwrite
That is, control is performed so that processing is continued without performing error processing.

In the third means of the present invention, in the first or second means, when an error is simultaneously detected in the hit way, the error processing is not performed, the mishit processing is performed, and the supplemented data is processed. That is, control is performed so as to be registered in the relevant area of the error occurrence way.

Further, the fourth means of the present invention is the same as the first to third means, wherein there is no hit way and
When an error is detected in one way, a mishit process is performed without performing the error process, and control is performed so that the replenished data is registered in the area of the way in which the error has occurred.

The fifth means of the present invention is a set associative method or a full associative method having a plurality of ways, and comprises an error detecting means for detecting an error in data output to each way. In the associative storage device, which performs an error process when an error is detected, when an error is detected in the read data, a mishit process is performed, and the supplemented data is registered in the area of the way in which the error has occurred, When an error is detected in the read data in a plurality of ways,
The purpose is to perform a mishit process and register the replenished data in the area of a specific one way, and control to overwrite the data in which the area becomes invalid in another error way. .

The sixth means of the present invention is a set associative method or a full associative method having a plurality of ways, and comprises an error detecting means for detecting an error in data output to each way. ,
When an error is detected in the associative storage device, when an error is detected in the read data, a mishit process is performed to register the replenished data in the area of the erroneous way, and Is to be controlled so as to overwrite data that invalidates the area, regardless of the hit / miss hit.

Further, the seventh means of the present invention is a set associative method or a full associative method having a plurality of ways, and comprises an error detecting means for detecting an error of data output to each way. When an error is detected in the read data in the associative storage device, a mis-hit process is performed, but the supplemented data is not registered in the associative memory, and all the ways in the associative memory are performed. Is to overwrite the data in which the area becomes invalid.

[0014]

The associative memory according to the present invention will be described below using the operation of the control method. Hereinafter, the operation of each means will be described. In each of the means, a set associative method or a full associative method having a plurality of ways, comprising error detecting means for detecting an error of data output to each way, performing error processing when an error is detected, Operates on storage devices.

First Means When one way hits and the other way has an error, the processing is continued ignoring the error, so that the probability of a system down can be reduced and the availability of the system can be improved. Can be done.

Second Means When one way hits and the other way has an error, data is written in such a way that the area of the way in which the error occurred becomes invalid, and the error is ignored and the processing is performed. Is continued, if the error is caused by a soft error in the memory element, the data can be corrected to normal invalid data, and no error occurs in subsequent accesses.

Third Means In addition to the first and second means, if the hit way is also an error at the same time, a mishit process is performed instead of performing an error operation, and the replenished data is stored in the relevant area of the error generating way. Therefore, if the error is caused by a soft error of the memory element, the original error data can be erased, and no error occurs in subsequent accesses.

Fourth Means In addition to the first to third means, if there is no hit way and an error is detected in one way, the operation is replaced with a mishit operation and the replenished data is detected as an error. If the error is caused by a soft error in the memory element, the original error data can be erased, and no error occurs in subsequent accesses.

Fifth Means When the read data has an error, a mishit operation is performed to register the supplemented data in the way in which the error has occurred, and to register the read data in a plurality of ways. If an error occurs, a mishit operation is performed to register the replenished data in one specific way, and the other errored way overwrites the invalid data in the relevant area. Is caused by a soft error in the memory element, the data can be converted into normal valid data and normal invalid data, and no error occurs in subsequent accesses.

Sixth Means When the read data has an error, a mishit operation is performed to register the supplemented data in the erroneous way, and the other ways are irrespective of the hit / mishit. Since the data which becomes invalid is overwritten on the area, it is possible to eliminate the possibility that the refilled data and the data of the other way become the same,
The data can be converted into normal valid data and normal invalid data, and no error occurs in subsequent accesses.

Seventh Means When an error occurs in the read data, a mishit operation is performed, but the supplemented data is not registered in the associative memory, and data which invalidates all the ways of the associative memory is deleted. Since the area is overwritten, it is possible to eliminate the possibility that the refilled data becomes the same as the data of the other way, and it is possible to correct all the data to normal invalid data. Does not occur,
A normal mishit operation is performed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for controlling an associative storage device according to the present invention will be described below. FIG. 1 shows a data processing device using an associative memory device as a premise of the present invention. In FIG. 1, reference numeral 1 denotes a processor for transmitting an address and accessing data corresponding to the address;
, An address bus for transmitting an address, 3 a portion for transferring the address of the associative memory itself in the address bus, 4 a portion to be compared with the content of the associative memory in the address bus, and 5 a way for storing a tag of the associative memory. 0, a tag memory of way 1 for storing a tag of associative memory, 7 a comparator for comparing the tag read from the memory of way 0 with the contents of the address, and 8 a memory of way 1 The comparator 9 compares the tag read from the address bus 4 with the contents of the address bus 4. The transmission line 9 sends out a match signal indicating that the tag 7 matches as a result of the comparison by the comparator 7. As a result, a transmission line for transmitting a coincidence signal indicating the coincidence is shown.

In FIG. 1, reference numeral 11 denotes a memory for way 0 for storing data when the way 0 is pointed by the associative memory, and reference numeral 12 denotes data when the way 1 is pointed by the associative memory. A memory for way 1 for storage, 13 is a tri-state driver for driving read data from the memory for way 1 when the way 0 is pointed by the associative memory, and 14 is a way point for way 1 by the associative memory. The tri-state driver 15 for driving the read data from the way 1 memory in the case indicated is provided with an error signal (ERR) when the tag data output from the way 0 tag memory has an error.
Error detecting means 16 for outputting 0) and error detecting means 16 for outputting an error signal (ERR1) when the tag data output from the tag memory of way 1 has an error.

In FIG. 1, reference numeral 17 denotes a processor 1
Is a data bus for transmitting and receiving data, and 18 is a way 0
Tag data buses 0 and 19 for outputting data to the tag memory of No. 1 are tag data buses 1 for outputting data to the tag memory of Way 1. In this embodiment, the processor 1 executes each embodiment by executing a program stored in a memory device (not shown).

FIGS. 2 to 7 show first to sixth embodiments according to the present invention.
6 is a flowchart showing the operation of the embodiment. FIGS. 8 to 13 show the operation when the first to sixth embodiments are associative memory devices having a two-way configuration (way 0, way 1), particularly cache devices.

Here, in FIGS. 8 to 13, HIT0: a hit signal indicating that way 0 has been hit HIT1: a hit signal indicating that way 1 has been hit ERR0: read from way 0 Error signal ERR1 indicating that an error has been detected in the issued tag data: ERR1: an error signal indicating that an error has been detected in the tag data read from way 1. In this embodiment, HIT0, HIT1
If both are “1”, an error is determined as an impossible state.

The embodiment described below corresponds to each figure.

Embodiment 1 FIGS. 2 and 8 show a first embodiment of a method for controlling an associative memory device according to the present invention. This embodiment corresponds to the above-described means 1 and means 4 of the present invention.

In the embodiment corresponding to the means 1, first,
It is determined whether any way has been hit (S10
1). And when you hit any of the ways,
It is determined whether an error has occurred in the hit way (S
102). If an error has occurred in this way, normal error processing is performed (S103). If no error has occurred, hit processing (S104) is performed. If no hit is found in any of the ways, it is determined whether an error has occurred in each way (S105). If no error has occurred, normal mishit processing (S107) is performed. If it has occurred, error processing (S1
03).

When corresponding to the fourth means, after the above-mentioned error occurrence determination (S105), it is determined whether there is only one way in which an error has occurred, and if not, error processing (S103) is performed. If not, a mishit process is performed. It should be noted that the processing enclosed by a broken line in FIG. 6 shows the processing performed when the latter example is performed, and the error processing is performed as it is in the embodiment corresponding to the first means. FIG. 8 is a table showing the operation when the control method according to this embodiment is applied to a two-way associative storage device.

Embodiment 2 FIGS. 3 and 9 show a second embodiment of a control method for a content addressable memory device according to the present invention. This embodiment corresponds to the means 2 and 4 of the present invention described above.

In the embodiment corresponding to the means 2, first,
It is determined whether any way has been hit (S20).
1). And when you hit any of the ways,
It is determined whether an error has occurred in the hit way (S
202). If an error has occurred in this way, normal error processing (S203) is performed. If no error has occurred in a way other than the hit way, hit processing (S20) is performed.
4, S206). If an error has occurred in a way other than the hit way, data for invalidating the area of the way in which the error has occurred is written (S20).
5) Then, hit processing (S206) is performed. If no hit is found in any of the ways, it is determined whether an error has occurred in each way (S207). If no error has occurred, normal mishit processing (S20) is performed.
9) is performed, and if an error has occurred, error processing (S203) is performed.

When corresponding to the fourth means, after the above-described error occurrence determination (S205), it is determined whether there is only one way in which an error has occurred. If not, error processing (S203) is performed. If not, a mishit process (S209) is performed. It should be noted that the processing enclosed by a broken line in the figure indicates the processing performed when the latter example is performed, and the error processing is performed as it is in the embodiment corresponding to the second means. FIG. 9 is a table showing operations when the control method according to this embodiment is applied to a two-way associative storage device.

Embodiment 3 FIGS. 4 and 10 show a third embodiment of the method for controlling an associative memory device according to the present invention. This embodiment corresponds to the means 3 and 4 of the present invention described above.

In the embodiment corresponding to the means 3, first,
It is determined whether any of the ways has been hit (S30).
1). And when you hit any of the ways,
It is determined whether an error has occurred in the hit way (S
302). If an error has occurred in this way, a mishit process is performed, and the data read from the main storage device is written in the relevant area of the error occurrence way (S3).
03). If no error has occurred, hit processing (S3
04). If no hit is found in any of the ways, it is determined whether or not an error has occurred in each way (S307). If no error has occurred, normal mishit processing (S309) is performed. If it has occurred, error processing (S303) is performed.

If no error has occurred in the hit way, hit processing (S305) is performed. When the fourth means is used, the method is surrounded by a broken line after the above-mentioned error occurrence determination (S305). Processing, that is, whether an error has occurred in a way other than the hit way is determined (S
304), if an error has occurred, write data for invalidating the area of the way in which the error has occurred (S306); if no error has occurred,
Hit processing (S305) is performed. If none of the ways is hit, it is determined whether an error has occurred (S
307) If an error has occurred, step 303
Is executed, and if no error has occurred, a mishit process is performed. Here, when corresponding to the fourth means, it is determined whether there is only one way, and if it is not one, step 303 is executed; otherwise, a mishit process (S309) is performed. The control method according to this embodiment
FIG. 10 shows the operation when applied to a two-way associative storage device.

Embodiment 4 FIGS. 5 and 11 show a fourth embodiment of the method for controlling an associative memory device according to the present invention. This embodiment corresponds to the means 5 of the present invention described above.

In this embodiment, first, it is determined whether an error has occurred in any of the ways (S401).
If no error has occurred, it is determined which way has been hit (S402). When hitting any of the ways, the hit processing (S40)
3) is performed, and if no hit occurs, the mishit processing (S
404). If an error has occurred in any of the ways, it is determined whether an error has occurred in a plurality of ways. Is replenished with data from the main storage device (S40).
5, S406).

When an error occurs in a plurality of ways, a mishit process is performed, and data from the main storage device is replenished to a corresponding location of one of the ways in which the error occurred, while the other way is executed. The data which invalidates the corresponding part is written (S407). FIG. 11 is a table showing the operation when the control method according to this embodiment is applied to a two-way associative storage device.

Fifth Embodiment FIGS. 6 and 12 show a fifth embodiment of the method for controlling an associative memory device according to the present invention.

In this embodiment, first, it is determined whether an error has occurred in any of the ways (S501).
If no error has occurred, it is determined which way has been hit (S502). If any of the ways is hit, hit processing (503)
Is performed, and if no hit occurs, a mishit process (S50)
Perform 4). If an error occurs in any of the ways, the data from the main storage device is replenished to the corresponding location of the error-occurring way without performing the mishit processing, and all errors in which other errors have occurred are performed. Data for invalidating the way is written (S505). FIG. 12 is a table showing the operation when the control method according to this embodiment is applied to a two-way associative storage device.

Embodiment 6 FIGS. 7 and 13 show a sixth embodiment of the method for controlling an associative storage device according to the present invention. This embodiment corresponds to the means 7 of the present invention described above.

In this embodiment, first, it is determined whether an error has occurred in any of the ways (S601).
If no error has occurred, it is determined which way has been hit (S602). If any of the ways is hit, hit processing (603)
Is performed, and if no hit occurs, a mishit process (S60)
Perform 4). If an error occurs in any of the ways, perform a mishit process and invalidate the relevant locations of all ways without replenishing data from the main memory to the relevant locations of the error-occurring way. Is written (S607). FIG. 13 is a table showing the operation when the control method according to this embodiment is applied to a two-way associative storage device. In this embodiment, the operation has been described on the assumption that the cache device is used. However, the present invention can be applied to other associative memories such as TLB in the same manner.

[0044]

According to the first means, even if one of the ways has an error, if the other is a hit, an error is ignored and a hit operation is performed without performing an error. It has the effect of improving the availability of the system.

In the second means, even if one of the ways has an error, if the other is a hit, the hit operation is performed without ignoring the error, and the way in which the error occurred is invalidated. By writing new data to the entire tag, if the error is caused by a soft error in the memory element, it can be converted to normal invalid data, and the error will not occur in subsequent accesses. It is possible to reduce the number, which has the effect of greatly improving the availability of the system.

In the third means, in addition to the advantages of the first means and the second means, a mishit operation is performed without causing the hit way to be an error, and the replenished data is registered in the error generating way. If the error is due to a soft error in the memory element, the original error data can be erased, and no error will occur in subsequent accesses.
It is possible to reduce the probability of the system going down, which has the effect of greatly improving the availability of the system.

According to the fourth means, in addition to the advantages of the first means, the second means, and the third means, even when an error occurs, a mishit operation is performed without causing an error, and the replenished data is stored. If the error is due to a soft error in the memory element, the original error data can be erased and the error will not occur in subsequent accesses. This has the effect of greatly improving the availability of the system.

According to the fifth means, even when an error occurs in a plurality of ways, if the error is caused by a soft error in the memory element, the tag can be converted into normal valid data and normal invalid data. Since no error occurs in the first access, the probability of the system going down can be reduced, and the availability of the system can be greatly improved.

According to the sixth means, even when an error occurs, a mishit operation is performed without causing an error, and the replenished data is registered in the error occurrence way, and the other ways are invalidated. It is possible to eliminate the possibility that the refilled data becomes the same as the data of the other ways, which contributes to the improvement of the reliability, and can change the tag into normal valid data and normal invalid data,
Since errors do not occur in subsequent accesses, the probability of system down can be reduced, and the availability of the system can be greatly improved.

According to the seventh means, even when an error occurs, a mishit operation is performed without causing an error, the refilled data is not directly registered in the associative memory, but is directly sent to the processor which has accessed the data. Invalidate the way, it is possible to eliminate the possibility that the refilled data will be the same as the data in other ways, contributing to the improvement of reliability and to correct all tags to normal invalid data. , And subsequent access will not generate an error,
Since the normal mishit operation is performed, the probability of the system going down can be reduced, and the availability of the system can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an associative memory device to which the present invention is applied.

FIG. 2 is a block diagram showing the operation of the first embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 3 is a block diagram showing an operation of a second embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 4 is a block diagram showing the operation of a third embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 5 is a block diagram showing the operation of a fourth embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 6 is a block diagram showing an operation of a fifth embodiment of the control method for the content addressable memory device according to the present invention.

FIG. 7 is a block diagram showing the operation of a sixth embodiment of the control method for the content addressable memory device according to the present invention.

FIG. 8 is a table showing the operation of the first embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 9 is a table showing the operation of the second embodiment of the method for controlling the content addressable memory device according to the present invention.

FIG. 10 is a third control method of the content addressable memory device according to the present invention.
6 is a table showing the operation of the example of FIG.

FIG. 11 is a fourth method of controlling the content addressable memory device according to the present invention.
6 is a table showing the operation of the example of FIG.

FIG. 12 is a fifth embodiment of the content addressable memory control method according to the present invention;
6 is a table showing the operation of the example of FIG.

FIG. 13 is a sixth method of controlling the content addressable memory device according to the present invention;
6 is a table showing the operation of the example of FIG.

FIG. 14 is a flowchart showing an operation of a conventional method for controlling an associative storage device.

Continuing from the front page (72) Inventor Yasutoshi Sakurai 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Koichi Odahara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Invention Takumi Nonaka 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kenji Hoshi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Eiji Kanaya Nakahara, Kawasaki City, Kanagawa Prefecture 1015, Kamiodanaka-ku, Fujitsu Limited (56) References JP-A-61-7959 (JP, A) JP-A-4-127341 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB G06F 12/16 G06F 12/08

Claims (3)

(57) [Claims] 1. A set associative method or a full associative method having a plurality of ways, comprising error detecting means for detecting an error in data output to each of the ways, and performing error processing upon error detection. in content addressable memory, a hit in one of the ways, and the error detecting means
When an error is detected in the other way by
The contents of the way where the error occurred in the area where the error occurred
By overwriting data that becomes invalid, the error
Normalize the area where the
A method for controlling an associative storage device, wherein hit processing is performed using a way. 2. The control of the associative storage device according to claim 1.
In the method, when simultaneously detecting an error in the hit way,
Performs a mis-hit process and replaces the refilled data with an error.
Register in the area where the error occurred in the area where the error occurred
A region in which the error has occurred, thereby normalizing the region where the error has occurred . 3. The associative memory according to claim 1 or 2.
In the device control method, if there is no way
If an error is detected in one of the ways,
Performs hit processing and replenishes data with an error
Registering in the area of the way where the error occurred
Wherein the area in which the error has occurred is normalized .