JP5056487B2 - Debugging support mechanism and processor system - Google Patents

Description

  The present invention relates to a debugging support mechanism for supporting a program debugging operation for a processor system using a processor having a cache memory.

  Recently, processor systems are strongly required to achieve both high performance and low power consumption due to market demands. For this reason, a processor system employing a multiprocessor configuration, a processor system equipped with an accelerator dedicated to specific processing in addition to a general-purpose processor, and the like are widely adopted.

  In many processor systems, there is a problem that the processing performance deteriorates due to the low access speed of a memory device provided outside the processor. For this reason, a technique is often used in which a cache memory that can be accessed at high speed is provided inside the processor, and a copy of data of a memory device provided outside the processor is stored in the cache memory.

  However, in a processor system in which a plurality of master devices including a processor having a cache memory commonly use main memory, there is a problem that data consistency cannot be ensured between the cache memory of the processor and the main memory (cache consistency problem). Arise. For example, when the data at the address A is rewritten in the cache memory of the processor, if the data at the address A is read from the main memory by another master device, there is a problem that the wrong data is used in the master device .

  As a technique for solving the cache coherency problem, a technique (generally referred to as a snoop method) for controlling the cache memory based on information obtained by monitoring access to the cache memory or access to the main memory is well known. . However, this method has a drawback in that power consumption increases because monitoring processing is performed each time a memory access occurs. In addition, since the processor is in a standby state until cache coherency is ensured, there is also a disadvantage that processing performance is lowered. Furthermore, there is a drawback that the amount of circuit objects increases with the realization of the monitoring device.

These drawbacks are not a problem in processor systems for applications where personal power consumption is not strongly required (personal computers, workstations, etc.), but for applications where there is a strong demand for low power consumption (mobile phones, digital cameras, etc.). This is a serious problem in processor systems. For this reason, a processor system for applications where there is a strong demand for lower power consumption generally does not include a cache coherency maintenance mechanism. The cache memory, cache coherency, and snoop method are described in Non-Patent Document 1 and the like, and thus detailed description thereof is omitted here. Further, techniques related to cache coherency are disclosed in Patent Documents 1 and 2 and the like.
JP 2003-345653 A JP-A-6-150032 David A. Patterson, John L. Hennessy, "Computer Configuration and Design 3rd Edition", published by Nikkei BP

  In processor systems that do not have a cache coherency maintenance mechanism, there are no problems such as an increase in power consumption, a decrease in processing performance, or an increase in the amount of circuitry, but a bug in the program due to cache coherency not being maintained. When this occurs, there is a problem that debugging is not easy and the development man-hour of the program increases.

  An object of the present invention is to facilitate program debugging for a processor system that does not include a cache coherency maintenance mechanism.

  A debugging support mechanism includes a first master device having a central processing unit and a cache memory, a second master device, and a main memory used in common between the first master device and the second master device. Are provided in the first master device and include a mismatch detection unit and a stop request issuing unit. The mismatch detection unit detects a data mismatch in the cache memory when the memory access occurs. The stop request issuing unit issues a stop request to the central processing unit when the data mismatch is detected by the mismatch detection unit.

  For example, the debug support mechanism further includes an address information storage unit. The address information storage unit stores address information for memory access when data mismatch is detected by the mismatch detection unit. For example, the debugging support mechanism further includes an access type information storage unit. The access type information storage unit stores access type information for memory access when data mismatch is detected by the mismatch detection unit. For example, the access type information includes information indicating an access source and information indicating read access / write access. For example, the debugging support mechanism further includes a mismatch detection control unit. The mismatch detection control unit controls operation / non-operation of the mismatch detection unit.

  It is possible to provide the program developer with the internal state information (program counter information, etc.) of the central processing unit at the time when the data mismatch of the cache memory occurs, the memory access address information and the access type information. For this reason, debugging can be efficiently performed when a bug in the program due to the cache coherency problem occurs. As a result, the number of program development steps can be greatly reduced.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows a processor system in the first embodiment. The processor system 10 of the first embodiment includes a processor (first master device) 20, an accelerator (second master device) 30, an interconnect 40, and a main memory 50. The processor 20 and the accelerator 30 can perform read / write access to the main memory 50 via the interconnect 40.

  The processor 20 includes a CPU (Central Processing Unit) 21, a cache memory 22, and a debugging support mechanism 23. The CPU 21 performs arithmetic processing, control processing, and the like by executing programs. The cache memory 22 is a memory that can be accessed at a higher speed than the main memory 50, and is provided for storing a copy of data in the main memory 50. The debug support mechanism 23 is a mechanism for supporting the debugging work of the program, and includes a debug start register 24, a mismatch detection unit 25, and a break request issue unit 26.

  The debug activation register 24 is a register that can be read / written by the CPU 21 and is provided to control the validity / invalidity of the debug support mechanism 23. For example, the debug activation register 24 is set to “1” when the debug support mechanism 23 is enabled, and is set to “0” when the debug support mechanism 23 is disabled.

  The mismatch detection unit 25 receives data mismatch (data in the cache memory 22) triggered by the occurrence of access to the cache memory 22 of the CPU 21, access to the main memory 50 of the cache memory 22, and access to the main memory 50 of the accelerator 30. And the data in the main memory 50 are detected. The mismatch detection unit 25 activates the mismatch detection signal DET supplied to the break request issuing unit 26 when detecting a data mismatch in the cache memory 22.

  The break request issuing unit 26 activates the mismatch detection signal DET supplied from the mismatch detection unit 25 when the debug activation register 24 is set to “1” (when the debug support mechanism 23 is in a valid state). In response, the break request signal BRK supplied to the CPU 21 is activated. When the break request signal BRK from the debug support mechanism 23 (break request issuing unit 26) to the CPU 21 is activated, the execution of the program by the CPU 21 is stopped.

  As described above, the debugging support mechanism 23 implements a debugging function for issuing a break request to the CPU 21 when a data mismatch in the cache memory 22 is detected. Although not shown, the debug support mechanism 23 also implements a debugging function that issues a break request to the CPU 21 when it is detected that access to a predetermined address has been performed a predetermined number of times. Yes. This type of debugging function is disclosed in, for example, Japanese Patent Laid-Open No. 56-58199.

  FIG. 2 shows the flow of program debugging in the first embodiment. When the program developer recognizes that a bug in the program due to the cache coherency problem has occurred during the development of the program executed by the processor 20 (CPU 21) (step S11), the debug start register 24 of the debug support mechanism 23. Is set to "1" (step S12). As a result, the debug support mechanism 23 is enabled (step S31). Thereafter, the program developer starts the program under development (step S13). Thereby, execution of the program by CPU21 is started (step S21). During the execution of the program by the CPU 21, the mismatch detection unit 25 of the debug support mechanism 23 monitors whether or not a data mismatch in the cache memory 22 has occurred. The mismatch detection unit 25 of the debug support mechanism 23 activates the mismatch detection signal DET when detecting a data mismatch in the cache memory 22 (step S32). Along with this, the break request issuing unit 26 of the debug support mechanism 23 activates the break request signal BRK (step S33). Thereby, the execution of the program by the CPU 21 is stopped (step S22). Then, the program developer acquires the internal state information (program counter information, etc.) of the CPU 21 and investigates the cause of the bug (step S14).

  In the first embodiment as described above, the internal state information (program counter information, etc.) of the CPU 21 at the time when the cache memory consistency problem occurs can be provided to the program developer. This makes it possible to efficiently debug program bugs resulting from cache consistency problems. As a result, the program development period can be shortened.

  FIG. 3 shows a processor system in the second embodiment. In the description of the second embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and detailed description thereof is omitted.

  The processor system 10a of the second embodiment is obtained by replacing the processor 20 with the processor 20a in the processor system 10 of FIG. 1 (first embodiment). The processor 20a is obtained by replacing the debug support mechanism 23 with the debug support mechanism 23a in the processor 20 of FIG.

  The debug support mechanism 23a is obtained by replacing the mismatch detection unit 25 with the mismatch detection unit 25a and adding an address register 27 in the debug support mechanism 23 of FIG. The mismatch detection unit 25 a operates in the same manner as the mismatch detection unit 25 of FIG. 1, and stores memory access address information in the address register 27 when a data mismatch of the cache memory 22 is detected. The address register 27 is a register that can be read / written accessed from the CPU 21.

  In the second embodiment as described above, program debugging can be performed in the same manner as in the first embodiment (FIG. 2), and the internal state information (program counter information, etc.) of the CPU 21 when a cache coherency problem occurs. In addition, address information for memory access can be provided to the program developer. Accordingly, the efficiency of program debugging can be further improved, and the program development period can be further shortened. In particular, the address information of the memory access at the time when the cache coherency problem occurs is used in a debugging function that issues a break request to the CPU 21 when it is detected that a predetermined number of accesses to the predetermined address has been performed. As a result, the efficiency of program debugging can be greatly improved.

  FIG. 4 shows a processor system in the third embodiment. In describing the third embodiment, the same reference numerals as those used in the first and second embodiments are used for the same elements as those described in the first and second embodiments. Description is omitted.

  The processor system 10b of the third embodiment is obtained by replacing the processor 20a with the processor 20b in the processor system 10a of FIG. 3 (second embodiment). The processor 20b is obtained by replacing the debug support mechanism 23a with the debug support mechanism 23b in the processor 20a of FIG.

  The debug support mechanism 23b is obtained by replacing the mismatch detection unit 25a with the mismatch detection unit 25b and adding an access type register 28 in the debug support mechanism 23a of FIG. The mismatch detection unit 25b operates in the same manner as the mismatch detection unit 25a of FIG. 3, and also accesses the access type information (information indicating the access source and read access / write access when the data mismatch of the cache memory 22 is detected. Are stored in the access type register 28. The access type register 28 is a register that can be read / written accessed from the CPU 21.

  In the third embodiment as described above, program debugging can be performed in the same manner as in the first embodiment (FIG. 2), and internal state information (program counter information, etc.) of the CPU 21 when a cache coherency problem occurs. In addition to memory access address information, memory access access type information can be provided to the program developer. Accordingly, the efficiency of program debugging can be further improved, and the program development period can be further shortened.

  FIG. 5 shows a processor system in the fourth embodiment. In the description of the fourth embodiment, the same reference numerals as those used in the first, second, and third embodiments are used for the same elements as those described in the first, second, and third embodiments. The detailed description is omitted.

  The processor system 10c of the fourth embodiment is obtained by replacing the processor 20b with the processor 20c in the processor system 10b of FIG. 4 (third embodiment). The processor 20c is obtained by replacing the debug support mechanism 23b with the debug support mechanism 23c in the processor 20b of FIG.

  The debug support mechanism 23c is obtained by replacing the mismatch detection unit 25b with the mismatch detection unit 25c and adding a mismatch detection activation register 29 in the debug support mechanism 23b of FIG. The mismatch detection activation register 29 is a register that can be read / written accessible from the CPU 21, and is provided to control the operation / non-operation of the mismatch detection unit 25c. For example, the mismatch detection activation register 29 is set to “1” when the mismatch detection unit 25c is set to the operating state, and is set to “0” when the mismatch detection unit 25c is set to the non-operating state. The mismatch detection unit 25c operates in the same manner as the mismatch detection unit 25b in FIG. 4 when the mismatch detection activation register 29 is set to “1”.

  FIG. 6 shows the flow of program debugging in the fourth embodiment. The program debugging flow in the fourth embodiment is that the program developer sets the mismatch detection activation register 29 of the debugging support mechanism 23c to “1” with respect to the program debugging flow in the first embodiment (FIG. 2). Thus, a procedure (steps S12 ′ and S31 ′) in which the mismatch detection unit 25c of the debug support mechanism 23c is in an operating state is added.

  In the fourth embodiment as described above, since the operation / non-operation of the inconsistency detection unit 25c can be controlled via the inconsistency detection activation register 29, the inconsistency detection unit 25c can be brought into an operating state only during program debugging. . Therefore, power consumption can be suppressed during actual system operation. Although it is possible to give the debug activation register 24 the role of the mismatch detection activation register 29, the debug support mechanism 23c also realizes a debug function other than the debug function using the mismatch detection unit 25c. In addition to the debug activation register 24, a mismatch detection activation register 29 is provided.

  FIG. 7 shows a processor system in the fifth embodiment. In describing the fifth embodiment, the same elements as those described in the first, second, third, and fourth embodiments are used in the first, second, third, and fourth embodiments. The same reference numerals are used, and detailed description is omitted.

  The processor system 10d of the fifth embodiment is obtained by replacing the processor 20c with the processor 20d-1 and replacing the accelerator 30 with the processor 20d-2 in the processor system 10c of FIG. 5 (fourth embodiment). The processors 20d-1 and 20d-2 are obtained by replacing the debug support mechanism 23c with the debug support mechanism 23d in the processor 20c of FIG. The debug support mechanism 23d is obtained by replacing the mismatch detection unit 25c with the mismatch detection unit 25d in the debug support mechanism 23c of FIG.

  When the mismatch detection activation register 29 of the processor 20d-1 (20d-2) is set to “1”, the mismatch detection unit 25d of the processor 20d-1 (20d-2) ) Access to the cache memory 22 of the CPU 21, access to the main memory 50 of the cache memory 22 in the processor 20 d-1 (20 d-2), access to the cache memory 22 of the CPU 21 in the processor 20 d-2 (20 d-1), and the processor 20 d. -2 (20d-1), when the access to the main memory 50 of the cache memory 22 occurs, the data mismatch of the cache memory 22 of the processor 20d-1 (20d-2) (the processor 20d-1 (20d-2) Cat And the data in the main memory 50 and the data in the cache memory 22 of the processor 20d-1 (20d-2) and the data in the cache memory 22 of the processor 20d-2 (20d-1)). To detect. When the mismatch detection unit 25d of the processor 20d-1 (20d-2) detects a data mismatch in the cache memory 22 of the processor 20d-1 (20d-2), it issues a break request for the processor 20d-1 (20d-2). The mismatch detection signal DET supplied to the unit 26 is activated.

  In the fifth embodiment as described above, a multiprocessor configuration using the processors 20d-1 and 20d-2 is adopted. Even in such a case, the debug support mechanism 23d is added to the processors 20d-1 and 20d-2. By providing, the same effects as those of the first, second, third and fourth embodiments can be obtained.

Regarding the above first to fifth embodiments, the following additional notes are further disclosed.
(Appendix 1)
In a processor system comprising: a first master device having a central processing unit and a cache memory; a second master device; and a main memory used in common between the first master device and the second master device. A debugging support mechanism provided in the first master device,
A mismatch detection unit that detects data mismatch in the cache memory triggered by the occurrence of memory access;
A debugging support mechanism, comprising: a stop request issuing unit that issues a stop request to the central processing unit when a data mismatch is detected by the mismatch detection unit.
(Appendix 2)
In the debug support mechanism described in Appendix 1,
A debugging support mechanism, comprising: an address information storage unit for storing address information of memory access when data mismatch is detected by the mismatch detection unit.
(Appendix 3)
In the debug support mechanism described in appendix 1 or appendix 2,
A debugging support mechanism comprising: an access type information storage unit for storing access type information for memory access when data mismatch is detected by the mismatch detection unit.
(Appendix 4)
In the debug support mechanism described in Appendix 3,
The debug support mechanism, wherein the access type information includes information indicating an access source and information indicating read access / write access.
(Appendix 5)
In the debugging support mechanism according to any one of appendices 1 to 4,
A debugging support mechanism comprising: a mismatch detection control unit that controls operation / non-operation of the mismatch detection unit.
(Appendix 6)
A first master device having a central processing unit, a cache memory, and a debugging support mechanism;
A second master device;
A main memory used in common between the first master device and the second master device;
The debugging support mechanism includes:
A mismatch detection unit that detects data mismatch in the cache memory triggered by the occurrence of memory access;
A processor system, comprising: a stop request issuing unit that issues a stop request to the central processing unit when the data mismatch is detected by the mismatch detection unit.

  As mentioned above, although this invention was demonstrated in detail, above-mentioned embodiment is only an example of this invention and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

It is a figure which shows the processor system in 1st Embodiment. It is a figure which shows the flow of the program debug in 1st Embodiment. It is a figure which shows the processor system in 2nd Embodiment. It is a figure which shows the processor system in 3rd Embodiment. It is a figure which shows the processor system in 4th Embodiment. It is a figure which shows the flow of the program debug in 4th Embodiment. It is a figure which shows the processor system in 5th Embodiment.

Explanation of symbols

10, 10a, 10b, 10c, 10d ... processor system; 20, 20a, 20b, 20c, 20d-1, 20d-2 ... processor; 21 ... CPU; 22 ... cache memory; 23, 23a, 23b, 23c, 23d ... Debug support mechanism; 24, debug start register; 25, 25a, 25b, 25c, 25d, mismatch detection unit; 26, break request issue unit, 27, address register, 28, access type register, 29, mismatch detection start register; Accelerator; 40 Interconnect; 50 Main memory; BRK Break request signal; DET Mismatch detection signal

Claims (5)

In a processor system comprising: a first master device having a central processing unit and a cache memory; a second master device; and a main memory used in common between the first master device and the second master device. A debugging support mechanism provided in the first master device,
A mismatch detection unit that detects data mismatch in the cache memory triggered by the occurrence of memory access;
A debugging support mechanism, comprising: a stop request issuing unit that issues a stop request to the central processing unit when a data mismatch is detected by the mismatch detection unit. The debugging support mechanism according to claim 1,
A debugging support mechanism, comprising: an address information storage unit for storing address information of memory access when data mismatch is detected by the mismatch detection unit. In the debugging support mechanism according to claim 1 or 2,
A debugging support mechanism comprising: an access type information storage unit for storing access type information for memory access when data mismatch is detected by the mismatch detection unit. In the debugging support mechanism according to claim 3,
The debug support mechanism, wherein the access type information includes information indicating an access source and information indicating read access / write access. A first master device having a central processing unit, a cache memory, and a debugging support mechanism;
A second master device;
A main memory used in common between the first master device and the second master device;
The debugging support mechanism includes:
A mismatch detection unit that detects data mismatch in the cache memory triggered by the occurrence of memory access;
A processor system, comprising: a stop request issuing unit that issues a stop request to the central processing unit when the data mismatch is detected by the mismatch detection unit.

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