JP4114915B2 - Data processing apparatus and data processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to cache coherency in a data processing apparatus having a cache memory. For example, when an external bus master can access a local memory of a data processor, the present invention is effective when applied to maintenance of cache coherency when an external bus master accesses a local memory. About.
[0002]
[Prior art]
Japanese Patent Laid-Open No. 2000-282704 and Japanese Patent Laid-Open No. 2001-306486 are documents that describe a technique for making a local memory connected to a local bus of a data processor accessible to an external bus master connected to a bus different from the local bus. There is a publication. The former describes a data processing system in which a general-purpose bus and an SDRAM bus are provided as external buses for a CPU, and a bus master connected to the general-purpose bus can access the SDRAM via a transparent control unit provided in the CPU. The In the latter, in a system in which a bus master is connected to the CPU chip via an external system bus and an RDRAM (SDRAM) is connected via a dedicated interface, the bus master can access the RDRAM (SDRAM) via the CPU chip. The control method is described.
[0003]
[Problems to be solved by the invention]
When the data processor incorporates the cache memory, when the external bus master and the data processor share the cache target area (cacheable area), it is necessary to take coherency between the local memory and the cache memory. In order to maintain this coherency, for example, when an external bus master accesses the cacheable area, an interrupt is input to the data processor before the access, and the cache memory of the data processor is purged by the interrupt handler. Access the area. However, if an external bus master interrupts the data processor and the handler purges the cache memory, the performance may be degraded. In particular, when the amount of data transferred by the external bus master is small, preprocessing for realizing coherency by the interrupt handler takes longer than actual transfer, and cannot be ignored as overhead.
[0004]
In addition, the cache memory itself can actively monitor the bus access state, and can adopt a snoop cache control that operates actively so as to maintain cache coherency. The active control by the memory increases the physical and logical scale of the circuit, resulting in an increase in cost.
[0005]
An object of the present invention is to provide a data processing apparatus and further a data processing system capable of reducing overhead due to preprocessing for shifting to processing for maintaining cache coherency when a cacheable area can be shared with an external bus master. There is to do.
[0006]
Another object of the present invention is to provide a data processing apparatus and a data processing system capable of reducing the physical and logical scale for maintaining cache coherency when a cacheable area can be shared with an external bus master. Is to provide.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
[1] In the data processing device according to the present invention, the first bus and the second bus can be connected to the outside separately, and the external bus master connected to the first bus is connected to the second bus. A data processor capable of giving a bus right allowing access, and includes a cache memory capable of caching the external memory. This data processor checks the state of the cache memory when the condition of the access request from the external bus master satisfies a specific condition, and if there is a block that hits the cache memory for the memory access address from the external bus master, An operation for maintaining cache coherency with the data of the access address is performed, and external memory access in response to an access request from the external bus master can be started.
[0010]
According to the above-described means, in the preprocessing for shifting to the processing for maintaining the cache coherency when the data processing apparatus can share the cacheable area with the external bus master, the condition of the access request from the external bus master is a specific condition. What is necessary is just to determine whether it satisfy | fills, and preprocessing, such as a state preservation | save required for interruption processing to CPU, is not required. The relationship between CPU operations is matched by giving the external bus master the bus rights in the data processor. Further, since the cache memory does not actively perform the operation for maintaining the cache coherency by monitoring the bus state, the cache coherency is maintained as compared with the case where the conventional bus snoop cache control is employed. It is possible to reduce the physical and logical scale.
[0011]
As one specific aspect of the present invention, the data processing apparatus includes a control register for programmably specifying the specific condition. The control register has a first storage area for designating a specific address used for comparison with an access address. This is used to determine whether the access address is a cacheable area.
[0012]
The control register has a second storage area for designating an address range for address comparison. The size of the cacheable area can be specified arbitrarily.
[0013]
The control register includes a third storage area for designating whether a specific condition is satisfied when the address comparison result matches or does not match. When the cacheable area is directly specified using the first storage area and the second storage area, it is only necessary that the address comparison result coincides with a specific condition. When a non-cacheable area is designated using the first storage area and the second storage area, a mismatch between address comparison results may be satisfied as a specific condition. This is useful for specifying a state in which the cacheable area is divided into non-cacheable areas.
[0014]
The control register may have a fourth storage area for selectively designating that the specific condition is not satisfied. In short, it is possible to select / deselect a series of processes for maintaining cache coherency.
[0015]
For example, when the cache hit block in the cache based on the memory access address by the external bus master is dirty and responds to the write access, the cache coherency maintaining operation writes back the block and invalidates the cache hit. When a block is dirty and responds to a read access, the block is written back and cleaned, and when the cache hit block is clean and responds to a write access, the hit block is invalidated and the cache is hit When the block is clean and responds to read access, and when there is no block to hit, nothing is done.
[0016]
[2] A data processing apparatus according to the present invention from a more specific viewpoint includes a CPU incorporating a cache memory, an external interface circuit to which an external bus master can be connected, a memory interface circuit to which an external memory can be connected, and a common connection therebetween Having an internal bus. The external interface circuit can delegate the bus right in response to a request from the external bus master, and when the bus right is delegated, the memory interface circuit from the internal bus in response to a request from the external bus master The external memory can be accessed via Furthermore, the external interface circuit issues a predetermined cache control command to the CPU and waits for a predetermined response to the CPU when an access condition when accessing the external memory through the memory interface circuit satisfies a specific condition. Thus, external memory access via the memory interface circuit can be started. When the CPU receives the cache control command, the CPU checks the state of the cache memory, and if there is a block hitting the cache memory with respect to the memory access address, maintains the cache coherency with the data at the memory access address. It is possible to perform an operation and return the predetermined response to the external interface circuit.
[0017]
Also in the present invention, as described above, in order to shift to processing for maintaining cache coherency when the data processing apparatus can share a cacheable area with an external bus master, preprocessing such as state saving necessary for interrupt processing to the CPU is performed. In addition, the physical and logical scales for maintaining cache coherency can be reduced as compared with the case where the conventional bus snoop cache control is employed.
[0018]
Similarly to the above, the external interface circuit is preferably provided with a control register to which the first to fourth storage areas are allocated so that the specific condition can be specified in a programmable manner.
[0019]
When the external interface circuit is waiting for the predetermined response in a state in which the bus right is given to the outside, the external interface circuit has the bus right to the outside on condition that the state of the external interface circuit is the predetermined state. It is desirable to have a function that requests release and retry. The predetermined state is a state in which the external interface circuit cannot accept a new access request. For example, when the CPU instructs the external interface circuit to perform external read access and the CPU is waiting for data read, the external bus master may acquire the bus right from the external interface circuit and be able to access the external memory. At this time, even if the CPU attempts to write back the cache memory in order to maintain cache coherency, the CPU waits for read data for the previously issued read access, and therefore performs external memory access for write back. You couldn't do it and you could end up deadlocking. When the external interface circuit is in a state where it cannot accept a new access request, such a deadlock may occur. Therefore, the bus right is granted to the external bus master by the function of releasing the bus right and retrying. If abandoned, the previous read access is processed and the CPU can issue a new access request. In this state, the external bus master may retry the external memory access suspended or canceled due to the bus right abandonment. Thereby, the possibility of deadlock can be prevented in advance.
[0020]
[3] A data processing system according to the present invention includes a data processor, a local bus connected to the data processor, an external memory connected to the local bus, a system bus connected to the data processor, An external bus master connected to the system bus; and other circuits connected to the system bus. The data processor includes a cache memory that can give the external bus master a bus right that allows access to the external memory and that can cache the external memory, and access from the external bus master When the request condition satisfies a specific condition, an operation of checking the state of the cache memory and maintaining cache coherency with the data at the memory access address if there is a block hitting the cache memory with respect to the memory access address The external memory access in response to the access request from the external bus master can be started.
[0021]
The access request by the external bus master may include address space information to which the external bus master is connected. Thus, the data processor can interface with the external bus master in accordance with the access capability of the external bus master such as the bus width and the number of wait cycles.
[0022]
As described above, the data processor is preferably provided with a control register to which the first to fourth storage areas are allocated, so that the specific condition can be specified in a programmable manner. Further, when a plurality of external bus masters are connected to the system bus, the control registers may be provided according to the respective external bus masters so that the specific conditions can be specified in a programmable manner.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 illustrates a data processing system according to the present invention. The data processing system shown in FIG. 1 includes a data processor 1, a local bus 2 connected to the data processor 1, an external memory connected to the local bus 2, for example, a double data rate large capacity SDRAM (Synchronous Dynamic Random Access). Memory) 3, system bus 4 connected to the data processor 1, external bus master 5 connected to the system bus 4, other circuits connected to the system bus 4, such as flash memory (FLASH) 6 and SRAM (Static A random access memory (Random Access Memory) 7 and a PCI (Peripheral Component Interconnect) bus 8 connected to the data processor 1 are provided. The local bus 2 is dedicated to the SDRAM 3 and conforms to the bus specification of SSTL (Stub Series Terminated Transceiver Logic) 2, which is a small-amplitude high-speed interface for memory modules, for example. The system bus 4 conforms to LVTTL (Low Voltage TTL) and is used as a shared bus. The external bus master 5 means a bus master module such as a graphic controller or a hard disk controller. Although not shown, a plurality of external bus masters and a plurality of ASICs can be connected to the system bus 4.
[0024]
The data processor 1 includes a CPU 11 incorporating a cache memory 10, a DMAC 12 (Direct Memory Access Controller), a PCI interface circuit 13, an SDRAM interface circuit 14, an external bus interface circuit 15, a peripheral bridge interface circuit 16, a debug interface circuit 17, and the like. And an internal bus (on-chip bus) 18 for connecting the circuit modules. The peripheral bridge interface circuit 16 constitutes a bridge between the on-chip bus 18 and the peripheral bus 20. An appropriate internal peripheral circuit (IP) 21 is connected to the peripheral bus 20. The SDRAM interface circuit 14 is connected to the SDRAM 3, which is a local memory of the data processor 1, via the local bus 2. The external bus interface circuit 15 is connected to the system bus 4 and the on-chip bus 18.
[0025]
The SDRAM 3 includes a cacheable area by the cache memory 10. The external bus interface circuit 15 issues a bus right request from the CPU 11 that is the bus master module on the on-chip bus 18 side, a bus right request from the DMAC 12, and a bus right request from the external bus master 5 that is the bus master module on the system bus 4 side. Mediate. In FIG. 1, BREQ is a bus right request signal from the external bus master 5 to the external bus interface circuit 15, and BACK is a bus right approval signal from the external bus interface circuit 15 to the external bus master 5.
[0026]
If the CPU 11 or the DMAC 12 acquires the bus right, the bus master module that has acquired the bus right can access the circuit module of the system bus 4 via the external bus interface circuit 15.
[0027]
On the other hand, when the external bus master 5 on the system bus 4 side acquires the bus right, the external bus master 5 can access the circuit module of the system bus 4, and the SDRAM 3 can be accessed via the external bus interface circuit 15. Made possible. In the system shown in FIG. 1, the SDRAM 3 which is a high-speed and large-capacity memory is used as a local memory separated from the system bus 4 by using the high-speed bus specification of SSTL2. This is because it can be used as a memory or a frame buffer memory. The path when the external bus master 5 accesses the SDRAM 3 is a path that communicates with the external bus master 5, the external bus interface circuit 15, the on-chip bus 18, the SDRAM interface circuit 14, and the SDRAM 3. When the external bus master 5 on the system bus side acquires the bus right, the external bus master 5 can also access other circuit modules on the on-chip bus 18. In short, the external bus master 5 can access the data processor 1 including the local memory (SDRAM 3).
[0028]
FIG. 2 illustrates a physical address map assigned to a circuit module connected to the on-chip bus 18 of the data processor. Each circuit module is mapped to a 4-gigabyte (GB) address space. For example, in the figure, FEMI_db is an address space allocated to the external bus interface circuit 15 when the external bus interface circuit 15 is regarded as a memory mapped I / O, and EMI_DRAM is an address space of the SDRAM 3.
[0029]
FIG. 3 illustrates an address map assigned to the external bus interface circuit 15. Here, a 128 megabyte (MB) address space is divided into five areas from area 0 to area 4. As is apparent from the example in the figure, there are cases where a plurality of external bus masters 5 are connected to the external bus interface circuit 15. Although not shown, a plurality of ASICs can be connected.
[0030]
When the external bus master 5 accesses a circuit module on the system bus 4, a module selection signal (chip selection signal) of the corresponding circuit module is asserted to indicate which circuit module is accessed. When the external bus master 5 accesses the data processor 1, all module selection signals are negated. At this time, the external bus master 5 outputs address space information 26 (see FIG. 1) to the external bus interface circuit 15 in order to notify which area in FIG. The external bus interface circuit 15 has the memory control register AnMCR (n = 0 to 4) of FIG. 4 for each of the areas 0 to 4 of FIG. 3 as the control register 27, and is controlled by the address space information notified by the external bus master 5. One of the registers AnMCR (n = 0 to 4) is selected, whereby the external bus interface circuit 15 recognizes control information such as the number of wait cycles necessary for communication with the external bus master 5.
[0031]
The memory control register AnMCR (n = 0 to 4) in FIG. 4 exists corresponding to each of the areas 0 to 4 as described above, and between the device connected to each area and the external interface circuit 15. Specify parameters that regulate access. When the external bus master 5 accesses the external interface circuit 15, the address space information 26 notifies which address area it is connected to. The external interface circuit 15 performs interface control of information by handshaking with the external bus master 5 in accordance with the contents of the notified memory control register AnMCR (n = 0 to 4).
[0032]
FIG. 5 illustrates a bus arbitration sequence between the external bus master 5 and the external interface circuit 15. In the period T1, the system bus 4 is being accessed via the external interface circuit 15 by the CPU 11 on the on-chip bus 18 side. In the period T2, the state of the system bus 4 when the external bus master 5 takes the bus right and accesses the data processor 1 is shown. Since the external bus interface circuit 15 does not have the bus right, the external bus interface circuit 15 is in a high impedance state, and information such as an address is output from the external bus master 5 that has the bus right on the system bus 4. The period T3 indicates a state in which the system bus 4 is accessed again via the external interface circuit 15 by the CPU 11 or the like on the on-chip bus 18 side after that. In FIG. 5, the signals BREQ and BACK are shown as negative logic signals.
[0033]
FIG. 6 illustrates a processing flow when the external bus master 5 accesses the local memory. First, the external bus master 5 asserts the bus right request signal BREQ to the external interface circuit 15 to request the bus right of the on-chip bus 18 (ST1). If there is no conflict with the on-chip bus 18 side, the bus right approval signal BACK is asserted and the bus right is given to the external bus master 5 (ST2). As a result, the external bus master 5 accesses the data processor 1. Subsequently, the external bus master 5 sends an address, data (at the time of writing), and a command to the external interface circuit 15 (ST3). The external interface circuit 15 determines whether or not the memory access address is a cache coherency (also simply referred to as coherency) target address (ST4), and sends a coherency command to the CPU 11 when a specific condition of being a coherency target address is satisfied. . The details of the operation of the CPU 11 when a coherency command is received will be described later. Generally, the state of the cache memory 10 is checked, and if there is a block hitting the cache with respect to the memory access address, the memory access address An operation for maintaining cache coherency with the other data is performed, and a response to the coherency command is returned to the external interface circuit 15. When the external interface circuit 15 confirms receipt of a response to the coherency command (ST6), this time, it supplies an access command to the SDRAM interface circuit 14 to start an access operation of the SDRAM 3 (ST7).
[0034]
FIG. 7 illustrates a coherency processing flow by the CPU 11 after receiving a coherency command. The coherency command is accepted (ST10), the cache memory 10 is checked (ST11), it is determined whether or not there is a cache hit (ST12), and if it is a cache miss, a response to the coherency command is returned to the external interface circuit 15 (ST19). ). If it is a cache hit, it is determined whether or not the dirty block is hit (ST13), and it is then determined whether the access is a response to the write access, in other words, whether the coherency is maintained during the write access or the coherency during the read access. (ST14, ST15). As a result of the determination in steps ST12 to ST15, when the hit block in the cache is dirty and the access responds to the write access, the hit block is written back and invalidated (ST16). If it is dirty and responds to a read access, it writes back the hit block and cleans the block (ST17), and if the cache hit block is clean and responds to a write access, the hit block is invalidated (ST18), a response to the coherency command is returned to the external interface circuit 15 (ST19).
[0035]
The control register 28 for programmably specifying a specific condition called a coherency target address will be described. As the control register 28, the external interface circuit 15 includes, for example, a snoop address register SNPARn (n = 0, 1) illustrated in FIG. 8 and a snoop control register SNPCRn (n = 0, 1) illustrated in FIG. Have.
[0036]
FIG. 8 shows an example of the snoop address register SNPARn (n = 0, 1). In bits 31 to 0 (CADR: first storage area) of the snoop address register SNPARn, the CPU 11 can arbitrarily designate a 32-bit physical address (address information used for comparison with the access address).
[0037]
FIG. 9 shows an example of the snoop control register SNPCRn (n = 0, 1). Bits 1 to 0 (SNPMD: third storage area and fourth storage area) indicate whether to enable the function of the external interface circuit 15 to issue a coherency command, and when issuing a coherency command, a snoop address It designates whether to issue when the comparison result of the address of the register SNPARn and the access address of the external bus master 5 is coincident or not. Bits 4 to 2 (RANGE: second storage area) specify an address length for address comparison. Bits 7 to 4 specify to which area the external bus master connected to the snoop address register SNPARn and the snoop control register SNPCRn is used. In this example, two snoop address registers SNPARn and snoop control registers SNPCRn are both mounted, and it is possible to support up to a case where the external bus master 5 is connected to a maximum of two areas. When a plurality of external bus masters are connected, the external bus interface 15 can be arbitrarily controlled by providing the corresponding snoop address register SNPARn and snoop control register SNPCRn.
[0038]
When directly specifying the cacheable area CE1 of FIG. 10 using the first storage area of the snoop address register SNPARn and the second storage area of the snoop control register SNPCRn, a condition for issuing a coherency command is satisfied when the address comparison result matches. And it is sufficient. When the non-cacheable area NCE2 of FIG. 10 is designated using the first storage area of the snoop address register SNPARn and the second storage area of the snoop control register SNPCRn, the condition for issuing the coherency command is satisfied when the address comparison result does not match. And it is sufficient. This setting is convenient for designating a state where the cacheable area CE2 is divided into the non-cacheable area NCE2.
[0039]
Next, a deadlock condition caused by the full state of the internal buffer of the external interface circuit 15 and a method for solving it will be described with reference to FIG.
[0040]
When the external interface circuit 15 waits for a response from the CPU 11 to the cache coherency command while giving the bus right to the external bus master 5 (ST6 in FIG. 6), the state of the external interface circuit 15 is a predetermined state. For example, on condition that the request reception buffer (30 in FIG. 1) of the external interface circuit 15 is full and cannot accept a new access request (ST8 in FIG. 6), the external interface circuit 15 Has a function of requesting the external bus master to release the bus right and retry (ST9 in FIG. 6). For example, when the CPU 11 instructs external read access to the SRAM 7 or the like externally connected to the external interface circuit 15 and the CPU 11 is waiting for data read, the external bus master 5 acquires the bus right from the external interface circuit 15 and the SDRAM 3 May be made accessible. At this time, even if a cache coherent command is issued and the CPU 11 attempts to write back the cache memory 10, for example, the CPU 15 waits for read data for the previously issued read access, so the external memory for write back There is a possibility that access cannot be made and a deadlock occurs. Therefore, when the external interface circuit 15 is in a state where it cannot accept a new access request, such a deadlock may occur. Therefore, the bus right is released and retried to the external bus master 5 by the request function. If the right is abandoned, the previous read access is processed, and the CPU 11 can issue a new access request. In this state, the external bus master 5 may retry the access to the SDRAM 3 that has been interrupted or canceled due to abandonment of the bus right. Thereby, the possibility of deadlock can be prevented in advance.
[0041]
According to the data processor 1 described above and the data processing system to which the data processor 1 is applied, the following operational effects are obtained.
[0042]
When the external bus master 5 accesses the SDRAM 3 as the cacheable local memory of the data processor 1, the processing for maintaining the cache coherency of the cache memory 10 is not required, and the interrupt processing to the data processor 1 becomes unnecessary, and the processing overhead And the memory access can be speeded up. The data transfer processing of the external bus master 5 and the arithmetic processing of the data processor 1 can be executed in parallel, and the data processing performance can be improved. On the other hand, when interrupt processing to the data processor is interposed to maintain such cache coherency, the data processor cannot execute other processing during the execution of the interrupt handler, and overhead of interrupt processing About 50 to 100 cycles are required in processor machine cycles (interrupt start, register saving, recovery, etc.). In the present invention, the overhead is about 10 processor cycles, and data transfer and processor processing can be executed in parallel.
[0043]
Furthermore, the driver software for the external bus master 5 can be simplified, and the development man-hours can be reduced. This is because the coherency interrupt handler can be removed from the driver of the external bus master 5.
[0044]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0045]
For example, the cache operation associated with the coherency check when the external bus master performs read access can be performed as follows. That is, when the block in which the read hit of the cache memory is dirty, the hit block is written back and cleaned, and the data is directly supplied to the external interface circuit 15. When the read hit block of the cache memory is clean, the data of the hit block is supplied to the external interface circuit 15. As described above, since the data desired by the external bus master 5 exists in the cache memory 10 of the CPU 11 at the time of a read hit of the cache memory, by transferring the data directly from the CPU 11 to the external interface circuit 15, the above-described data is obtained. As compared with the case where the external interface circuit 15 receives the completion notification of the coherency command and accesses the SDRAM interface circuit 14 again, the high-speed access becomes possible.
[0046]
The on-chip circuit module of the data processor is not limited to the above description, and can be changed as appropriate. The external memory as the local memory is not limited to the double data rate SDRAM, but may be a single data rate or other storage type memory. The specifications of the system bus and the local bus are not limited to LVTTL and SSTL2, and can be changed as appropriate. The present invention can also be applied to a multiprocessor system composed of a plurality of cache built-in processors.
[0047]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0048]
When the external bus master accesses the cacheable memory of the data processing device, interrupt processing to the data processing device is not required to maintain cache coherency of the cache memory, and processing overhead for maintaining cache coherency is reduced. Access can be speeded up. The data transfer processing of the external bus master and the arithmetic processing of the data processing device can be executed in parallel, and the data processing performance can be improved. Furthermore, the driver software for the external bus master can be simplified and the development man-hours can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a data processing system according to the present invention.
FIG. 2 is an explanatory diagram exemplifying a physical address map assigned to a circuit module connected to an on-chip bus of a data processor;
FIG. 3 is an explanatory diagram illustrating an address map assigned to an external bus interface circuit;
FIG. 4 is an explanatory diagram of a memory control register AnMCR.
FIG. 5 is a timing chart illustrating a bus arbitration sequence between an external bus master and an external interface circuit.
FIG. 6 is a flowchart illustrating a process when an external bus master accesses a local memory.
FIG. 7 is a flowchart illustrating coherency processing by the CPU after receiving a coherency command.
FIG. 8 is an explanatory diagram illustrating an example of a snoop address register SNPARn.
FIG. 9 is an explanatory diagram illustrating an example of a snoop control register SNPCRn.
FIG. 10 is an explanatory diagram comparing a state in which a cacheable area is directly designated and a state in which a non-cacheable area is designated using the first storage area of the snoop address register and the second storage area of the snoop control register. .
[Explanation of symbols]
1 Data processor
2 Local bus
3 SDRAM
4 System bus
5 External bus master
10 Cache memory
11 CPU
15 External interface circuit
27, 28 Control register
AnMCR memory control register
SNPARn snoop address register
SNPCRn Snoop control register
CADR first area
SNPMD third storage area and fourth storage area
RANGE 2nd area

Claims (20)

The first bus and the second bus can be separately connected to the outside, and a bus right allowing access to the external memory connected to the second bus can be given to the external bus master connected to the first bus A data processing device comprising a cache memory capable of caching the external memory;
When the condition of the access request from the external bus master satisfies a specific condition, the state of the cache memory is checked, and if there is a block hitting the cache memory with respect to the memory access address, the data of the memory access address After performing the process of maintaining cache coherency between them, it is possible to start external memory access in response to an access request from the external bus master ,
The process of maintaining the cache coherency is:
A first process for determining whether the hit block is dirty;
A second process for determining whether the access from the external bus master is a write access or a read access;
A third process for writing back data contained in the hit block to the external memory and invalidating the cache memory block when the hit block is dirty and the write access; data processing apparatus comprising a. The process of maintaining the cache coherency further includes writing back and cleaning the block when the cache memory hit block is dirty and responding to a read access, and the cache memory hit block is clean. The data processing apparatus according to claim 1 , further comprising: a fourth process of invalidating the block when responding to a write access. Process of maintaining the cache coherency further when the block hit of the cache memory and a hit block is absent when responding to a read access to a clean, claim 1, characterized in that do nothing Or the data processing apparatus of 2 . 3. The data processing apparatus according to claim 1, further comprising a control register for programmably specifying the specific condition. 5. The data processing apparatus according to claim 4 , wherein the control register has a first storage area for designating a specific address used for comparison with an access address. 6. The data processing apparatus according to claim 5 , wherein the control register has a second storage area for designating an address range for address comparison. 6. The data processing apparatus according to claim 5 , wherein the control register has a third storage area for designating whether a specific condition is satisfied when the address comparison result matches or does not match. 6. The data processing apparatus according to claim 5 , wherein the control register has a fourth storage area for selectively designating that the specific condition is not satisfied. A data processing device having a CPU incorporating a cache memory, an external interface circuit to which an external bus master can be connected, a memory interface circuit to which an external memory can be connected, and an internal bus to which they are commonly connected,
The external interface circuit can delegate the bus right in response to a request from the external bus master, and when the bus right is delegated, the memory interface circuit from the internal bus in response to a request from the external bus master The external memory can be accessed via
When an access condition for accessing the external memory through the memory interface circuit satisfies a specific condition, a predetermined cache control command is issued to the CPU, and a predetermined response is waited for the CPU to pass through the memory interface circuit. External memory access can be started,
When the CPU receives the cache control command, the CPU checks the state of the cache memory, and if there is a cache hit block for the memory access address, the CPU maintains cache coherency with the data at the memory access address. The predetermined response can be returned to the external interface circuit ,
The process of maintaining the cache coherency is:
A first process for determining whether the hit block is dirty;
A second process for determining whether the access from the external bus master is a write access or a read access;
A third process for writing back data contained in the hit block to the external memory and invalidating the cache memory block when the hit block is dirty and the write access; data processing apparatus comprising a. The process of maintaining cache coherency further writes back the hit block and cleans the block when the hit block is dirty and responds to a read access, and the hit block is clean and responds to a write access. 10. The data processing apparatus according to claim 9 , further comprising a fourth process for invalidating the hit block. 11. The data processing apparatus according to claim 10 , wherein the external interface circuit has a control register for designating the specific condition, and the control register is accessible by the CPU. 12. The data processing apparatus according to claim 11 , wherein the control register has a first storage area for designating a specific address used for comparison with an access address from the external bus master . 13. The data processing apparatus according to claim 12 , wherein the control register has a second storage area for designating an address length for performing address comparison. 13. The data processing apparatus according to claim 12 , wherein the control register has a third storage area for designating whether a specific condition is satisfied when the address comparison result matches or does not match. 13. The data processing apparatus according to claim 12 , wherein the control register has a fourth storage area for selectively designating that the specific condition is not satisfied. The external interface circuit, when the external bus master is waiting for the predetermined responses that gave the bus, on condition that the state of the external interface circuit is in a predetermined state, to the external bus master 11. The data processing apparatus according to claim 10, wherein the bus right is requested to be released and retried. 17. The data processing apparatus according to claim 16 , wherein the predetermined state is a state in which the external interface circuit cannot accept a new access request. A data processor, a local bus connected to the data processor, an external memory connected to the local bus, a system bus connected to the data processor, an external bus master connected to the system bus, and the system A data processing system having other circuits connected to the bus,
The data processor includes a cache memory that can give the external bus master a bus right that allows access to the external memory and that can cache the external memory, and access from the external bus master A process of checking the state of the cache memory when a request condition satisfies a specific condition, and maintaining cache coherency with data at the memory access address if there is a block hitting the cache for the memory access address To enable external memory access in response to an access request from the external bus master ,
The process of maintaining the cache coherency is:
A first process for determining whether the hit block is dirty;
A second process for determining whether the access from the external bus master is a write access or a read access ;
When the hit block is dirty and the write access, the third process of writing back the data contained in the hit block to the external memory and invalidating the cache memory block; data processing system which comprises a.   19. The data processing system according to claim 18, wherein the access request from the external bus master includes address space information to which the external bus master is connected.   The data processor includes a control register for programmably specifying the specific condition, and the control register includes a first storage area for specifying a specific address used for comparison with an access address, and an address 19. A second storage area for designating an address range for comparison, and a third storage area for designating whether a specific condition is coincidence or mismatch of address comparison results. The data processing system described.

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