JP3072446B2 - Data processing device and cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

In the present invention, each of a plurality of processing devices has a cache memory, and each processing device has a main storage device.
Cache for executing relates to a data processing apparatus for sharing, particularly search for cache memory directory, and invalid
Related to a data processing device having a directory control function.
I do.

[0002]

2. Description of the Related Art Hitherto, in a data processing device, for example, a main storage device using a low-speed and large-capacity storage element and a cache device using a high-speed and small-capacity storage element are hierarchized. I have. The cache memory has a copy of the block obtained by subdividing the data on the main storage device,
The apparent access from the central processing unit to the main storage is speeded up.

In a data processing device based on a multiprocessor system in which a plurality of central processing units share one memory and each central processing unit has a cache memory, each central processing unit operates according to rewriting of the cache memory. In addition, it is necessary to rewrite or erase the contents of the cache memory of another central processing unit so that a memory mismatch does not occur.

In this case, when the cache memory receives a BI (Buffer Invalidation Request) request from the central processing unit, searches the cache memory directory, and finds that the contents of the invalidation address are in the cache memory. , The corresponding directory in the cache memory is invalidated.

Further, in order to perform this directory search in parallel with general memory access, a directory copy for invalidating a directory is provided in addition to a directory for memory access, and the same data is written to two directories. Thus, the efficiency of memory access is improved.

[0006]

Here, when an error occurs in a RAM (random access memory), for example, a directory, the data in the two directories differs due to the error. Therefore, the data in the two directories is compared, and if the data is different, it is determined that an error has occurred.

FIG. 6 is a block diagram showing an example of a conventional cache directory control system of this type. FIG.
, A directory (hereinafter, referred to as DIR) 11
And a directory copy (hereinafter referred to as DIRC) 12 having the same configuration as the above.

The DIR 11 receives a request address (hereinafter, referred to as a memory address) from a central processing unit (not shown) for memory access.
REQ ADR. ) And the match circuit 13-
0 performs a match check between WAY (way) 0 ADR from DIR 11 and REQ ADR, and WAY 0 A
If DR matches REQ ADR, DIR WAY0
The MCH is turned on, indicating that there is data to be sought in the cache memory.

The match circuit 13-1 checks the match between the WAY1 ADR from the DIR 11 and the REQ ADR, and if the WAY1 ADR matches the REQ ADR, the DIR WAY1 MCH is activated and data to be obtained exists in the cache memory. You can see that.

On the other hand, the DIRC 12 receives an invalidation address (hereinafter, referred to as BI ADR) and outputs a part of the address of the BI ADR to the match circuits 14-0 and 14-1. The match circuit 14-0 is connected to the WAY0 of the DIRC12.
ADR and BI ADR are checked for a match and WA
If Y0 ADR matches BI ADR, DIRCW
AY0 MCH rises, indicating that there is address data to be invalidated in the cache memory.

[0011] The match circuit 14-1 is provided with a W
AY1 ADR is checked for consistency with BI ADR, and if WAY1 ADR matches BI ADR, D
The IRCWAY1 MCH is turned on, and it is understood that there is address data to be invalidated in the cache memory.

In such a configuration, BI performs the following operation. (1) BI-ADR is passed only to the DIRC 12 to see if there is a match. (2) If there is no match, the process ends. (3) If there is a match, there is address data to be invalidated in the cache memory.
11, BI-ADR is passed to both the DIRC 12 and the corresponding entry is deleted.

Here, in (1) and (3), if any one of the match circuits 13-0, 13-1, 14-0, and 14-1 fails, the address to be invalidated is stored in the directory. Could remain. For this reason, the contents of the cache memory and the contents of the main storage device may be different.

Further, such directory data comparison has not been performed when the cache memory employs the set associative method. The reason for this is that in the set associative method, a plurality of ways are provided on a line accessed using a part of an address, and data and way addresses are registered in each of the ways. This is because every check requires a huge amount of material.

An object of the present invention is to provide a cache directory control function capable of detecting a failure of a match circuit so that an address to be invalidated does not remain in the directory and reducing the physical quantity of the directory.
Processing device and cache memory having the same
It is in.

[0016]

Means for Solving the Problems The present invention has the following arrangement to solve the above-mentioned problems. FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, each of a plurality of central processing units 1 has a set associative cache memory 8.
And each central processing unit 1 shares one main storage device 2 via the storage control device 3.

In each cache memory 8, the directory 11 has a plurality of ways at the same address, registers a way address for each way, and inputs a request address for memory access.

The directory copy 12 has a plurality of ways at the same address, registers a way address for each way, and inputs an invalidation address from the central processing unit 1 in which the contents of the cache memory 8 have been rewritten or erased. I do.

The selecting means 15 operates to select either the invalidation address or the request address and input the selected address to the directory 11. It is desirable that the selection means 15 be constituted by, for example, a multiplexer or a mechanical changeover switch.

When the selecting unit 15 selects an invalidation address, the matching unit 10 checks whether the way address of the directory 11 corresponding to the invalidation address matches the way address of the directory copy 12.

Then, a failure of the matching means 10 is detected based on the result of the matching means 10. More preferably, the following is desirable.

That is, there is provided a timer section 16 for counting the predetermined time interval, and the selecting means 15 is configured to perform a selection operation by an output at a predetermined time interval output from the clock section 16. It is desirable that the timer unit 16 be constituted by, for example, a timer or a program counter.

The matching means 10 has a first match circuit 13 for checking whether a way address matches a request address or an invalidation address selected by the selecting means 15 for each way, and A second match circuit for checking a match between a way address and the invalidation address for each way; and a check for match between the output of the first match circuit 13 and the output of the second match circuit. The third match circuit 17 may be used.

Of these match circuits, the first match circuit 13 is preferably formed by an EOR circuit.

[0025]

According to the present invention, in the cache memory 8, the directory 11 and the directory copy 12 have a plurality of ways at the same address and register a way address for each way.
Enter the request address and copy directory 1
2 inputs an invalidation address.

Then, the invalidating address is selected by the selecting means 15, and the invalidating address is input to the directory 11. Then, the matching means 10 checks whether the way address of the directory 11 and the way address of the directory copy 12 with respect to the invalidation address match, so that a failure of the matching means can be detected.

Further, the selection means 15 operates so as to input the invalidation address to the directory 11 at regular time intervals according to the output from the timer section 16, so that the failure of the matching means 10 can be periodically checked. From
It doesn't need as much to directly compare the contents of the directory .

Further, the first match circuit 13 checks the match between the way address and the request address selected by the selecting means 15 for each way, and performs a memory access when they match. Second match circuit 1
4 performs a match check between the way address and the invalidation address for each way.

When the invalidating address is selected by the selecting means 15 , the first match circuit 13 checks whether the way address matches the invalidating address. Further, since the third match circuit 17 checks the match between the output of the first match circuit 13 and the output of the second match circuit 14, it can be seen from the result that one of the match circuits has failed. .

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described. <Embodiment 1> FIG. 2 is a block diagram showing the configuration of a first embodiment of a data processing apparatus using a multiprocessor system for implementing a cache directory control system according to the present invention.

In FIG. 2, six central processing units 1-0
1 to 5 are connected to the main storage device 2 via the storage control device 3 so that each central processing unit 1 (1-0 to 1-5) shares the main storage device 2.

FIG. 3 shows a detailed configuration of each central processing unit and its peripheral circuits. Each central processing unit includes an instruction control unit 5, an operation execution unit 6, and a storage control unit 7.

The storage control unit 7 includes a directory unit 9
And a cache memory 8 comprising a data section 20 and
The directory section 9 is searched for a memory access from the instruction control unit 5, and the result is stored in the instruction control unit 5.
Send to

The data section 20 is accessed by the address data registered in the directory section 9 when a block corresponding to the directory section 9 exists,
The desired block is read and the data in the block is sent to the instruction control unit 5. The directory section 9 manages entries according to a request from the instruction control unit 5. <Structure of Cache Memory 8> FIG. The cache memory 8 stores two WAY0 ADR and WAY1 A at the same address.
It has a DIR 11 that has a DR and inputs a request address for memory access from the central processing unit 1. BI ADR or REQ on the input side of DIR11
A selector (hereinafter referred to as SEL) 15 for selecting ADR and outputting it to DIR 11 is provided.

A counter (hereinafter referred to as CNTR) 16
Is used to count time, and SE is counted at regular time intervals.
L15 provides a selection signal for performing a selection operation.

The DIRC 12 stores two Ws at the same address.
It has AY0 ADR, WAY1 ADR, and input the invalidation address from the central processing unit 1 which caused the rewrite or erase the contents of the cache memory 8.

The match circuit 13-0 includes the DIR 11 and the SE
WA15 ADR and SE of DIR11 connected to L15
A match check with BI ADR or REQ ADR from L15 is performed, and its output is output to a match circuit 17-0. When these addresses match, DIR WAY0 MCH is output.

The match circuit 13-1 includes the DIR 11 and the SE
WAY1 ADR and SE of DIR11 connected to L15
A match check with BI ADR or REQ ADR from L15 is performed, and its output is output to a match circuit 17-1. When these addresses match, DIR WAY1 MCH is output.

On the other hand, the cache memory 8 has a DIRC 12 having the same configuration as the DIR 11, and the DIRC 12 has two WAY0 ADRs and WAY1 ADRs.
IADR is input.

The match circuit 14-0 is connected to the input / output side of the DIRC 12, and is connected to the WAY0 ADR and B
A match with IADR is checked, its output is output to match circuit 17-0, and when these addresses match, DIRCWAY0 MCH is output.

The match circuit 14-1 is connected to the input / output side of the DIRC 12, and is connected to the WAY1 ADR and the B
A match with the IADR is checked, and its output is output to the match circuit 17-1. When these addresses match, a DIRCWAY1 MCH is output.

The match circuit 17-0 includes a match circuit 13-
A match between the output of the match circuit 13-0 and the output of the match circuit 14-0 is checked.
The output “1” is output to the EOR circuit 18 when the output of −0 matches. The match circuit 17-1 is a match circuit 1
A match between the output of the match circuit 13-1 and the output of the match circuit 14-1 is checked. When the output of the match circuit 13-1 matches the output of the match circuit 14-1, the output "1" is EOR.
Output to the circuit 18.

The EOR circuit 18 determines whether the output of the match circuit 17-0 corresponding to way 0 is "1" and
Other than when the output of the match circuit 17-1 corresponding to "1" is "1", the comparison error (CMPR ERR)
Is output.

Next, the cache directory control system according to the first embodiment configured as described above will be described.
First, normally, the SEL 15 selects the REQ ADR, and the REQ ADR is input to the DIR 11 and also to the match circuits 13-0 and 13-1. Then, REQ ADR and WAY0 are output by the match circuit 13-0.
-A match with ADR is performed and WAY0 ADR
Is equal to REQ ADR, DIR WAY0 M
The CH is turned on, indicating that there is data to be sought in the cache memory 8.

The match circuit 13-1 checks the match between the WAY1 ADR from the DIR 11 and the REQ ADR. If the WAY 1 ADR matches the REQ ADR, the DIR WAY 1 MCH is activated and the data to be obtained exists in the cache memory 8. You can see that

On the other hand, the DIRC 12 receives the BI ADR and inputs a part of the address of the BI ADR to the match circuit 14-.
0, 14-1. The match circuit 14-0 has a DI
A check is made between the WAY 0 ADR and the BI ADR of the RC 12, and if the WAY 0 ADR matches the BI ADR, the DIRC WAY 0 MCH is activated, and it can be seen that there is address data to be invalidated in the cache memory 8.

The match circuit 14-1 is provided with the W
AY1 ADR is checked for consistency with BI ADR, and if WAY1 ADR matches BI ADR, D
The IRCWAY1 MCH rises, and it can be seen that there is address data to be invalidated in the cache memory 8.

Next, counting is performed by the CNTR 16, for example, once every tens or hundreds of times.
6 sends a selection signal to the SEL 15. Then SE
L15 is switched to select BI ADR,
ADR is DIR11 and match circuit 13-0,13-
1 is input.

Then, the invalidation address and the WAY0-ADR of the directory 11 are matched by the match circuit 13-0.
Is checked, and the match circuit 13-1 checks the match between the invalidation address and the WAY1 ADR of the DIR11.

Further, the match circuit 17-0 checks the match between the output of the match circuit 13-0 and the output of the match circuit 14-0, and outputs the result to the EOR circuit 18. Match circuit 1 by match circuit 17-1
A match between the output of 3-1 and the output of match circuit 14-1 is checked, and the result is output to EOR circuit 18.

In the EOR circuit 18, the DIRC WAY 0
The output of MCH and the output of DIR WAY0MCH completely match, and the output of DIRC WAY1 MCH and D
When the output of the IR WAY1 MCH completely matches, the CMPR ERR is not output. This indicates that the contents of the two DIR11 and DIRC12 match.

On the other hand, match circuits 13-0, 13-1, 1
4-0, 14-1, 17-0, 17-1, EOR circuit 1
8 fails, the DIRC WAY 0
The output of MCH does not completely match the output of DIR WAY0 MCH and / or DIRC WAY1 MC
Since the output of H and the output of DIR WAY1 MCH do not completely match, the EOR circuit 18 uses the CMPR ER
ROR is established, and it can be seen that the contents of the two directories do not match.

That is, there is a possibility that the address to be invalidated remains in the directory. Therefore,
This indicates that all purging and the like are necessary. As described above, according to the first embodiment, the contents of the directory and the contents of the directory copy are read using the same address at regular time intervals, and the match output is compared. Therefore, when a failure of the match circuit is detected, Performs all the purging, the address to be invalidated does not remain in the directory, and the reliability of the computer can be improved. In addition, since the match output is compared at regular time intervals, there is no need for a physical quantity sufficient to directly compare the contents of the directory.

Next, a second embodiment for realizing the cache directory control system according to the present invention will be described. <Embodiment 2> FIG. 5 shows an example of the configuration of the directory 11a of the embodiment 2. The directory 11a is provided with eight WAY0-WAY7 on the same address.
Address bits 20-25 of QADR or BI ADR
Is to be entered.

In addition, 8 corresponding to each of WAY0 to WAY7.
Three match circuits 13-0 to 13-7 are provided,
Address bits 01 to 19 of REQ ADR or BIADR are input to the respective match circuits 13-0 to 13-7. Each match circuit 13-0 to 13-7 is a WA
Y0 MATCH to WAY7 MATCH are output.

Although not shown, the directory copy 12a has the same configuration as the directory 11a, except that only the BI ADR is input. further,
These match circuit 13 over 0 to 13 over 7, 14 over 0-1
If match circuits 17-0 to 17-7 are provided corresponding to 4-7 and a NAND circuit is provided, WAY 0
~ WAY7 can be checked for a match.

Further, the present invention can be applied to a plurality of ways other than the first and second embodiments. Further, the address is not limited to a part of the BI ADR, and an address generated arbitrarily or in ascending order or descending order may be input to two directories at regular time intervals.

In the first and second embodiments, a case has been described in which a plurality of central processing units 1 share one main storage device 2. For example, a plurality of central processing units 1 are provided with a plurality of main storage units. The present invention can be similarly implemented even when the device 2 is shared .

[0059]

According to the present invention, the contents of the directory and the contents of the directory copy are read out using the same address at fixed time intervals, and the match output is compared, so that the failure of the matching means can be detected. Can be.

If all purging is performed when a failure of the match circuit is detected, the address to be invalidated does not remain in the directory.
The reliability of the computer can be improved.

Further, since the comparison of the match output is performed at regular time intervals, it is not necessary to have the physical quantity required to directly compare the contents of the directory.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration block diagram of a first embodiment according to the present invention.

FIG. 3 is a configuration block diagram of each CPU.

FIG. 4 is a detailed configuration block diagram of a directory unit.

FIG. 5 is a configuration diagram of a directory according to a second embodiment of the present invention.

FIG. 6 is a configuration block diagram showing an example of a conventional cache directory control method.

[Explanation of symbols]

 1, central processing unit 2, main storage unit 3, storage control unit 5, instruction control unit 6, arithmetic execution unit 7, storage control unit 8, cache memory 9, directory unit 10, match Means 11 DIR 12 DIRC 13, 14, 17 Match circuit 15 SEL (selector) 16 CNTR (counter) 18 EOR circuit 20 Data section

──────────────────────────────────────────────────続 き Continued from the front page (56) References JP-A-63-197253 (JP, A) JP-A-1-204164 (JP, A) JP-A-64-82238 (JP, A) JP-A-4- 191945 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/08 G06F 12/16 310 G06F 15/16

Claims (4)

(57) [Claims] 1. A set associative cash cache
Multiple central processing units with memory share main storage
In the data processing device, each cache memory registers a way address for each of a plurality of ways, and
Request for memory access from the central processing unit
Register a directory for inputting addresses and way addresses for each of a plurality of ways.
The central processing unit that has rewritten or erased the memory contents
Directory copy to input an invalidation address from the server, and either the invalidation address or the request address
And selecting when the invalidation address is selected by the selecting means.
Way of the directory corresponding to the invalidation address of
Address and the way address of the directory copy
And a matching means for performing a match check on the data processing device. 2. A timer unit for measuring a predetermined time interval,
From the time interval output from the timer
2. The apparatus according to claim 1, wherein said selecting means performs a selecting operation.
On-board data processing device. 3. The method according to claim 1, wherein the matching means includes a way for each of the ways.
Address and the request address selected by the selection means.
Address or invalid address
1 match circuit, and a way address and
The second map for checking the match with the invalidation address
Switch and the output of the first match circuit and the second match.
Match to check the match with the output of the switch circuit
2. The circuit according to claim 1, wherein the circuit comprises a circuit.
Data processing device. 4. A plurality of central processing units sharing a main storage device.
Set associative key provided for each
In cache memory, Before registering the way address for each way of multiple ways
Request for memory access from the central processing unit
A directory for entering the address, Register a way address for each of multiple ways and save
Rewriting of moly contents or The central processing unit that caused the erasure
A directory copy to enter the invalidation address from Either the invalidation address or the request address
Selecting means for selecting and inputting to the directory; When the invalidating address is selected by the selecting means,
Way of the directory corresponding to the invalidation address of
Address and the way address of the directory copy
A matching means for checking the match of A cache memory comprising: