JP2004062377A - Shared cache memory fault processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To narrow the affecting range of a fault generated in a cache memory as far as possible by specifying the position of the fault and limiting a section which is affected by the fault. <P>SOLUTION: A shared cache memory fault processing system comprises an address comparator 59 for suppressing the hit decision of a compartment which is not allocated to a request source processor in indexing a cache by a request from an optional processor, a replacement entry generation circuit 55 for selecting the compartment allocated to the request source processor in accordance with constitutional information stored in a compartment instruction circuit 52 in registering data in the cache, a fault detection circuit 58 for informing the compartment number of a fault whose correction is impossible when the correction disabled fault is detected at the time of cache index, and a shared cache control part 51 for specifying a section which can be affected by the fault on the basis of the information from the fault detection circuit 58, updating the constitutional information, and informing the compartment instruction circuit 52 of updated contents to process the fault. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a shared cache memory failure handling method, and more particularly to a shared cache memory failure handling method for continuing system operation while limiting a range affected by a failure occurring in a cache memory shared by a plurality of processors.
[0002]
[Prior art]
FIG. 7 is an explanatory diagram illustrating an example of a computer system including a shared cache memory. In the figure, shared cache units 21 and 22 are shared caches having the same configuration, and are shared by processors 11, 12, 13 and 14, respectively. On the other hand, the shared cache units 21 and 22 are connected to the main memory 41 via the system bus 31.
[0003]
Recently, in such a system, it is possible to logically divide resources such as a processor and a main memory into a plurality of partitions and operate each of them as an independent system. In this case, when a memory access from a processor belonging to each section is performed, the software is aware of the existence of another section by adding the start address of the memory area allocated to the section as an offset value at the time of transmission from the processor. Instructions can be executed without the need.
[0004]
However, when considering the reliability of each section, a unit shared by a plurality of sections, for example, the shared cache unit 21 is a single point of failure (SPOF: Single) of the section 1 and the section 2 as can be understood from the drawing. (Point of Failure), and there is a problem in that a failure of the cache memory causes two partitions to go down.
[0005]
[Problems to be solved by the invention]
As described above, in a computer system having a conventional shared cache memory, when a failure occurs in a cache memory shared by a plurality of partitions, if the failure cannot be corrected, each partition is There is a disadvantage that the system will go down.
[0006]
An object of the present invention is to identify the location of a fault that has occurred in a cache memory, limit the section affected by the fault, and reduce the range of the fault as much as possible in order to improve the above problems. It is an object of the present invention to provide a shared cache memory failure handling method that can perform the processing.
[0007]
[Means for Solving the Problems]
The shared cache memory failure processing method according to the present invention is directed to a shared cache memory having a plurality of compartments, in which a usable compartment is pre-allocated for each processor in a shared cache memory shared by a plurality of processors, and a processor divided into an arbitrary plurality of partitions. In the case where the shared cache memory is shared, when an uncorrectable failure is detected at the time of cache indexing, a section affected by the failure is specified, and a means for processing the failure is provided.
[0008]
A shared cache memory fault processing method according to the present invention is a compartment instruction circuit for storing configuration information indicating which compartment is to be assigned to each processor in a shared cache memory having a plurality of compartments and shared by a plurality of processors. And an address comparison circuit for suppressing a hit judgment of a compartment not allocated to the requesting processor when indexing the cache by a request from any processor, and a configuration held by the compartment instruction circuit when registering data in the cache A replacement entry generation circuit for selecting a compartment allocated to the requesting processor according to the information; and a failure detection circuit for notifying the compartment number when an uncorrectable failure is detected during cache indexing. And a shared cache control unit that identifies a section affected by the failure based on a notification from the failure detection circuit, updates the configuration information, notifies the compartment instruction circuit, and performs a failure process. I do.
[0009]
Further, in the above-described shared cache memory failure handling method, the compartment instruction circuit includes a register group including a bit width equal to the number of compartments of the cache and a word number equal to the number of processors connected to the cache, And obtaining and holding the configuration information from the unit, further obtaining a processor ID signal from the shared cache control unit to generate compartment allocation information, and notifying it to the address comparison circuit and the replacement entry generation circuit. Features.
[0010]
Further, the shared cache memory fault processing method of the present invention includes a fault history register for holding the number of faults occurring in a cache for each compartment in a shared cache memory having a plurality of compartments and shared by a plurality of processors; A replacement entry instruction circuit for determining a compartment for registering data by referring to the information of the failure history register when registering data to the cache and instructing the cache, and when an uncorrectable failure is detected at the time of cache index, the compartment number is determined. A failure detection circuit for notifying the shared cache control unit, and a compartment having no failure history by referring to the information of the failure history register when registering data by mishit when accessing the cache by a request from an arbitrary processor. To And having a shared cache control unit instructing the replacement entry instruction circuit to-option.
[0011]
Further, in the above-described shared cache memory failure processing method, the failure history register includes a register group including a word number equal to the number of compartments in the cache and a bit width capable of holding the number of failures to be managed. Is stored for each compartment as failure history information, and the failure information is transmitted to the replacement entry generation circuit and the shared cache control unit.
[0012]
Further, in the shared cache memory failure processing method of the present invention, the shared cache control unit notifies a failure information received from the failure detection circuit to a diagnosis processor, and performs processing of the failure based on a diagnosis result of the diagnosis processor. It is characterized by executing.
[0013]
That is, the cache memory according to the present invention is a shared cache of a set associative system including a plurality of compartments, and an available compartment can be allocated in advance to each processor sharing the cache. As a result, when the shared cache is shared by the processors divided into a plurality of partitions, it is possible to specify a partition that leads to a system down when an uncorrectable failure occurs in the cache, and to limit the range of the failure.
[0014]
Further, the shared cache memory according to the present invention is provided with a failure history register for storing a failure history of the compartment for each compartment, so that the failure history of the cache compartment is managed and a replacement entry associated with a cache miss is determined. Registration in a compartment having a failure history can be suppressed.
[0015]
Furthermore, by managing the history of faults, when a fault is detected in the cache memory, the fault history register is referenced, and if it is determined that a fault has repeatedly occurred in the relevant compartment, the operation of the cache memory is stopped. Then, it is possible to shift to system down.
[0016]
The present invention is particularly effective for a system in which a computer system is divided into a plurality of logical partitions and an operating system can be operated independently in each of the partitions, when a cache memory is shared from a plurality of partitions, It is possible to specify a section where an unusual failure has occurred, limit the range of the failure, and continue operation without affecting the operation of other sections.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, a shared cache memory failure processing method according to the present invention provides configuration information indicating which compartment is assigned to each processor in a shared cache unit 21 having a plurality of compartments and shared by a plurality of processors 11 and 12. When the cache is indexed by a request from an arbitrary processor, an address comparison circuit 59 that suppresses a hit judgment of a compartment that is not allocated to the requesting processor, and when registering data in the cache. A replacement entry generating circuit 55 for selecting a compartment allocated to the requesting processor in accordance with the configuration information held by the compartment instructing circuit, and when an uncorrectable failure is detected during cache indexing A failure detection circuit 58 for notifying the compartment number of the same, and a shared section for identifying the section affected by the failure based on the notification from the failure detection circuit, updating the configuration information, notifying the compartment instruction circuit, and performing failure processing A cache control unit 51.
[0019]
That is, configuration information indicating which cache compartment is to be assigned to each of the processors 11 and 12 is stored in the compartment instruction circuit 52. When the cache is indexed by a request from the processor 11 or 12, the address comparison circuit 59 suppresses the determination of a hit in a cache compartment that is not allocated to the requesting processor.
[0020]
When registering data in the cache, the replacement entry generation circuit 55 selects a compartment to be registered from the cache compartments assigned to the requesting processor. Thus, it is possible to arbitrarily assign an available cache compartment for each processor according to the configuration information held by the compartment instruction circuit 52.
[0021]
When the failure detection circuit 58 detects an uncorrectable error at the time of cache indexing, the shared cache control unit 51 notifies the diagnostic processor of an error report and the requesting processor number. As a result, the diagnostic processor specifies the partition affected by the failure, and brings the partition down.
[0022]
Referring to FIG. 1, the shared cache control unit 51 is connected to the processors 11, 12 and the system bus 31, and has a control function in the shared cache unit 21.
[0023]
The compartment instruction circuit 52 is connected to the shared cache control unit 51, the replacement entry circuit 55, and the address comparison circuit 59, and provides information indicating which cache compartment is assigned to the index request source and is valid at the time of cache indexing. Output.
[0024]
The LRU memory 53 is a memory used for LRU (Least Recently Used) control of the cache, and holds 1-bit information for each line of the cache.
[0025]
The address generation unit 54 inputs and holds the cache index address from the shared cache control unit 51, and outputs a part of the address as a cache index address and a key.
[0026]
The replacement entry generation circuit 55 is connected to the shared cache control unit 51, the compartment instruction circuit 52, and the LRU memory 53, determines a cache compartment to be registered at the time of registering data in the cache, and determines a cache address array (AA) 56 and cache data. An instruction to write to the determined compartment is output to the array (DA) 57.
[0027]
The shared cache is a two-way set associative store-in cache, and a cache AA 56 for storing a key address of the cache and a cache DA 57 for storing a data block constitute a memory array including two compartments.
[0028]
The address comparison circuit 59 receives signals from the cache AA 56, the compartment instruction circuit 52, and the address generation unit 54, performs a cache hit determination, and outputs a determination result.
[0029]
The data selector 60 receives an output from the address comparison circuit 59, selects an output from any one of the data read from the cache DA 57, and outputs the selected data.
[0030]
The failure detection circuit 58 performs a parity check on the values read from the cache AA 56 and the cache DA 57, and outputs the compartment number to the shared cache control unit 51 when an error is detected.
[0031]
FIG. 2 is a configuration diagram showing an example of the compartment instruction circuit 52 and the replacement entry generation circuit 55.
[0032]
In FIG. 2, the compartment instruction circuit 52 is constituted by a register group consisting of two words of a register having a 2-bit width. Here, the bit width of the register is equal to the number of compartments of the cache, and the number of words is equal to the number of processors directly connected to the shared cache unit 21. These registers hold the allocation configuration information for each cache compartment input from the shared cache control unit 51.
[0033]
In addition, the compartment instruction circuit 52 receives two request source ID signals corresponding to each word of the register from the shared cache control unit 51, and converts the request source ID signal into a word of “1” for each bit of the register group. The logical sum of the stored values is output and distributed to the replacement entry generation circuit 55 and the address comparison circuit 59 as compartment allocation information.
[0034]
Further, referring to FIG. 2, the replacement entry circuit 55 is realized by a simple combination circuit. FIG. 3 shows the truth values of this combinational circuit.
[0035]
Next, the operation of the above-described shared cache memory will be described.
[0036]
(1-1) Initialization of shared cache memory
When the initialization of the shared cache memory is performed when the system is started, the compartment instruction circuit 52 is added to the operations of clearing the cache AA 56, the cache DA 57, and the LRU memory 53 as performed when the normal cache memory is initialized. Is initialized.
[0037]
As described above with reference to FIG. 2, the compartment instructing circuit 52 includes a register that stores information on the association between each processor connected to the shared cache memory and each compartment of the shared cache memory. Set by control from an external diagnostic processor.
[0038]
FIG. 2 illustrates an example in which the processor 11 is assigned the compartment 0 of the shared cache memory and the processor 12 is assigned the compartment 1 of the shared cache memory as an example of the setting.
[0039]
(1-2) Reading from cache memory
Next, an operation for reading the shared cache memory from the processors 11 and 12 will be described. First, a read request from the processor is sent to the shared cache control unit 51, and the shared cache control unit 51 starts reading the shared cache memory. .
[0040]
The shared cache control unit 51 sends an ID signal corresponding to the processor number of the read request source to the compartment instruction circuit 52, and obtains compartment allocation information of the shared cache allocated to the processor.
[0041]
On the other hand, the read address is sent from the shared cache control unit 51 to the address generation unit 54, the index addresses of the cache AA 56 and the cache DA 57 are obtained, each memory array is indexed, and the index key is passed to the address comparison circuit 59.
[0042]
The address comparison circuit 59 compares the cache AA 56 with the index key obtained from the address generation unit 54 and makes a cache memory hit determination. At this time, the compartment allocation information from the compartment instruction circuit 52 indicates to the read requesting processor Masks hit assignments for unassigned compartments. The data selector 60 obtains the hit determination result, selects one of the data output from the cache DA 57, and transfers it to the shared cache control unit 51.
[0043]
At this time, if a cache hit occurs, the shared cache control unit sends the fetched data to the processor to complete a series of operations. However, if a cache miss occurs, data is further fetched from the main memory 41.
[0044]
First, the shared cache control unit that has received the notification of the cache mishit from the address comparison circuit 59 sends a request for reading the requested address to the system bus 31.
[0045]
Subsequently, the LRU memory 53 determines a cache compartment to be replaced according to a predetermined logic. This information is masked by the compartment assignment information obtained from the compartment instruction circuit 52 in the replacement entry generation circuit 55, and is assigned to the requesting processor. Obtain one compartment from among the compartments assigned.
[0046]
The shared cache control unit reads the data of the compartment from the cache AA 56 and the cache DA 57 and, if the data has been updated (registered as a “dirty” block in the cache), via the system bus 31. The replacement operation is completed by writing the data back to the main memory.
[0047]
Subsequently, in response to the read request to the system bus 31, the main memory 41 or another shared cache returns a response. Therefore, the shared cache control unit 51 determines the requested address and data in the cache AA56 and the cache DA57 in advance. At the same time as writing to the compartment, it is sent to the requesting processor.
[0048]
(1-3) Writing to cache memory
Next, the write operation from the processors 11 and 12 to the shared cache memory will be described. First, in the case of a write request from the processor, the index of the shared cache memory is performed as in the case of reading.
[0049]
If a cache hit occurs, the shared cache control unit 51 writes the requested address to the corresponding entry of the cache AA 56 and the cache DA 57, updates the LRU memory 53, and completes the write operation.
[0050]
When a cache miss occurs, data is first registered from the main memory or another shared cache memory to the shared cache memory, and a cache replacement operation is performed as necessary. Writing to the shared cache memory is performed as in the case of a hit, and the operation is completed.
[0051]
(1-4) Bus snoop operation
In addition to the above-described cache read / write operation, the configuration of the above-described shared cache memory requires a cache snooping and data sweep-out / update operation by a bus snoop. The individual indexing operation, sweeping-out operation, and updating operation are the same as the operations described in the above description, so that the description will not be repeated here.
[0052]
(1-5) Operation when a cache failure occurs
When the failure detection circuit 58 detects a failure in a read request from the processors 11 or 12 or a read operation accompanying a replace operation at the time of a cache miss, the shared cache control unit 51 interrupts the read operation of the shared cache memory to perform the shared operation. The operation of the cache unit 21 is temporarily suspended (HOLD), the occurrence of a failure is notified to an external diagnostic processor, and the subsequent failure processing is entrusted.
[0053]
Upon receiving the notification of the uncorrectable failure of the cache memory, the diagnostic processor extracts the failure compartment number and the allocation information of the processor and the cache compartment through the shared cache control unit 51, specifies the logical partition to which the failure spreads, A process for bringing the logical partition down is started.
[0054]
On the other hand, if the shared cache memory includes a logical partition to which a failure does not propagate, the setting information of the compartment instruction circuit 52 is updated to prevent access from the failed logical partition, and then the shared cache is updated. Release the hold of the unit and resume operation.
[0055]
FIG. 4 is a block diagram showing a second embodiment of the present invention. In the figure, the shared cache memory failure handling system according to the present invention holds the number of failures occurring in a cache for each compartment in a shared cache unit 21a having a plurality of compartments and shared by a plurality of processors 11 and 12. A failure history register 62; a replacement entry instruction circuit 65 for determining a compartment for registering data by referring to the information of the failure history register when registering data in the cache and instructing the cache; And a failure detection circuit 68 for notifying the shared cache control unit of the compartment number when the cache history is detected. Reference to select a compartment no fault history instructing the replacement entry indicating circuit and a shared cache control unit 61.
[0056]
That is, the failure history register 62 is a register that stores, for each cache compartment, a value indicating the number of times a failure has occurred in the cache address array (AA) 66 for storing tags and the cache data array (DA) 67 for storing data. The failure history register 62 has a plurality of bits of information for each cache compartment, and information obtained by ORing each of them is output as a failure history.
[0057]
When registering data in the cache due to a cache mishit in response to a request from the processor 11 or 12, the replacement entry generation circuit 65 selects a compartment to be registered from cache compartments having no history of occurrence of a failure. As a result, new registration in a compartment having a failure history can be suppressed, and a cache line in which a failure has actually occurred can be prevented from being overwritten and reused.
[0058]
Referring to FIG. 4, the shared cache control unit 61 is connected to the processors 11, 12 and the system bus 31, and has a control function in the shared cache unit 21a.
[0059]
The failure history register 62 is connected to the shared cache control unit 61 and the replacement entry generation circuit 65, and is the number of times a failure has occurred in the cache address array (AA) 66 for storing tags and the cache data array (DA) 67 for storing data. Is stored for each cache compartment.
[0060]
The LRU memory 63 is a memory used for LRU (Least Recently Used) control of the cache, and holds 1-bit information for each line of the cache.
[0061]
The address generation unit 64 inputs and holds the cache index address from the shared cache control unit 61, and outputs a part of the address as the cache index address and the key.
[0062]
The replacement entry generation circuit 65 is connected to the shared cache control unit 61, the failure history register 62, and the LRU memory 63, determines a cache compartment to be registered when registering data in the cache, and sets a cache address array (AA) 66 and cache data. An instruction to write to the determined compartment is output to the array (DA) 67.
[0063]
The above-mentioned shared cache is a two-way set associative store-in cache, and the cache AA 66 and the cache DA 67 each constitute a memory array including two compartments.
[0064]
The address comparison circuit 69 receives a signal from the cache AA 66 and the address generation unit 64, performs a cache hit determination, and outputs a determination result. At this time, the result of the hit determination is not affected by the failure history information stored in the failure history register 62. Even in the compartment where the failure history remains, if the keys match, the determination result is output as a cache hit.
[0065]
The data selector 70 receives an output from the address comparison circuit 69, and selects and outputs an output from any one of the data read from the cache DA 67.
[0066]
The failure detection circuit 68 performs a parity check on the values read from the cache AA 66 and the cache DA 67, and outputs the compartment number to the shared cache control unit 61 when an error is detected.
[0067]
FIG. 5 is a configuration diagram showing an example of the failure history register 62 and the replacement entry generation circuit 65.
[0068]
In the figure, the failure history register 62 is composed of a register group consisting of two words of a 2-bit width register. Here, the number of words in the register is equal to the number of compartments in the cache, and the bit width needs to be large enough to indicate the number of failure histories to be managed. These registers hold failure history information for each cache compartment set by the shared cache control unit 61. All of the stored information is distributed to the shared cache control unit 61 and the replacement entry generation circuit 65.
[0069]
Further, the replacement entry circuit 65 is realized by a simple combination circuit as shown in FIG. FIG. 6 shows the truth values of this combinational circuit.
[0070]
Next, the operation of the above-described shared cache memory will be described.
[0071]
(2-1) Initialization of shared cache memory
When the initialization operation of the shared cache memory is performed when the system is started, in addition to the operation of clearing the cache AA 66, the cache DA 67, and the LRU memory 63 which is performed when the normal cache memory is initialized, the failure history register 62 Is initialized.
[0072]
As shown in FIG. 5, the failure history register 62 includes a register for storing failure history information for each compartment of the shared cache memory, and this history information is shared when a failure occurs during system operation. Rewritten by the cache control unit 61. Here, in order to show one state during system operation, an appropriate value is selected and displayed in the figure.
[0073]
(2-2) Reading from the cache memory
Next, the operation when reading the shared cache memory from the processors 11 and 12 will be described. First, a read request from the processor is sent to the shared cache control unit 61, and the shared cache control unit 61 starts reading the shared cache memory. .
[0074]
That is, the read address is sent from the shared cache control unit 61 to the address generation unit 64, the index addresses of the cache AA 66 and the cache DA 67 are obtained, each memory array is indexed, and the index key is passed to the address comparison circuit 69.
[0075]
The address comparison circuit 69 compares the cache AA 66 with the index key obtained from the address generation unit 64, and determines a hit in the cache memory. The data selector 70 obtains the hit determination result, selects one of the data output from the cache DA 67, and transfers it to the shared cache control unit 61.
[0076]
At this time, if a cache hit occurs, the shared cache control unit sends the fetched data to the processor to complete a series of operations. However, if a cache miss occurs, data is further fetched from the main memory 41.
[0077]
First, the shared cache control unit 61 that has received the notification of the cache mishit from the address comparison circuit 69 sends a request for reading the requested address to the system bus 31.
[0078]
Subsequently, the cache compartment to be replaced is determined according to a predetermined logic based on the LRU information stored in the LRU memory 63. This information is masked by the failure history information obtained from the failure history register 62 in the replacement entry generation circuit 65, A compartment number to be newly registered is obtained from compartments having no failure history.
[0079]
The shared cache control unit 61 reads the data of the compartment from the cache AA 66 and the cache DA 67, and if the data has been updated (registered as a “dirty” block in the cache) via the system bus 31 The replacement operation is completed by writing the data back to the main memory 41.
[0080]
Subsequently, since the main memory 41 or another shared cache memory returns a response in response to the read request to the system bus 31, the shared cache control unit 61 determines the requested address and data in the cache AA 66 and the cache DA 67 in advance. At the same time, the data is written to the compartment and sent to the requesting processor to complete a series of operations.
[0081]
(2-3) Writing to cache memory
Next, the write operation from the processors 11 and 12 to the shared cache memory will be described. First, in the case of a write request from the processor, the index of the shared cache memory is performed as in the case of reading.
[0082]
If a cache hit occurs, the shared cache control unit 61 writes the requested address to the corresponding entry of the cache AA 66 and the cache DA 67, updates the LRU memory 63, and completes the write operation.
[0083]
In the case of a cache miss, as in the case of a read miss, first, data is registered from the main memory 41 or another shared cache memory to the shared cache memory, and a cache replacement operation is performed as necessary. As in the case of a cache hit, writing to the shared cache memory is performed, and the operation is completed.
[0084]
(2-4) Bus snoop operation
In addition to the above-described cache read / write operation, the configuration of the above-described shared cache memory requires a cache snooping and data sweep-out / update operation by a bus snoop. The individual indexing operation, sweeping-out operation, and updating operation are the same as the operations described in the above description, so that the description will not be repeated here.
[0085]
(2-5) Operation when a cache failure occurs
When the failure detection circuit 68 detects a failure in a read request from the processor 11 or 12, the shared cache control unit 61 sends the read data as destroyed (POISONED) data to the requesting processor. The processor that has received the corrupted data determines that processing cannot be continued and starts processing such as shutting down the partition including the processor, but this process is beyond the scope of the present invention. I will not go into detail.
[0086]
Subsequently, the shared cache control unit 61 reads the value of the failure history register 62, adds +1 to the value of the word corresponding to the compartment in which the failure has occurred, and writes it back to the failure history register 62, thereby performing the subsequent cache replacement operation. For example, data is not newly registered in the compartment.
[0087]
At this time, if the value of the read failure history information is a prescribed value (here, “11”), it is determined that the failure in the same compartment has been repeated a prescribed number of times or more, and the operation of the shared cache unit 21 is performed. Is held (HOLD), and the fact that a fault has repeatedly occurred is notified to an external diagnostic processor (not shown) and the subsequent fault processing is entrusted.
[0088]
Upon receiving the notification, the diagnostic processor performs a failure process such as bringing down a system including all partitions.
[0089]
If the value of the read failure history information does not exceed the specified value, the shared cache control unit 61 further flushes the failed line of the cache AA 66 and discards the destroyed data.
[0090]
Further, when a failure is detected during a replace operation at the time of a cache miss or a read operation accompanying a write, the failure cannot be notified to the processor by the same means as in the above-described read operation. An attempt is made to specify a partition corresponding to the address from the address used for the cache access.
[0091]
In the case where a plurality of partitions are operated at the same time as in the above-described shared cache memory, a main storage address is assigned to each partition, and the main storage access from the processor is performed by adding an offset value for each partition. Is It is assumed that the addition of the offset value is performed inside the processor, whereby the software of each section can be executed without being aware of the existence of other sections. Therefore, if the address at the time of detecting the failure is known, it is possible to specify the corresponding section.
[0092]
When the partition is successfully specified, the shared cache control unit notifies one of the processors belonging to the partition of the failure using a means such as an interrupt. Upon receiving the notification, the processor determines that the continuation of the processing is impossible and starts processing such as bringing down the system of the partition.
[0093]
If the partition cannot be identified, the shared cache control unit 61 determines that the operation of the entire system including all the partitions cannot be continued, suspends the operation of the shared cache unit 21 (HOLD), and causes a fatal failure. Is notified to an external diagnostic processor, and the subsequent fault processing is entrusted.
[0094]
Further, when the section is successfully specified, the update of the failure history register 62 and the flush operation of the cache line are performed as in the case of the above-described readout, and a series of failure operations is completed.
[0095]
As described above, after the occurrence of a cache memory failure, the notification to the processor, the update of the failure history register, and the flushing of the cache line are completed, the shared cache unit 21 immediately continues to operate, and the subsequent memory An access request and a bus snoop operation can be executed. Therefore, in a section where the failure does not spread, the operation can be continued without being affected by the failure.
[0096]
Even after registration in the failed compartment is suppressed by the failure history, it is possible to read and write from already registered lines (healthy data) other than the failed line in that compartment. It is. Compared with the compartment degeneracy method that is generally performed when a cache fault occurs, the present invention does not require the process of flushing the cache accompanying the degeneration operation, and simplifies the fault processing procedure.
[0097]
In the above-described embodiment, the configuration of the shared cache memory is the two-way set associative system. However, the configuration can be configured with more compartments. For example, in the case of a 4-way set associative configuration, it is necessary to add 6-bit information to each line of the cache to the LRU memory, and the replacement entry generation circuit has a more complicated configuration. It is feasible.
[0098]
Further, in the above description, the failure detection circuit is a parity detection circuit, but it is also possible to perform failure detection and correction using an ECC (error correction code) as generally used in computer systems for mission critical applications today. is there.
[0099]
Further, the present invention can be realized without depending on the number of processors and buses connected to the shared cache.
[0100]
【The invention's effect】
As described above in detail, according to the present invention, when an uncorrectable failure is detected in a shared cache memory, it is possible to easily specify a logical partition using the failed cache line. Therefore, it is possible to cause only the partition concerned to perform closed failure processing, for example, system down, without spreading the failure to the operation of another logical partition.
[0101]
Furthermore, the cache memory can continue to operate even after a failure has occurred, and can continue to operate the system without affecting other partitions except for the partition affected by the failure.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a configuration diagram showing a main part of FIG. 1;
FIG. 3 is an explanatory diagram showing a truth value of a replacement entry generation circuit 55;
FIG. 4 is a block diagram showing a second embodiment of the present invention.
FIG. 5 is a configuration diagram showing a main part of FIG. 4;
FIG. 6 is an explanatory diagram showing a truth value of a replacement entry generation circuit 65;
FIG. 7 is an explanatory view showing a conventional example of the present invention.
[Explanation of symbols]
11, 12, 13, 14 processors
21, 21a, 22 Shared cache unit
31 System bus
41 Main Memory
51, 61 Shared cache control unit
52 compartment indication circuit
53,63 LRU memory
54, 64 address generator
55, 65 replacement entry generation circuit
56,66 Cache AA
57,67 Cache DA
58, 68 failure detection circuit
59, 69 Address comparison circuit
60, 70 data selector
62 Failure history register

Claims (6)

In a shared cache memory having a plurality of compartments and shared by a plurality of processors, a usable compartment is pre-allocated to each processor, and when the shared cache memory is shared by any of a plurality of divided processors, a cache is used. A shared cache memory failure processing method, comprising: when an uncorrectable failure is detected during indexing, a section affected by the failure is specified, and the failure is processed. In a shared cache memory having a plurality of compartments and shared by a plurality of processors, a compartment instruction circuit holding configuration information indicating which compartment is to be assigned to each processor, and a cache indexed by a request from an arbitrary processor An address comparison circuit for suppressing a hit determination of a compartment not assigned to the requesting processor, and selecting a compartment assigned to the requesting processor according to the configuration information held by the compartment instruction circuit when registering data in the cache. A replacement entry generation circuit, a failure detection circuit for notifying the compartment number when an uncorrectable failure is detected at the time of cache indexing, and the failure based on a notification from the failure detection circuit. Shared cache memory fault processing system characterized by having a shared cache control unit that identifies a partition to affect by updating the configuration information performs the notified failure processing to the compartments instruction circuit. 3. The shared cache memory fault handling method according to claim 2, wherein said compartment instruction circuit includes a register group including a bit width equal to the number of compartments of the cache and a word number equal to the number of processors connected to said cache. Obtaining the configuration information from the control unit and holding it, further obtaining a processor ID signal from the shared cache control unit to generate compartment allocation information, and notifying it to the address comparison circuit and the replacement entry generation circuit. A shared cache memory failure handling method. In a shared cache memory having a plurality of compartments and shared by a plurality of processors, a failure history register that holds the number of failures occurring in the cache for each compartment, and information of the failure history register when registering data in the cache. A replacement entry instructing circuit for determining a compartment for registering data by referring to and instructing the cache; a failure detecting circuit for notifying the shared cache control unit of the compartment number when an uncorrectable failure is detected during cache indexing; When registering data due to a mishit when accessing the cache in response to a request from the processor, the replacement entry instruction circuit is instructed to refer to the information in the failure history register and select a compartment having no failure history. Shared cache memory fault processing system characterized by having a shared cache control unit that. 5. The shared cache memory fault handling method according to claim 4, wherein said fault history register includes a register group including a word number equal to the number of compartments of the cache and a bit width capable of holding the number of faults to be managed. A shared cache memory failure processing method, wherein failure information transmitted by a section is stored as failure history information for each compartment, and is transmitted to the replacement entry generation circuit and the shared cache control unit. 6. The shared cache memory failure processing method according to claim 2, wherein the shared cache control unit notifies a failure information received from the failure detection circuit to a diagnosis processor, and outputs the failure information to a diagnosis result of the diagnosis processor. A shared cache memory failure handling method, wherein the failure is executed based on the failure.

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