JPH09269358A - Testing apparatus for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a testing apparatus in which the number of interleave stages of a memory used as a defect analysis memory is reduced by a method wherein a control means by which a DRAM can be operated at higher speed in a high-speed page mode by paying attention to a fact that an address generated by a pattern generator generates a regularly random or linear address pattern. SOLUTION: A plurality of DRAM's 160, 160,..., for storage of a fail address, are installed in the prescribed number of interleave stages. Small-capacity temporary buffer means (e.g. FIFO memories 130, 130,...) are installed so as to be inserted before the respective DRAM's 160. For a storage and control operation to the respective temporary buffer memory means, a storage control means is installed in such a way that an input fail address 321adr whose row address 121row is identical to the input fail address 321adr is stored in a temporary buffer memory means. The fail address 321adr which is stored in the temporary buffer memory means is read out, and the DRAM's 160 can be written in a high-speed write mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis memory of a semiconductor memory testing device for testing a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 3 shows the basic configuration of the entire memory test apparatus. The memory testing device includes a timing generator 310, a pattern generator 320, a failure analysis memory (AFM: addres).
s failure memory) 200, a waveform shaper 330, a logical comparator 340, and a memory under test (MUT) 1
1. Perform various tests. The timing generator 310 generates various reference clock signals. Pattern generator 3
Reference numeral 20 supplies an address signal, a test data signal, a control signal to be given to the MUT 11, a fail address 321adr to the AFM 200, and expected value data to the logical comparator 340. The waveform shaper 330 shapes the waveform into a predetermined waveform required for the test and then applies the waveform to the MUT 11. The MUT 11 is tested by writing and reading test data according to a control signal. The output data from the MUT 11 is given to the logical comparator 340. Logical comparator 340
Is the expected value data from the pattern generator 320 and the MU
The output data from T11 is compared and the resulting fail information 341fl is supplied to the AFM 200. In the AFM 200, the fail information 341fl and the pattern generator 32
The fail address 321adr from 0 is received, and based on this, it is stored as fail information in the position corresponding to the MUT11 address in the internal memory.

FIG. 2 shows an internal block diagram of a failure analysis memory (AFM). The main configuration of the AFM 200 is composed of an address selection unit 220, a memory control unit 240, and a memory unit 260. The address selection unit 220 receives the fail address 321 adr from the pattern generator 320, receives a selection condition from the outside, and receives the fail address 3 adr.
A desired upper address signal is selectively supplied from the 21 adr to the memory control unit 240, and the remaining lower address signals are supplied to the memory unit 260. The memory control unit 240 receives the fail information from the logical comparator 340 and sends a write signal to the memory unit 26 when the fail occurs.
0. The memory unit 260 receives the write signal and writes to the memory location corresponding to the lower address signal. Here, the memory circuit used in the memory unit 260 is required to operate at a higher speed than the MUT 11. Therefore, the high-speed SRAM is used for the interleaved structure to cope with the speedup. In the analysis after the test, the fail address of the MUT 11 is analyzed by sequentially checking the fail information stored in the SRAM of the AFM 200 in the interleaved configuration.

By the way, the MUT 11 which is the memory under test
The operating speed of the device has an access time of several nanoseconds in an ultrahigh-speed ECL device. On the other hand, 64 Mbits or more have appeared in large capacity DRAM. As described above, in order to support various types of memory devices of ultra-high speed or large-capacity, the memory used for the memory unit 260 needs a memory configuration means capable of operating at ultra-high speed and having large capacity. Conventional AFM memory unit 26
In No. 0, the high-speed SRAM has an interleaved structure to support ultra-high speed and large capacity.

By the way, for address access to the memory section 260, the address values are expressed as # 0, # 1, and # 2.
There are both cases of serial access that increases sequentially by one, and cases of discrete random access such as address values #FFFF, # 0, and # 1281, and it must be possible to support these. In addition, in the AFM, in order to support the bit configuration of the MUT and the simultaneous measurement of a large number, for example, 1 to 12
A flexible circuit configuration capable of 8-bit parallel operation is required.

By the way, in recent years, the capacity of high-speed SRAMs has been increasing, and it has become difficult to obtain large-capacity high-speed SRAMs. On the other hand, the memory under test M mainly composed of DRAM
As for the UT11, varieties with a larger capacity are appearing. Therefore, in order to increase the capacity of the memory unit 260, it is desirable to use a large capacity DRAM element as the memory element. However, the DRAM device can operate at a relatively high speed in a high-speed page mode (or hyper page mode operation) in which each column address is accessed within the same row address, such as serial access. In the case of frequently changing random access,
Each time, it takes time to give a corresponding row address, which results in a relatively low speed operation.

By the way, the AFM 200 is accessed at the same address as the address pattern applied to the device. This address is generally a random address generation depending on the test pattern. Therefore, when the DRAM element is used, the row address is accessed each time, and the operation is slow. As a result, the conventional D
In the configuration using RAM, the number of interleave stages increases. On the other hand, the equivalent memory capacity of the AFM is only the memory capacity for one interleave stage. This means, for example,
The equivalent memory capacity is the same in the case of four interleaves and the case of eight interleaves. For this reason, it is desirable to reduce the number of interleave stages as much as possible in terms of circuit scale, cost, power consumption, and installation space.

Next, an example of high-speed data storage operation in the interleaved configuration is shown in FIG. This drawing is a configuration example and a timing chart in the case of using a memory element having a difference of twice the operation cycle and configuring interleaving to operate at the same high speed. Here, each memory forming the interleave is called a bank, and when the number of interleaves is 8, each memory is numbered as banks # 1- # 8. For reading the stored data, the data obtained by OR-adding the data of the same address in all banks is used as fail address information. From this, it can be seen that if a memory element operating at twice the low speed is used, the number of interleaved stages will be doubled, and the number of peripheral circuits and memories used will also be doubled.

Next, FIG. 6 shows an example of two types of operation timing when the DRAM is used in read modify write. The first form is,
Normal with row and column addresses set
The second mode is a high-speed page mode mode of operation in which the same row address is selected and the column / address side is changed. Comparing the operation cycle times in these two operations, it can be seen that the high speed page mode operation is capable of approximately twice as high speed operation. Usually, the difference in this operation cycle is a large difference of about 2 to 3 times.

[0010]

As described above, since the addresses are randomly supplied, it is necessary to use the low speed normal mode operation mode when using the DRAM. As a result, the number of interleave steps is more than doubled, which is a problem in terms of circuit scale, mounting space, and cost. Here, an ALPG (algorithmic pattern generator) built in the pattern generator 320.
Is generated by the arithmetic means so as to generate a test pattern dedicated to the memory. Further, the address pattern for the MUT test is a well-known test pattern (for example, PING PONG, GALL
OPING, MSCAN, CHECKER BOARD, ROW BAR, COLUMN BAR, A
DDRESS COMPLEMENT, STRIPE) is used. That is, A
The address pattern generated by the LPG is a random address pattern which is random but has regularity. Generation of a random address pattern having this regularity is shown in FIG. The pattern form of serial access shown in FIG. 5A, or the pattern of alternately accessing the address incremented by +1 from the minimum value and decremented by -1 from the maximum value of the address value shown in FIG. 5B 5C, and the pattern form of an interference system in which the same address shown in FIG. 5C is accessed many times. Often, these always access the same row address.

Therefore, the problem to be solved by the present invention is that the address generated by the pattern generator 320 is a random or linear address pattern generation having regularity, and the DRAM is operated in a high speed page mode. In order to reduce the number of interleaved stages of the memory used in the failure analysis memory (AFM), fail storage is performed and a control means corresponding thereto is provided.

[0012]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, a plurality of predetermined interleaved DRAMs 160 for storing fail addresses are provided, and a small capacity temporary storage is provided in front of each DRAM 160. Buffer memory means is provided by inserting, and storage control to each temporary buffer memory means is performed by controlling a fail address 321adr where the row address 121row of the input fail address 321adr is the same.
Is provided in the corresponding temporary buffer memory means, the fail address 321 adr stored in the temporary buffer memory means is read out, and the DRAM 160 is read.
Is a constituent means provided with a control means for writing in the high speed write mode.

Secondly, in order to solve the above problems, in the configuration of the present invention, the DRAM 16 for storing the fail address is provided.
0 is provided in a predetermined number of interleaved stages, and each DRAM 1
A small-capacity temporary buffer memory means (for example, the FIFO memory 130) is provided in front of 60, and storage control to each temporary buffer memory means is performed firstly. In other interleave stages, row address comparison is inconsistent or empty. And if its temporary buffer memory means is empty,
Thereafter, row address comparison is started at this row address 121row, a fail address storage control signal is supplied to the corresponding temporary buffer memory means, counting of the number of buffers of the temporary buffer memory means is started, and secondly, the previous row address 121row. And the row address 121row of the input fail address 321adr match, the fail address storage control signal is supplied to the corresponding temporary buffer memory means to count the number of buffers of the temporary buffer memory means, and thirdly, the temporary buffer of its own. When the memory means reaches a stage just before the overflow, a distribution storing control means for the temporary buffer memory means for transitioning to the row address non-comparison state and performing the first, second, and third operations is provided. Fail address 321 stored in
A control means for reading adr and writing the DRAM 160 in the high-speed write mode is provided.

Thirdly, in order to solve the above problems, in the configuration of the present invention, the DRAM 16 for storing the fail address is provided.
0 is provided in a predetermined number of interleaved stages, and each DRAM 16
A small-capacity FIFO memory 130 is provided in front of 0, and the storage control in each FIFO memory 130 is as follows.
If the row address comparison of the other interleave stage is inconsistent or empty, and if its own FIFO memory 130 is empty, this row address 121row is stored in the address register 171, and row address comparison is started thereafter, and the corresponding FIFO memory is started. A fail address storage control signal (fail storage signal 179wck, page flag signal 178pag) is supplied to the buffer 130, and the buffer counter 174 starts counting the number of buffers of the FIFO memory 130.
When a match between the row address 121row previously stored in the address register 171 and the row address 121row of the input fail address 321adr is detected, a fail address storage control signal is supplied to the corresponding FIFO memory 130 to cause the FIFO memory 130 to store data. The number of buffers is counted by the buffer counter 174, and thirdly, by repeatedly receiving the input fail address 321adr of the matching row address 121row and detecting the stage before the overflow of the own FIFO memory 130, the row address non-comparison state is set. After the transition, the subsequent capture is stopped, the storage control is transferred to the next empty-state interleave stage, and when the number of interleave stages has reached one cycle, the suspended state transits to the empty state and waits,
FIFO memory 13 having the first, second, and third operations described above
A distribution storage control means for 0 (for example, a fail storage signal generation section 170 and a memory control section 140) is provided, and F
Fail address 32 stored in IFO memory 130
A memory control unit 1 that reads 1 adr and writes the DRAM 160 in a high-speed write mode (for example, high-speed page mode operation or hyper page mode operation)
40 is provided. Here, as the temporary buffer memory means, there is a means for realizing a first-in first-out temporary buffer in the FIFO memory 130 or the register file. As a result, when the device under test MUT fails, the DR in the fail analysis memory 200 that stores the corresponding fail address 321adr information.
The AM can be operated in the high-speed page mode, and the number of interleave stages can be reduced.

As the memory control section 140, the F
In order to control the fetching of the fail address 321adr from the IFO memory 130 and the write control to the DRAM 160, the fail storing signal 179wck1 from the fail storing signal generator 170 is received, and the fail storing operation is activated in the DRAM 160, and the FIFO memory 130 is activated. The fail address 321 adr stored in the FIFO memory 130 is counted to obtain the number of times of reading, and the fail address 321 adr buffer-stored in the FIFO memory 130 is sequentially read, and the DRAM 16
There is a configuration means for sequentially writing the fail address information in 0 in the high speed write mode (for example, high speed page mode operation or hyper page mode operation).

A DRAM for storing a fail address
A plurality of predetermined interleaved stages 160 are provided for each DRAM
A small-capacity FIFO memory 130 is inserted in front of 160, and there is a specific configuration means including memory control units 1401 to 140n and fail storage signal generation units 1701 to 170n.

Fail storage signal generators 1701-170n
Is a pair of corresponding bank memory units 1101 to 110n, has a plurality of interleave stages, receives the row address 121row selected by the address selection unit 120, and the fail information 341fl from the logical comparator 340, 1, the other interleave stage has a row address comparison mismatch or is in an empty state, and therefore, its own buffer counter 174
Is empty, the new row address 121row is stored in the address register 171, the row address comparison is started thereafter, the number of buffers is counted by the stage detection buffer counter 174 before the overflow, and the corresponding F
Fail address storage control signal to IFO memory 130 Fail storage signal 179wck, page flag signal 178pag
Secondly, when a match between the comparison row address 121row previously stored in the address register 171 and the input fail address 321adr is detected, the fail address storage control signal fail storage in the corresponding FIFO memory 130 is performed. The signal 179wck and the page flag signal 178pag are supplied, the buffer counter 174 is counted, and thirdly, the input fail address 321adr of the matching row address 121row is repeatedly received, and the buffer counter 174 exceeds the predetermined count value (the step before the FIFO overflow). ) Is detected, the state is changed to the stop state, the subsequent capture is stopped, the storage control is transferred to the next interleave stage in the empty state, and the transition from the stop state to the empty state is made when the number of interleave stages has reached one cycle. In order to wait and cycle through the number of interleaved stages, Address 121row
If no match is found during the comparison and use with the bank counter 170c for counting up the circulating position and instructing the empty state bank memory unit 110 to be stored next, NO.
There is a configuration means for providing the R gate 170b and the decoder 170d.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the address from the pattern generator 320 is checked, and the bank memory unit 11 of the interleave stage where the row address of the storage DRAM 160 is the same.
By controlling the fail information to be supplied and stored in 0, and storing DRAM 160 as a control means for writing in the high speed page mode operation (or hyper page mode operation) in which the same row address is written at high speed, In addition, the write cycle of the DRAM is made faster, which reduces the number of interleaved stages. Here, as the number N of interleaved steps, 20 steps, for example, 20 steps are provided so that a regular random address generated by the pattern generator 320 can be captured.

In FIG. 1, a DRAM is used in the memory section,
The block diagram of AFM200 of this invention is shown. This configuration has an address selection unit 120 and bank memory units 1101-11.
0n and the fail storage signal generator 170. The address selection unit 120 receives the fail address 321adr from the pattern generator 320, receives a setting condition from the outside, and generates a regular random address as shown in FIG. The row address 121row is selectively allocated and output so as to be increased. The column address 122adr is the remaining address line. These are stored in a plurality of bank memory units 1101 to 11
Supply to 0n. The row address 121row is also supplied to the fail storage signal generator 170. The row / column division here means that the DRAM 160 of each bank is allocated so as to improve the hit rate at the same row address in a short period of the fail address generation.

As shown in FIG. 1, the internal structure of one bank memory unit 1101 comprises a FIFO memory 1301, an address selector MUX1351, a memory control unit 1401 and a DRAM 1601. The operation for one bank memory unit 1101 will be described below.

The FIFO memory 1301 is a memory as a small capacity "temporary buffer means" for temporarily holding and storing fail data of the same row address. The row address 121row, the column address 122adr,
When the fail information 341fl from the logical comparator 340 is received and the corresponding fail store signal 179wck from the fail store signal generator 1701 is present, it is stored in this temporary memory. With this FIFO memory 1301, D
The RAM 1601 secures a waiting time during the refresh operation and also enables continuous storage of fail data at the same row address.

The DRAM 1601 is composed of a plurality of D's each having a desired large capacity.
It consists of a RAM memory element. The address line supplied to the DRAM receives the row address 131row and the column address 132clm from the FIFO memory 1301, and the address selector MUX1351 receives an address signal obtained by multiplexing both row / column address signals.

The memory control unit 1401 has a FIF
Control of taking out fail data from the O memory 1301 and high-speed page writing control to the DRAM 1601 are performed. However, the first first write operation is write control for accessing the row address. FIG. 7 shows a specific internal configuration example of this memory control unit 1401.
Shown in This internal configuration is the fail storage trigger 141.
A refresh trigger 142, a refresh timer 143, an oscillator 144, a sequence controller 145, a program counter 146, a sequence memory 147, a timing generation memory 148, and others.

The fail store trigger 141 receives the fail store signal 179wck1 and activates the fail store operation to the DRAM 1601. This fail storage trigger 141
FIG. 8 shows an example of this internal detailed circuit configuration.
This internal configuration includes a FIFO storage counter 141a, a D
RAM storage counter 141b and counter comparator 141
c and others. The operation is the fail store signal 17
In response to 9wck1, the FIFO storage counter 141a counts up, and when the counter comparator 141c does not match the value of the DRAM storage counter 141b, the leading edge differential signal of this non-coincidence signal is used as the fail storage trigger signal 141trg.
Is supplied to the sequence controller 145 shown in FIG. This activates the fail storage operation to the DRAM 1601. The other DRAM storage counter 141
b receives the one-address storage signal 141rck1 from the sequence memory 147 and counts up. Where F
The IFO storage counter 141 a includes the timing generator 31.
Since the DRAM storage counter 141b operates with the reference system operation clock output from 0, and the DRAM storage counter 141b operates with the clock from the oscillator 144 in the AFM, the mismatch detection output of the counter comparator 141c is an asynchronous signal. Therefore, the fail storage trigger signal 141trg is synchronized with the FF for synchronization and output.

The DRAM storage counter 141b is for detecting the presence / absence of data during continuous writing in the high speed page mode. Therefore, firstly, the DRAM storage counter 141b
If the count-up value and the counter comparator 141c do not match, the data still exists in the FIFO, so that the next fail-storing trigger signal 141trg is continuously output to the DRAM 1601 in the high-speed page mode. A continuous fail storage operation will be activated.
Secondly, when the count-up value of the DRAM storage counter 141b matches the counter comparator 141c, there is no data in the FIFO, so the fail storage trigger signal 141trg output is prohibited and the fail data storage operation is temporarily stopped. Stop.

The refresh trigger 142 shown in FIG.
The refresh operation interrupt is for activation, and is activated by a refresh request signal from the refresh timer 143. At the time of startup, if a fail storing operation is in progress, a wait flag is output so that the fail storing operation and the refresh operation do not conflict with each other. The refresh timer 143 divides the time by the clock from the oscillator 144, and refresh trigger 1 at every predetermined refresh time.
A refresh request signal is generated at 42.

The sequence controller 145, program counter 146, sequence memory 147, and timing generation memory 148 shown in FIG. 7 generate various predetermined timing signals for controlling the DRAM 1601. That is, the sequence control unit 145 receives the activation signal from the fail store trigger 141 or the refresh trigger 142, starts the operation of the program counter 146, and outputs various control signals from the sequence memory 147 and the timing generation memory 148 by the output address pointer. Occurs. A part of the output signal from the sequence memory 147 is returned to the sequence control unit 145, and the operation of the program counter 146 is incremented / loaded / held by the data in the sequence memory 147 to perform a predetermined sequence control. Also,
The timing generation memory 148 generates a DRAM write control signal, and stores timing data for performing a refresh operation and a fail storage operation in advance. The timing generation memory 148 is set by the program counter 146 as shown in FIG. 9, for example. A predetermined timing signal is output.

FIG. 9 shows timing data and waveforms generated during the fail storage operation (read modify write operation). This is an example of when the program counter 146 simply increments. When the page flag signal 178pag is "H" and input to the sequence controller 145, timing data for high speed page mode or hyper page mode operation is output from the timing memory, and the DRAM operates in high speed page mode or hyper page mode. I do. In high-speed page mode or hyper page mode operation, each time fail data for one fail address (column address) is stored, one address storage signal 141rck is output and the fail data is read from the FIFO memory.

Next, the fail storage signal generator 170 shown in FIG. 1 will be described. The fail storage signal generator 170
In response to the row address 121row signal for the DRAM 160 from the address selection unit 120, the multi-bank memory unit 1
For 101 to 110n, the former bank memory unit 1101
FI of the same row address 121row stored by 110n
A storage control operation is performed on the FO memories 1301 to 130n. That is, first, in the case of an existing row address that matches this row address, a storage control signal (page flag signal 178pag and fail storage signal 179wck) is generated in the matched bank memory unit 110n. Secondly, in the case of a new row address, a storage control signal is generated to the bank memory unit 110n in the next unused state, and the new row address is stored for the next comparison. Of course, there is no operation during the non-fail cycle. The row address mentioned here refers to the row address of the storage DRAM 160 in the bank memory unit 110. The page flag is also generated in the matched bank when the row addresses match.

FIG. 10 shows a specific internal configuration example of the fail storage signal generator 170. This includes a plurality of fail storage signal generators 1701 to 170n and a NOR gate 17.
0b, the bank counter 170c, and the decoder 170d.
And A plurality of fail storage signal generators 1701-1
70n is paired with a plurality of bank memory units 1101 to 110n. The internal configuration of the fail storage signal generator 1701 of bank # 1 is the address register 1711.
An address comparison unit 1721, a comparison flag 1731,
It consists of a buffer counter 1741 and others.

The operation of the fail storage signal generator 170 will be described with reference to the flowchart of FIG. Upon the start of the test, the fail information 341fl from the logical comparator 340 is received, and the address register 1711 for the bank # 1 initially selected by the decoder 170d operates. The row address 121row selected by the address selector 120 is fetched and the comparison flag 1731 is set to enable the subsequent row address comparison, and the fail storage signal 179wck1 is output to the FIFO memory 1301 of the corresponding bank # 1. Further, the buffer counter 1741 for the stage monitoring before the FIFO overflow is counted up, and the bank counter 170c for enabling fetching of different row address in the next fail storage signal generating section 1702 is counted up.

When the next fail cycle occurs, the row address is compared in the address register 1711 of bank # 1, and if they match, the buffer counter 1741 is counted up, and the fail storage signal 179wck1 and page flag are stored in the FIFO memory 1301 of bank # 1. The signal 178pag1 is output. If they do not match, the comparison flag 1732 of bank # 2 is set, and the same operation as in bank # 1 is performed. That is, the bank counter 170c and the buffer counter 1742 of the next bank are counted up, the row address comparison of the bank # 2 is started, and the FIFO memory 130 of the bank # 2 is started.
The fail storage signal 179wck2 is output to the second. After that, the same operation is performed, and different row addresses up to n points are simultaneously monitored by the fail storage signal generators 1701 to 170n.
FIFO memories 1301 to 13 of corresponding row addresses
It will be stored in 0n.

The buffer counter 1741 keeps the FIF under various conditions such as the number of interleave stages to be configured and the storage cycle time in the DRAM memory in the high speed page mode.
This is for monitoring so as not to exceed the O buffer full, and a value lower than the capacity value of the FIFO is normally used as the buffer full value. When it detects that the buffer is full, the subsequent comparison with the row address 121row is stopped until the number of interleave stages reaches one cycle, and the storage operation is shifted to the next interleave stage number of the empty bank memory unit 110n. The bank counter 170c has a NOR gate 170b.
This counts up only when the row address comparisons of all banks (limited to the bank that is performing row address comparison) are all inconsistent, and serves as a pointer that points to the next empty bank. When the final bank is reached, patrol is performed. . Note that the configuration example of FIG. 10 is an example of a circuit in which the bank counter 170c counts up and sequentially points to the next empty bank, but if desired, the empty bank may be directly encoded instead of the NOR gate 170b. Is also good.
A bank for which comparison is prohibited because the buffer counter 174n is full is also treated in the same manner as the empty bank state after one round. That is, when all the banks do not match as designated by the pointer of the bank counter 170c, the address is again stored in the address register 171n of the bank and the row address comparison is started. By sequentially repeating this, the fail address of the same row address is selectively stored in the FIFO of each bank. Note that the example of FIG. 10 is an example of a circuit that detects buffer fullness by the buffer counter 174n, but if desired, a write completion signal to the DRAM 160n from the corresponding memory control unit 140n is received, and this forces itself. You may make it use by making a transition to an empty bank state.

By the above operation, the FIFO memory 13
The address and page flag of the same row address are stored in 01. From now on, the fail data storage operation from the FIFO memory 1301 to the DRAM 1601 can be written in the high speed page mode (or hyper page mode operation) because the same row address is used. Therefore, the operation of storing fail data in the DRAM 1601 can be performed at high speed. As a result, the number of interleaved stages can be reduced, and the cost of the reduced stage number circuit can be reduced.

Regarding the above operation, each F from the start of the test
FIG. 12 shows an example of address data stored in the IFO memories 1301 to 1306. Here, the pattern generator 3
It is assumed that the random address signals generated from 20 are set as fail cycles and all are considered as fail conditions and are taken into the FIFO memory. Further, it is assumed that the fail address 321adr from the pattern generator 320 is 16 bits, and the lower 12 bits of this are allocated as the column address of the memory section 260 and the upper 4 bits are allocated as the row address. By the above operation, the FIFO memories 1301 to 1306 of each bank are
This shows a state in which addresses of the same row address value are being stored.

That is, first, the bank counter 170c shown in FIG. 10 points to bank # 1 as an initial value and all the comparison flags are disabled, so that the row address is
Address # 0000 of # 0 is FIFO memory 1301 of bank # 1
It is stored in. Next, the address where the row address is #F #FFF
When F comes, the row address does not match in any bank, so it is stored in the FIFO memory 1302 of bank # 2. When the address # 0001 comes next, a row address match occurs in the bank # 1, so the FIFO memory 13 of the bank # 1
It is stored in 02. As a result of being stored in this way, addresses # 0000, # 0001, # 0002, # 0003 are stored in bank # 1.
Stored in the FIFO memory 1301 of #FFFF, FFFE, FF
FD and FFFC are stored in the FIFO memory 1302 of bank # 2. The storage operation is similarly performed for the other banks # 3 to # 6. As a result, the same row address value is stored in each of the FIFO memories 1303 to 1306. As a result, each of the DRAMs 1601 to 1606 can be stored at high speed in the high speed page mode (or hyper page mode operation).

In the description of the above embodiment, the FIFO memory 130 is used in the bank memory unit 110, but if desired, another temporary buffer for realizing the first-in first-out function equivalent to that of the FIFO memory is provided. It may be realized by means. For example, register file, small capacity S
There is a configuration including a RAM and an address counter.

In the description of the above embodiment, the write operation of the DRAM is described as the read modify write operation. However, the write per bit mode having the write control function for each I / O data pin of the DRAM is described. Of D
RAM may be used. In this case, the time for reading can be further shortened.

[0040]

According to the present invention, the following effects can be obtained from the contents described above. In the present invention, the address from the pattern generator 320 is used as the fail storage signal generator 17
0 is checked, and the FI of the bank memory unit 110 is set so that the same row address is selected from the plurality of interleave stages.
An effect of selectively storing and controlling the FO memory 130 can be obtained. As a result, the same row address is buffered in the FIFO memory in each of the bank memory units 1101 to 110n, and the storage operation in the DRAM 160 can be performed in the high speed write mode in which the same row address is used.
As a result, the write cycle of the DRAM can be substantially speeded up, and the effect of reducing the number of interleaved stages of the bank memory units 1101 to 110n can be obtained. Further, the circuit scale is reduced, the size and cost can be reduced, and the economical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a failure analysis memory (AFM) 200 using a DRAM for a memory unit according to the present invention.

FIG. 2 is an internal configuration diagram of a failure analysis memory 200.

FIG. 3 is a basic configuration diagram of the entire memory test apparatus.

FIG. 4 is an example of a timing chart when a high speed operation is performed by interleaving using a plurality of memories.

FIG. 5 is an example of three types of address pattern generation modes applied during a MUT test.

FIG. 6 is a timing diagram example of a read-modify-write operation during random access and during serial access.

FIG. 7 is an internal configuration diagram of a memory control unit 1401 according to the present invention.

FIG. 8 is an example of a circuit configuration diagram inside the fail storage trigger 141 of the present invention.

FIG. 9 is a waveform chart of timing data and a generated timing data during a fail storing operation according to the present invention.

FIG. 10 is a diagram showing a fail storage signal generator 170 of the present invention.
FIG.

FIG. 11 is a diagram showing a fail storage signal generator 170 of the present invention.
FIG. 7 is an operation flowchart diagram of

FIG. 12 is an example of address data stored in each of the FIFO memories 1301-1306 from the start of the test according to the present invention.

[Explanation of symbols]

 11 MUT (memory under test) 1101, 110n bank memory section 120, 220 address selection section 121row, 131row row address 122adr, 132clm column address 1301 FIFO memory MUX1351 address selector 1401, 240 memory control section 141 fail storage trigger 141rck1 1 address storage signal 141trg Fail storage trigger signal 141a FIFO storage counter 141b DRAM storage counter 141c Counter comparator 142 Refresh trigger 143 Refresh timer 144 Oscillator 145 Sequence control unit 146 Program counter 147 Sequence memory 148 Timing generation memory 1601, 160n DRAM 1701, 170n Fail storage signal generation Part 170b NOR gate 170c Link counter 1711, 171n address register 1721 address comparison unit 1731 comparison flag 1741 buffer counter 178pag page flag signal 179wck fail storage signal 200 fail analysis memory 260 memory unit 310 timing generator 320 pattern generator 321adr fail address 330 waveform shaper 340 logical comparison Vessel 341fl Fail information

Claims (7)

[Claims] 1. A fail analysis memory (200) for storing a fail address (321adr) of a device under test (MUT), wherein a plurality of predetermined interleaved DRAMs (160) for storing fail addresses are provided, and each DRAM (160). A small-capacity temporary buffer memory means is provided in front of, and storage control to each of the temporary buffer memory means is such that the row address (121row) given to the DRAM (160) of the input fail address (321adr) is the same fail. Storage control means for storing the address (321adr) in the corresponding temporary buffer memory means is provided, the fail address (321adr) stored in the temporary buffer memory means is read, and the DRAM (160) is written in the high-speed write mode. To provide the control means to The semiconductor memory test apparatus and symptoms. 2. A fail analysis memory (200) for storing a fail address (321adr) of a device under test (MUT), wherein a plurality of predetermined interleaved DRAMs (160) for storing fail addresses are provided, and each DRAM (160). Is provided by inserting a small-capacity temporary buffer memory means, and the storage control in each temporary buffer memory means is
If the row address comparisons of the other interleave stages do not match and their own temporary buffer memory means are empty,
Thereafter, row address comparison is started at this row address (121row), a fail address storage control signal is supplied to the corresponding temporary buffer memory means, counting of the number of buffers in the temporary buffer memory means is started, and secondly, the previous row Address (121row) and input fail address (32
When the row address (121row) of (1adr) matches, the fail address storage control signal is supplied to the corresponding temporary buffer memory means, the number of buffers of the temporary buffer memory means is counted, and thirdly, its own temporary buffer memory When the means reaches a stage just before the overflow, a distribution storing control means is provided to the temporary buffer memory means for making a transition to the row address non-comparison state and performing the first, second and third operations, and the temporary buffer memory is provided. A semiconductor memory test apparatus comprising the control means for reading the fail address (321adr) stored in the means and writing the DRAM (160) in the high-speed write mode, and comprising the above. 3. A fail analysis memory (200) for storing a fail address (321adr) of a device under test (MUT), wherein a plurality of DRAMs (160) for storing fail addresses are provided in a predetermined number of interleaved stages, and each DRAM (160) A small-capacity FIFO memory (130) is provided in front, and storage control to each of the FIFO memories (130) is performed by the first control.
When the row address comparison of the other interleave stage does not match and the FIFO memory (130) of its own is empty, this row address (121row) is stored in the address register (171) and the row address comparison is started thereafter. ,
The fail address storage control signal is supplied to the corresponding FIFO memory (130) to start counting the number of buffers of the FIFO memory (130), and secondly, the row address (121row) previously stored in the address register (171).
When a match between the input fail address (321adr) and the row address (121row) is detected, the corresponding F
The fail address storage control signal is supplied to the IFO memory (130), the number of buffers of the FIFO memory (130) is counted, and thirdly, the input fail address (321adr) of the matching row address (121row) is repeatedly received, and Of the FIFO memory (130) is detected, a transition is made to the row address non-comparison state, the storage control is shifted to the next empty state interleave stage, and the first, second and third operations are performed. A distribution storage control means for the FIFO memory (130) is provided, the fail address (321adr) stored in the FIFO memory (130) is read out, and the DRAM (160) is read.
A semiconductor memory test apparatus having a memory control section (140) for writing data in a high-speed write mode, and having the above. 4. The memory control unit (140) stores the fail address (32) from the FIFO memory (130).
1 adr) take-out control and write control to the DRAM (160).
0) receives the fail store signal (179wck1), activates the fail store operation to the DRAM (160), and sends the fail address (32) to the FIFO memory (130).
1adr) storage operation, FIFO memory (130)
Address stored in the buffer (321adr)
4. The method according to claim 3, further comprising the steps of: sequentially reading the data, writing the DRAM (160) in a high-speed write mode, and providing activation control means for refreshing the DRAM (160) at predetermined time intervals. Semiconductor memory test equipment. 5. A fail analysis memory (200) for storing a fail address (321adr) of a device under test (MUT), wherein a plurality of DRAMs (160) for storing fail addresses are provided in a predetermined number of interleaved stages, and each DRAM (160) 4. The semiconductor memory testing device according to claim 3, wherein a small capacity FIFO memory (130) is provided in front of the memory control unit (1401 to 140n) and a fail storage signal generation unit (1701 to 170n). 6. A fail storage signal generator (1701-1)
70n) is paired with a corresponding bank memory unit (1101 to 110n) and has a plurality of interleaved stages, and an address selection unit (1
20), the row address (121row) selected in step 20) and the fail information (341fl) from the logical comparator (340) are received. (174)
Is empty, this new row address (121ro
w) is stored in the address register (171), row address comparison is started thereafter, the buffer counter (174) starts counting the number of buffers, and the corresponding FIFO memory (1
30) is supplied with a fail address storage control signal (fail store signal 179wck, page flag signal 178pag), and secondly, a comparison row address (121row) previously stored in the address register (171) and an input fail address (121row). 321adr) When a match between the two is detected, a fail address storage control signal (fail storage signal 179wck, page flag signal 178pag) to the corresponding FIFO memory (130) is supplied, the buffer counter (174) is counted, and 3 to the matching row address (1
21 row) input fail address (321adr) is received multiple times, the buffer counter (174) for stage detection before overflow detects that the predetermined count value has been exceeded, transitions to the suspended state, and suspends subsequent fetching. , When the number of interleaved stages has reached one cycle, it transits from the aborted state to the empty state and waits, and in order to cycle through the number of interleaved stages, if there is no match during row comparison with the row address (121row), count up the cyclic position. A bank counter (170c), a NOR gate (170b), and a decoder (170d) for indicating the next empty state bank memory section (110) to be stored are provided, and the above is provided. 5. The semiconductor memory testing device according to item 5. 7. The semiconductor memory testing apparatus according to claim 1, wherein the temporary buffer memory means realizes a first-in first-out temporary buffer circuit by a FIFO memory (130) or a register file.