KR940005770B1 - Data access time controller - Google Patents

Abstract

The method for controlling extended data access time and an apparatus therefor are disclosed including a main memory having at least 2 bank memories; at least 2 SIMMs (Single In-Line Memory Modules) installed in each bank memory; an address line, a row address strobe signal and a write enable signal commonly connected to the bank memories; and a column address strobe signal for selecting each bank memory, thereby shortening the access time of a main memory system.

Description

Extended data access time control method and apparatus

1 is a read cycle in the conventional fast page mode.

2 is a schematic diagram of a bank memory of the present invention.

3 is a schematic diagram of a SIMM module of the present invention.

4 is a row and column address diagram of the present invention.

5 is a timing cycle in the extended fast page mode of the present invention.

* Explanation of symbols for main parts of the drawings

11 to 14: Bank memory 21: Address line

22: 31 ~ 34: SIMM module

41-44:

The present invention relates to a control method and apparatus for minimizing data access time of a main memory device, and more particularly, to a control method and apparatus for controlling an extended memory data access time in a fast page mode when using a DRAM module.

In order to access (Read or Write) a conventional Dynamic Random Access Memory (DRAM) module, a predetermined timing of control signals must be given.

Signals for accessing data include address lines, data lines, , And And control signals. Above all The signal is a row address strobe signal. Is a column address strobe signal.

To access the data, you need to assert the row address to the address line and at the same time After asserting, open the address line after a certain amount of time It is supposed to assert. In this case, if you try to access several bytes continuously, you need to perform the whole cycle several times, so the time required is long. The attempted solution to this problem was fast page mode.

This method can be used if the row addresses of the data that you want to continue to access are the same. With a long time The only way to access data is by using in this case Reducing the time required to assert the effect is especially effective for repetitive accesses such as Burst Reading or Burst Write.

A conventional read cycle of the fast page mode is shown in FIG.

In this case, we first put a hang address on the address line Assert (a). At this time, the address should be loaded in advance by the assert time t _ASR of the address c.

After a predetermined time (t _RAD ) of the address (c), the address line is opened to load the address, and then (b) will be asserted, with the times t _ASC , t _CAH , t _CAS ) _corrected . At this time, the valid data D ₁ is loaded on the data line e in accordance with the time t _CAC .

However, when the row address in the address (c) of the subsequent access matches the previous row address, without the need to assert (a) Opens with Asserted, just change the dress and immediately after the time t _CP . Asserting (b) makes it possible to read data (e) faster (d). This method can reduce the data access time if the row addresses match.

The waveform (d) is And (e) the waveform is the data out waveform.

Meanwhile, the write cycle It is understood that there is no significant difference from the above-described read cycle except that an additional signal is required, and the fast page mode of the write cycle can reduce the access time during a transaction such as burst write.

The conventional fast page mode is a fast access method when the main memory is composed of one single bank memory, but is not very effective in minimizing the access time when the plurality of bank memories are configured. Therefore, an extended access method is required according to the expanded bank memory.

For example, assuming that the same page (typically 4 KB) belongs to the same bank memory even if multiple extended bank memories are used, fast page mode may be the fastest method when considering a row address as a high address.

However, if the area of the same page is divided into multiple bank memories, the function of the fast page mode can be further extended. That is, multiple bank memories have the same row address If you choose a low bank memory, you can extend the functionality of the fast page mode.

The present invention was devised to improve the access time degradation caused by the conventional multiple bank memory configuration, and an object of the present invention is to strobe a row address to all bank memories simultaneously in a system having a plurality of bank memories. The present invention provides an extended memory data access time control method and apparatus for improving the access time of a row address by expanding the area covered by the row address by the number of bank memories by strobing the open address for each bank memory.

Technical means for achieving the above object of the present invention, the main memory consisting of at least two bank memories, at least two SIMM modules configured in each of the bank memory and the plurality of banks in common connection The address line And And selecting the plurality of bank memories, respectively. And a row address is strobe in all bank memories, and the open address is strobe separately for each bank memory.

Here, the plurality of SIMM modules are connected in common And addresses, each connected separately And preferably constitute a data line.

Meanwhile, all bank memories of main memory are simultaneously asserted to RAS. Simultaneous asserting means and each of the plurality of bank memories The CAS selection means selected by the < RTI ID = 0.0 > and < / RTI > WE byte selection means serving as a signal, common strobe means for strobe common to all bank memories, and open strobe means for strobe separately strobe means for each bank memory, in the extended fast page mode It is characterized by minimizing the access time of the hang address. When the read and write transaction of the memory first compares the row address (bits 23 to 14) of the address with the row address in the previous transaction, and if the two addresses match as a result of the comparison, Without having to assert It is effective to assert it.

Hereinafter, preferred embodiments of the present invention by referring to the accompanying drawings in detail as follows.

2 is an expanded bank memory diagram of the present invention.

Here, only four bank memories 11 to 14 are described as examples, but the expansion can be any number.

The first to fourth bank memories 11 to 14 are separated from each other and contiguous with each other without addressing.

The address line 21 connected to the first to fourth bank memories 11 to 14 uses a 32-bit address line. The memory module uses a single in-line memory module (SIMM) of 1M x 9 bits.

3 shows the configuration of the first to fourth SIMM modules 31 to 34 in the bank memory of the present invention.

In the second and third degrees 22 is commonly connected to the first to fourth bank memories 11 to 14 and the SIMM modules 31 to 34. The first bank memory 11 41 is connected to the second bank memory 12, 42 is in the third bank memory 13, 43 is in the fourth bank memory 14; 44 are respectively connected.

On the other hand, the first to fourth SIMM modules 31 to 34 40 are commonly connected. In the first to fourth bank memories 11 to 14, 50 are commonly connected to the first SIMM module 31. 51 is connected to the second SIMM module 32 52 to the third SIMM module 33 53 to the fourth SIMM module 34 54 are respectively connected.

In addition, DATA 60 is commonly connected to the first to fourth bank memories 11 to 14, DATA1 61 is connected to the first SIMM module 31, and the second SIMM module 32 is connected. DATA2 (62) is in the third SIMM module 33, 63, the fourth SIMM module 34 is connected to the DATA4 (64), respectively.

remind Is used to select the bank memory, Is used to select bytes during a write transaction.

3 illustrates the inside of the bank memory of FIG. 2.

In FIG. 3, when only 1M x 9-bit SIMM is used, the entire area is 16MB. At this time, if the address of the area is set from 0 _x 000000 to 0 _x FFFFFF (hexadecimal), the address of each bank memory 11 to 14 is set to be cycled in units of 1 word (Word: 4 bytes).

That is, the first bank memory 11: 0 _x × × × × × 0-0 _x × × × × × 3

Second bank memory 12: 0 _x × × × × × 4 to 0 _x × × × × × 7

Third bank memory 13: 0 _x × × × × × 8-0 _x × × × × × B

Fourth Bank Memory 14: 0 _x × × × × × C-0 _x × × × × × F

Here, 0 represents a hexadecimal number and × represents Don't Care.

remind When 22 is separately asserted for each bank memory, as shown in Fig. 4A, the row address indicates ADDR [21 ~ 12], the open address indicates ADDR [11 ~ 2], and one row address shows 4KB. Select the memory area, but above If 22 is commonly connected to the first to fourth bank memories 11 to 14, as shown in Fig. 4B, the hang address indicates ADDR [23-14] and the open address indicates ADDR [13-4]. One row address selects 16 KB of memory, resulting in extended fast page mode.

5th degree The bank memory can be selected as the timing diagram of the extended fast page mode when the address is cycled. As shown in the timing chart above, all bank memories with (a) in common by having (b) independently (b) selects each bank memory.

That is (a) is asserted and said After (b) is asserted, valid data Di appears after t _CAC time of data out f. At this time, the valid data Di is accessed. The minimum access time here (c) After t _ACC , after t _OFF (d) is asserted and again accesses valid data D ₁ after t _CAC .

The average transaction time is reduced when this access process is compared with fast page mode. The reason is that the memory size selected by one row address e is quadrupled. That is, when one transaction (Read or Write) is required, the row address (bits 23 to 14) among the addresses is first compared with the row address in the previous transaction.

Here again if the two addresses coincide with each other Immediately above without needing to assert (a) Will assert, where (b) According to bits 2 and 3 of the address bits in (i = 0, 1, 2, 3) (b) is asserted.

That is, if bits [3 ~ 2] of address bit are øø is asserted to select the bank memory, and if bits [3 ~ 2] of the address bit are 01, Is equal to 10 Is equal to 11 These are each asserted so that each corresponding bank memory selection is made. On the other hand, during a write operation, if the memory size is in bytes, that byte of the corresponding byte (ie By asserting, byte selection is made. At this time, if the row address does not match the previous transaction hang address, You must assert (a).

As described in detail above, the present invention significantly shortens the access time of the main memory system and has an advantageous effect of allowing the commercially available fast page mode to be extended to any extent.

Claims (4)

A main memory composed of at least two bank memories, a SIMM module composed of at least two within each bank memory, an address line commonly connected to the plurality of bank memories, And And selecting the plurality of bank memories, respectively. And a row address is strobe to all bank memories, and the open address is strobe to be strobe separately for each bank memory. The method of claim 1, wherein the plurality of SIMM modules are connected in common Wow And addresses, each connected separately And data. All bank memories in main memory Asserted with at the same time Simultaneous asserting means and each of the plurality of bank memories Selected with The selection means, the upper address means for holding the address indicated by the row address and the open address in the address to be accessed toward the higher address according to the number of bank memories, and the byte selection in the write transaction of the memory Signaled A byte selecting means, a common strobe means for strobeing common to all bank memories, and a separate strobe means for strobing separately for each bank memory; An extended memory data access time control method, characterized in that to minimize the access time. 4. The method of claim 3, wherein in a read and write transaction of memory, a row address (bits 23 to 14) of an address is first compared with a row address of a previous transaction. Immediately without having to assert And asserted.