JP4285816B2 - PATTERN GENERATOR, PATTERN GENERATION METHOD, AND TEST DEVICE - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern generator, a pattern generation method, and a test apparatus used in a test apparatus that tests an electrical component.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a test apparatus used for testing an electrical component such as a semiconductor memory includes a pattern generator that generates a test pattern for use in testing the electrical component. The pattern generator includes an SRAM (Static Random Access Memory) for storing the test pattern, and a large-capacity DRAM (Dynamic Random Access Memory) when the capacity of the SRAM is insufficient.
When a DRAM is used to store a test pattern in a pattern generator, a refresh operation is required every certain time, and it takes time to access an address having a different ROW address. In order to avoid inconvenience, a cache memory is provided in the subsequent stage of the DRAM, and a test pattern is generated via the cache memory.
[0003]
FIG. 1 is a diagram showing a configuration of a conventional pattern generator for storing a test pattern in an SRAM. The pattern generator 99 includes a vector memory 101, a read controller 102, vector memory banks 103 and 104, a vector instruction multiplexer (MUX) 105, a sequence controller 100 having an address expander 106, and an SRAM. And a pattern signal generation unit 108 having a configured pattern memory.
[0004]
The vector memory 101 stores vector instructions (pattern programs) that define the order of test patterns to be generated. The read control unit 102 reads a vector instruction stored in the vector memory 101 and stores it in the vector memory bank 103 or the vector memory 104. The vector instruction multiplexer 105 selects a vector instruction stored in the vector memory bank 103 or the vector memory 104 and transfers it to the address expansion unit 106. The address expansion unit 106 expands the address of the vector instruction and transfers the address signal 107 obtained by the address expansion to the pattern signal generation unit 108. The pattern signal generation unit 108 extracts the test pattern signal stored in the pattern memory corresponding to the address signal 107 and generates the test pattern signal as the pattern signal 109 for testing the electrical component.
[0005]
FIG. 2 is a diagram illustrating an example of a pattern program stored in the vector memory 101. In the pattern program, “GOSUB A” outputs the address of the instruction as an address signal, and then proceeds to a subroutine (instruction stored at addresses # 11 to 15) indicated by label A (A: in the figure). It is an instruction to jump. “RETURN” is an instruction that means that the subroutine has ended. After outputting the address signal of the address of the instruction, the line next to “GOSUB” that is the jump source to the subroutine, that is, the address of “GOSUB” This is an instruction to return to the address obtained by adding 1 to. “REPEAT n (n is an arbitrary integer)” is an instruction for repeatedly generating an address signal corresponding to the address n times. “NEXT” is an instruction that outputs the current address as an address signal and advances the address, that is, adds 1 to the address. “STOP” is an instruction to end the generation of the test pattern. By combining these instructions, it is possible to define the order in which test patterns for testing electrical components are generated.
[0006]
FIG. 3 is a diagram illustrating an example of a compressed pattern program stored in the vector memory 101. Since the actual pattern program is very long, the capacity of the vector memory 101 must be increased in order to store all instructions. Therefore, in order to reduce the capacity required for the vector memory 101, the pattern program shown in FIG. 2 is compressed and stored in the vector memory 101. Specifically, the “NEXT” instruction in the pattern program is omitted, and the address of each instruction is added to the other instructions to be compressed and stored in the vector memory 101.
[0007]
In FIG. 3, “GOSUB A # 0 # 11” indicates an instruction to output the address signal # 0 and then output the address signal # 11. “REPEAT 3 # 3” indicates an instruction for outputting the address signal # 3 three times repeatedly. Here, the “NEXT” instruction for outputting the address signal # 1 and the address signal # 2 is omitted between “GOSUB A” and “REPEAT 3”.
[0008]
FIG. 4 is a diagram showing test patterns stored in the pattern memory of the pattern signal generation unit 108. The pattern memory of the pattern signal generation unit 108 stores a plurality of test patterns PAT0, PAT1,. For example, PAT2 is stored at address # 2 of the pattern memory, and PATF is stored at address #F of the pattern memory. When the test pattern is stored in the pattern memory of the pattern signal generation unit 108, for example, the test patterns PAT0, PAT1,... Are stored in advance in an external storage device such as a hard disk (not shown), and externally stored when the pattern generator is activated. What is necessary is just to read from a memory | storage device and to store sequentially in address # 0, # 1, ....
[0009]
FIG. 5 is a diagram illustrating the operation of a conventional pattern generator. FIG. 5 shows the operation when the number of words (number of instructions) that can be stored in each of the vector memories 103 and 104 is three. In the pattern generator 99, the read control unit 102 performs an initialization process of reading a vector command from the vector memory 101 and writing it into the vector memory bank 103 before performing a test process for generating a test pattern.
[0010]
That is, the read control unit 102 takes out an instruction stored in the vector memory 101 in consideration of a sequence (order) and transfers the instruction to the vector memory bank 103. Since the address # 1 of the vector memory 101 is an instruction “GOSUB A # 0 # 11” and the instruction jumps to the label A, the read control unit 102 determines that the instruction “GOSUB A # 0 # 11” Next, the jump destination instruction “REPEAT2 # 13” is stored in the vector memory bank 103.
Then, the read control unit 102 stores the “RETURN # 15, # 1” instruction of the next address to be executed next in the vector memory bank 103 after the “REPEAT2 # 13” instruction. In this example, the initialization process is completed by writing an instruction to the vector memory bank 103 for the first three words of the pattern program.
[0011]
After this initialization process is completed, the test process is started. In this test process, the address expansion unit 106 expands the compressed instruction stored in the vector memory bank 103 by the initialization process and outputs an address signal 107. When the address expansion unit 106 expands the instruction stored in the vector memory bank 103 by the initialization process, first, # 0 is output as an address signal from the instruction “GOSUB A # 0, # 11”, and then # 11 is output. To do. Next, from the instruction “REPEAT2 # 13”, # 12 to # 13 are sequentially output as address signals, and # 13 is output again. Next, after outputting # 14 as an address signal from the instruction “RETURN # 15 # 1,” # 15 is output, and then # 1 is output.
The address signal 107 output from the address development unit 106 is supplied to a pattern generation unit 108 having a pattern memory constituted by an SRAM. The pattern generation unit 108 outputs a test pattern stored in the pattern memory based on the supplied address signal 107. This output test pattern is applied to the electrical component.
[0012]
In the test process, the vector instruction multiplexer 105 selectively supplies a compressed instruction to the address expansion unit 106 from the vector memory bank 103 or 104 in which the vector instruction has already been written. Specifically, after the generation of the test pattern based on the instruction stored in the vector memory bank 103 is completed, the instruction stored in the vector memory bank 104 is supplied to the address expansion unit 106.
[0013]
Further, in the test processing, while the test pattern is generated based on the instruction stored in the vector memory bank 103, the vector instruction to be executed next by the read control unit 102 is transferred from the vector memory 101 to the vector memory bank. 104. Next, after the generation of the test pattern based on the instruction stored in the vector memory bank 104 is completed, the vector instruction multiplexer 105 supplies the instruction stored in the vector memory bank 103 to the address expansion unit 106.
[0014]
While the test pattern is being generated based on the instruction stored in the vector memory bank 104, the read control unit 102 transfers the vector instruction to be executed next from the vector memory 101 to the vector memory bank 103. To do. Next, after the generation of the test pattern based on the instruction stored in the vector memory bank 104 is completed, the vector instruction multiplexer 105 supplies the instruction stored in the vector memory bank 103 to the address expansion unit 106. By repeating such an operation, a test pattern can be generated continuously.
[0015]
In this pattern generator, a common vector instruction in a pattern program for generating a test pattern is realized by a subroutine represented by, for example, “GOSUB” instruction and “label A”. The amount of memory required can be reduced, and the capacity required for the vector memory 101 for storing the pattern program can be reduced. In addition, since it is not necessary to store the same test pattern in the pattern memory 110, the capacity required for the pattern memory 110 can be reduced.
[0016]
FIG. 6 is a diagram showing a configuration of a conventional pattern generation unit 108 that stores a test pattern in a DRAM. The pattern generation unit 108 includes a pattern memory 110 constituted by a DRAM, a transfer control unit 111, pattern memory multiplexers (MUX) 112 and 113, pattern memory banks 114 and 115, and a multiplexer (MUX) 116. Have.
In the pattern generation unit 108, the address signal 107 output from the sequence control unit 100 is input to the multiplexers 112, 113, and 116 and the transfer control unit 111. When the address signal 107 is input, the transfer control unit 111 outputs a test pattern corresponding to the address signal 107 from the pattern memory 110 to the multiplexers 112 and 113.
[0017]
The multiplexers 112 and 113 start operation by selecting either the multiplexer 112 or 113 based on a predetermined bit value serving as a reference of the address signal 107. When the multiplexer 112 is selected, the multiplexer 112 or 113 starts operation from the pattern memory 110. The output test pattern is output to the pattern memory bank 114. When the multiprocessor 113 is selected, the test pattern output from the pattern memory 110 is output to the pattern memory bank 115. The multiplexer 116 selects either the pattern memory bank 114 or 115 based on the input address signal 107, for example, based on the difference in the upper bits of the address signal 107, and selects the selected pattern memory bank 114 or 115. The pattern signal of the test pattern is read from and generated.
[0018]
[Problems to be solved by the invention]
As described above, when the SRAM is used as the pattern memory for storing the test pattern in the pattern signal generation unit 108, the capacity required for the pattern memory can be suppressed by using an instruction such as a subroutine in the pattern program. By the way, in recent years, the number of test patterns necessary for testing one electrical component has increased with the increase in scale and multifunction of electrical components. For this reason, the situation that the capacity of the SRAM is insufficient for storing these test patterns has occurred, and a DRAM must be used to store the test patterns.
[0019]
Generally, only continuous address data can be transferred from a DRAM at high speed. For this reason, in the case where the test pattern is stored in the pattern memory 110 constituted by the DRAM, only the test pattern of continuous addresses can be transferred to the pattern memory bank 114 or 115 at high speed. Therefore, when an instruction to jump to a subroutine including a test pattern that is not stored in the pattern memory bank 114 or 115 is described in the pattern program, a situation occurs in which the test pattern cannot be generated without delay. End up.
[0020]
FIG. 7 is a diagram showing an example of a test pattern stored in a pattern memory 110 configured by a conventional DRAM. In order to avoid the above situation, as shown in FIG. 7, test patterns used in the test are sequentially stored in the pattern memory 110. For this reason, for example, even the same test pattern used for initialization processing is stored at a plurality of addresses, and there is a problem that a very large capacity DRAM must be used as the pattern memory 110. is there.
[0021]
SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generator, a pattern generation method, and a test apparatus that can reduce the capacity required for a pattern memory that stores a test pattern. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.
[0022]
[Means for Solving the Problems]
To achieve the above object, a pattern generator according to a first embodiment of the present invention is a pattern generator that generates a test pattern used for testing an electrical component, and associates a plurality of test patterns with addresses. A pattern memory to store, a plurality of memory banks to store test patterns read from the pattern memory, a vector memory to store vector instructions that define the order in which the test patterns are generated, and a vector read from the vector memory Based on the command, after jumping to the jump destination address when the jump detection unit detects whether or not the address on the pattern memory of the test pattern to be generated jumps, and the jump detection unit detects jumping An address that detects the jump destination address where the address jumps further in From the memory bank based on the vector command read from the vector memory and the transfer control unit that reads the test pattern after the address detected by the address detection unit from the pattern memory and transfers it to the memory bank. And a generator for generating the test pattern.
[0023]
The address detection unit may detect a jump destination address to which the address jumps next after jumping to the jump destination address.
Further, in the order specified by the vector instruction, the jump part where the address on the pattern memory of the test pattern to be generated jumps, and the jump destination where the address jumps further after jumping to the jump destination address of the jump part An address storage unit that stores association information for associating an address is further provided, and the address detection unit has an address corresponding to the jump portion detected by the jump detection unit based on the association information in the address storage unit. Further, a jump destination address for jumping may be detected.
[0024]
You may make it further provide the address setting part which sets matching information to an address memory | storage part. The address setting unit may set the association information based on an instruction from the user. The address setting unit may set the association information by analyzing the vector command. Further, the address setting unit may complete the analysis before the generating unit generates the test pattern.
In addition, the vector instruction includes a jump source address, a jump destination address,
It is associated with the address of the jump destination when the address jumps later,
The address detection unit may detect a jump destination address when the address jumps later from the vector instruction.
[0025]
The transfer control unit may transfer the test pattern after the address detected by the address detection unit to a memory bank different from the memory bank storing the test pattern of the jump destination address. Further, the transfer control unit may transfer the test pattern after the address detected by the address detection unit to a memory bank in which the test pattern of the jump source address is stored.
[0026]
The plurality of memory banks are divided into a plurality of memory groups, and the transfer control unit uses the memory bank storing the test pattern of the jump destination address as the test pattern after the address detected by the address detection unit. You may make it transfer to the memory bank of a memory group different from the memory group to which it belongs. The transfer control unit may transfer the test pattern after the address detected by the address detection unit to the memory bank of the memory group to which the memory bank storing the test pattern of the jump source address belongs. . A plurality of memory banks may belong to each memory group.
[0027]
The transfer control unit performs test patterns after the address detected by the address detection unit while the test unit stored in the memory bank in which the test pattern of the jump destination address is stored is generated by the generation unit. May be transferred from the pattern memory to the memory bank. Further, the transfer control unit may start to transfer the test pattern after the address detected by the address detection unit from the pattern memory to the memory bank almost simultaneously with the generation of the jump destination test pattern by the generation unit. . The memory bank may be a bipolar or metal oxide semiconductor (MOS) RAM.
[0028]
In order to achieve the above object, a pattern generator according to a second embodiment of the present invention is a pattern generator that generates a test pattern used for testing an electrical component, and associates a plurality of test patterns with addresses. A pattern memory to store, a plurality of memory banks to store test patterns read from the pattern memory, a vector memory to store vector instructions that define the order in which the test patterns are generated, and a vector read from the vector memory Based on the command, after jumping to the jump destination address when the jump detection unit detects whether or not the address on the pattern memory of the test pattern to be generated jumps, and the jump detection unit detects jumping An address detector for detecting the address of the test pattern to be generated; A transfer control unit that reads the test pattern after the address detected by the address detection unit from the memory and transfers it to the memory bank in which the test pattern of the jump source address is stored, and the vector instruction read from the vector memory And a generator for generating a test pattern from the memory bank.
The address detection unit may detect an address after a number that can be accommodated by one memory bank from the jump destination address.
[0029]
In order to achieve the above object, a test apparatus according to the present invention is a test apparatus for testing an electrical component, and an input test pattern applied to the electrical component for the test, and the input test pattern applied to the electrical component. A pattern memory that stores a test pattern including an expected value pattern that is sometimes expected to be output from an electrical component, a plurality of memory banks that store a test pattern read from the pattern memory, and a test pattern are generated A vector memory for storing a vector instruction for defining the order; and a jump detection unit for detecting whether or not an address on the pattern memory of the test pattern to be generated jumps based on the vector instruction read from the vector memory; Jump to the jump destination address when it is detected by the jump detector. An address detection unit for detecting a jump destination address where the address further jumps later, a transfer control unit for reading a test pattern after the address detected by the address detection unit from the pattern memory, and transferring the test pattern to the memory bank; and a vector memory Based on the vector command read out from the generator, the generation unit that generates the test pattern from the memory bank, and the pin data that rearranges the test pattern generated by the generation unit according to the pin arrangement of the electrical terminals of the electrical component The waveform shaper that shapes the waveform of the input test pattern included in the test pattern output from the selector and the pin data selector, and the input test pattern shaped by the waveform shaper is given to the electrical component and output from the electrical component A device plug-in that receives the output signal Characterized in that it comprises a comparator for comparing the expected pattern and the output signal plug portion is received.
[0030]
The address detection unit may detect a jump destination address to which the address jumps next after jumping to the jump destination address. Further, in the order specified by the vector instruction, the jump part where the address on the pattern memory of the test pattern to be generated jumps, and the jump destination where the address jumps further after jumping to the jump destination address of the jump part An address storage unit that stores association information for associating an address is further provided, and the address detection unit has an address corresponding to the jump portion detected by the jump detection unit based on the association information in the address storage unit. Further, a jump destination address for jumping may be detected.
[0031]
In order to achieve the above object, a pattern generation method according to the present invention is a pattern generation method for generating a test pattern used for testing an electrical component, and stores a plurality of test patterns in a pattern memory in association with addresses. A step of storing a vector instruction defining the order in which the test patterns are generated in the vector memory, and an address on the pattern memory of the test pattern to be generated based on the vector instruction read from the vector memory. A jump detection step for detecting whether or not to jump, and when it is detected that an address on the pattern memory of the test pattern to be generated jumps, after jumping to the jump destination address, the jump destination is further jumped. Address detection step for detecting addresses A test pattern from the memory bank based on a vector command read from the vector memory and a pattern transfer step for reading the test pattern after the address detected in the address detection step from the pattern memory and transferring it to the memory bank. And a generation step that is generated by taking out. The address detection step may detect a jump destination address to which the address jumps next after jumping to the jump destination address.
The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are the solution of the invention. It is not always essential to the means.
FIG. 8 is a diagram showing the overall configuration of the test apparatus according to the present invention. This test apparatus includes a pattern generator 60 having a sequence controller 62 and a pattern generator 26, a pin data selector 66, a waveform shaper 72, and a device difference having an insertion port 78 into which an electrical component 76 can be inserted. And a comparator 84. The pattern generator 60 provides an input test pattern to the electrical component 76 for the electrical test 76 of the electrical component, and an expectation to be output from the electrical component 76 when the input test pattern is applied to the normal electrical component 76. A test pattern signal 28 (test pattern signal) having a value pattern is transferred to the pin data selector 66.
[0033]
Here, the “electric part” means a part that performs a predetermined action according to a current or a voltage. For example, a semiconductor part made of an active element such as an IC (Integrated Circuit) or an LSI (Large-Scale Integrated circuit). In addition to passive components, various sensors, and other components, these components are combined into a single package, and breadboards that implement these functions by mounting these components on a printed circuit board. This part is also included. An “input test pattern” refers to a temporal or spatial arrangement of digital signals input to an electrical component in order to perform an electrical test, and an “expected value pattern” refers to a predetermined test pattern as an electrical component. Is a temporal or spatial arrangement of digital signals predicted as an output when input to.
[0034]
The pin data selector 66 rearranges the physical position of the test pattern signal 28 transferred from the pattern generator 60 according to the arrangement of the electrical terminals of the electrical component 76, and waveforms the input test pattern 68 in the test pattern signal 28. While transferring to the shaper 72, the expected value pattern 70 is transferred to the comparator 84. The waveform shaper 72 shapes the waveform of the input test pattern 68 transferred from the pin data selector 66 and transfers it to the device insertion unit 80.
[0035]
The device insertion unit 80 supplies the input test pattern 74 transferred from the waveform shaper 72 to the input terminal of the electrical component 76 inserted into the insertion port 78. Thereby, the electrical component 76 outputs the output pattern according to the test pattern input from the input terminal to the device insertion unit 80 from the predetermined output terminal based on its own function. In addition, the device insertion unit 80 transfers the output pattern 82 input from the output terminal of the electrical component 76 inserted into the insertion port 78 to the comparator 84.
[0036]
The comparator 84 compares the output pattern 82 transferred from the device insertion unit 80 with the expected value pattern 70 transferred from the pin data selector 66, and if the output pattern 80 and the expected value pattern 70 match. For example, it is determined that the electrical component 76 operates normally. On the other hand, if they do not match, it is determined that the electrical component 76 does not operate normally.
[0037]
FIG. 9 is a diagram showing the configuration of the pattern generator according to the first embodiment of the present invention. The pattern generator 60 includes a sequence control unit 62 and a pattern generation unit 26. The sequence control unit 62 includes a vector memory 12, a read control unit 14, an address expansion unit 22, an address setting unit 23, an address memory 33, and a jump address transfer control unit 31. The pattern generation unit 26 includes a pattern memory 32, a transfer control unit 34, pattern memory multiplexers (MUX) 36, 37, 38, and 39, a pattern cache memory 54, and multiplexers (MUX) 44, 45, and 46. Have. Here, the jump detection unit referred to in the claims is mainly configured by the address expansion unit 22, and the address detection unit referred to in the claims is mainly configured by the jump transfer control unit 31. The generator is mainly composed of a transfer controller 34 and multiplexers 44-46.
The vector memory 12 is composed of, for example, a high-speed SRAM, and stores a pattern program that defines the order of test patterns.
[0038]
FIG. 10 is a diagram showing an example of a pattern program stored in the vector memory 12 of the pattern generator according to the first embodiment of the present invention. In the pattern program, “START # 11” is a command for starting a test from a test pattern corresponding to the address signal # 11. “REPEAT 2 # 13” is an instruction to output a test pattern corresponding to the next address signal after generating a test pattern corresponding to the address signal # 13 twice. “JUMP A (value of jump source address signal) B (value of jump destination address signal)” is an instruction for generating a test pattern corresponding to the address signal B next to the test pattern corresponding to the address signal A. is there.
[0039]
In the pattern program of the present embodiment, “NEXT C (address signal value)”, that is, an instruction to output the address signal C and advance the value of the address signal by 1 is omitted. In the pattern program shown in FIG. 9, for example, “NEXT # 12” is omitted between “START # 11” and “REPEAT 2 # 13”, and “REPEAT 2 # 13” and “JUMP # 1D # 31” are omitted. "NEXT # 14" to "NEXT # 1C" are omitted.
[0040]
Returning to FIG. 9, the read control unit 14 reads the pattern program instruction stored in the vector memory 12 from the head and transfers it to the address development unit 22.
The address expansion unit 22 performs address expansion based on the transferred instruction and outputs an address signal 24. Further, the address developing unit 22 detects whether or not the address signal 24 jumps, and when a jump is detected, outputs an LST signal of “1” indicating that a jump has occurred. In this embodiment, “1” is also output when pattern generation is started.
The address development unit 22 also outputs a BKSL signal 30 that selects a cache memory of the pattern generation unit 26 that outputs a test pattern to be generated. In this embodiment, the address developing unit 22 switches the BKSL signal between “1” or “0” and outputs it every time it detects that the address signal jumps.
[0041]
The address memory 33 is composed of, for example, a high-speed SRAM, and stores a jump destination address signal to which the address signal jumps in the order defined by the pattern program stored in the vector memory 12. When the pattern program shown in FIG. 10 is stored in the vector memory 12, # 31, # 51, and # 71 are stored in order from the top of the storage area.
The address setting unit 23 receives an address signal to be stored in the address memory 33 and stores it in the address memory 33. The address setting unit 23 may receive an address signal directly from an input device such as a mouse or a keyboard from a user of the pattern generator and store the address signal. The address setting unit 23 analyzes the pattern program stored in the vector memory 12 to analyze the address. A signal may be detected and stored in the address memory 33. In this embodiment, an address signal is set in the address memory 33 before a test process described later.
[0042]
When the LST signal “1” indicating that a jump has occurred is input from the address expansion unit 22, the jump transfer control unit 31 detects the jump destination address signal of the next jump and generates a pattern signal. Output to the device 26. In this embodiment, immediately after the test pattern is generated and when each jump is detected, the address is sequentially extracted from the head of the address memory 33, thereby acquiring the jump destination address signal of the next generated jump.
[0043]
The pattern memory 32 is composed of a DRAM and stores a plurality of test patterns. The pattern memory 32 outputs a test pattern of an address corresponding to the signal input from the transfer control unit 34 and its address.
The pattern cache memory 54 includes a first pattern cache memory 50 and a second pattern cache memory 52. The first pattern cache memory and the second pattern cache memory are composed of a RAM that can read and write data at high speed, for example, a bipolar or MOS RAM.
[0044]
The first pattern cache memory 50 includes two pattern memory banks 40 and 41 that form the same group for storing test patterns of consecutive addresses. The second pattern cache memory 52 has two pattern memory banks 42 and 43 that form the same group for storing test patterns of consecutive addresses. For example, when an R (READ: read instruction) signal is input from the transfer control unit 34, each pattern memory bank 40 to 43 receives a test pattern from its own area corresponding to the address input from the preceding multiplexers 36 to 39. Is read out to the subsequent multiplexers 44 and 45.
[0045]
In addition, each pattern memory bank 40 to 43 receives a / W (/ is inverted logic: WRITE: write instruction) signal in its own area corresponding to the address input from the preceding multiplexers 36 to 39. A test pattern input from the pattern memory 32 is written. In the present embodiment, each of the pattern memory banks 40 to 43 has, for example, four addresses, and one test pattern can be stored in each address.
[0046]
The transfer control unit 34 performs control to store the test pattern in the predetermined pattern memory banks 40 to 43 based on the address signal input from the address developing unit 22. In the present embodiment, the transfer control unit 34 outputs a test pattern from the pattern memory 32 based on the input address signal, and instructs the pattern memory banks 40 to 43 to be stored to perform a write operation / In addition to outputting the W signal, the SEL signal for selecting the address output from the pattern memory 32 is output to the preceding multiplexers 36 to 39 of the pattern memory bank.
[0047]
Further, based on the address signal input from the address development unit 22, the transfer control unit 34 performs control to read a test pattern corresponding to the address from the pattern memory banks 40 to 43. In the present embodiment, the transfer control unit 34 outputs an R signal instructing a read operation to the pattern memory banks 40 to 43 in which the test pattern to be read is stored based on the input address signal, A SEL signal for selecting the address signal output from the address developing unit 22 is output to the multiplexers 36 to 39 in the previous stage of the pattern memory bank.
[0048]
When the address signal of the jump destination of the next jump generated from the jump transfer control unit 31 is input to the transfer control unit 34, the pattern of a group different from the group of the pattern memory bank in which the previous jump destination test pattern is written. Control is performed to write the test pattern of the next jump destination address corresponding to the memory bank. In the present embodiment, the transfer control unit 34 outputs the test pattern of the corresponding address from the pattern memory 32, and the pattern memory banks 40 to 43 in a group different from the group of the pattern memory bank in which the previous jump destination test pattern is written. A / W signal for instructing the write operation is output to the multiplexor, and a SEL signal for selecting the address output from the pattern memory 32 is output to the preceding multiplexer of the pattern memory bank.
[0049]
Based on the SEL signal input from the transfer control unit 34, the multiplexers 36 to 39 convert either the address signal input from the address development unit 22 or the address signal input from the pattern memory 32 to the subsequent pattern memory bank 40. Transfer to ~ 43.
[0050]
The multiplexer 44 selects the test pattern read from the pattern memory bank 40 or the test pattern read from the pattern memory bank 41 based on the address input from the address developing unit 22 and outputs the selected test pattern to the multiplexer 46. The multiplexer 45 selects either the test pattern read from the pattern memory bank 42 or the test pattern read from the pattern memory bank 43 on the basis of the address input from the address development unit 22 to the multiplexer 46. Output.
[0051]
Based on the BKSL signal 30 input from the address expansion unit 22, the multiplexer 46 receives the test pattern of the first pattern cache memory 50 input from the multiplexer 44 or the test pattern of the second pattern cache memory 52 input from the multiplexer 45. Select one of these to output. In the present embodiment, when the BKSL signal is “0”, the test pattern of the first pattern cache memory 50 is selected, and when the BKSL signal is “1”, the test pattern of the second pattern cache memory 52 is selected. .
[0052]
FIG. 11 is a diagram illustrating an operation of the pattern generator according to the first embodiment of the present invention. FIG. 11 shows an operation when the pattern program shown in FIG. 10 is stored in the vector memory 12. First, initial processing for storing the test pattern in any one of the pattern memory banks is performed. In the initial processing, the read control unit 14 takes out the instruction “START # 11” from the vector memory 12 and transfers it to the address development unit 22. The address expanding unit 22 expands the instruction “START # 11” and outputs an address signal # 11. When the transfer control unit 34 receives the address signal # 11, the transfer control unit 34 reads the four test patterns PAT11 to PAT14 after the address # 11 from the pattern memory 32 and writes the test patterns in the pattern memory bank 40. Further, the transfer control unit 34 reads the test patterns PAT 15 to 18 of the address signals # 15 to # 18 from the pattern memory 32 and writes the test patterns to the pattern memory bank 41.
[0053]
When the initial process is completed, the test process is performed. In the test process, the read control unit 14 sequentially fetches instructions from the instruction “START # 11” from the vector memory 12 and transfers them to the address development unit 22. Upon receiving the instruction “START # 11”, the address expansion unit 22 expands the address and outputs the address signal # 11 and the BKSL signal of “0”, and outputs the LST signal of “1” to the jump transfer control unit 31. To do. Next, the address expansion unit 22 sequentially expands the subsequent instructions, outputs addresses # 12, # 13, # 13, # 14, # 15, # 16,..., And outputs a BKSL signal of “0”. At the same time, an LST signal of “0” is output. When the LST signal of “1” is input from the address expansion unit 22, the jump transfer control unit 31 extracts the address # 31 stored at the head from the address memory 33 and outputs it to the transfer control unit 34.
[0054]
When the transfer control unit 34 receives the address signal # 11 from the address developing unit 22, the transfer control unit 34 reads the PAT 11 corresponding to the address # 11 from the pattern memory bank 40, and then the address signal # 12 after # 11 from the address developing unit 22. , # 13, # 13, # 14, the test patterns PAT12, PAT13, PAT13, PAT14 corresponding to these address signals are read from the pattern memory bank 40 in the same manner. The test patterns PAT11, PAT12, etc. read in this way are selected by the multiplexers 44 and 46 and output to the pin data selector 66.
[0055]
When the transfer control unit 34 receives the address # 31 from the jump transfer control unit 31, in parallel with the above operation, the transfer control unit 34 reads the test pattern after the address # 31 from the pattern memory 32, and the pattern currently being read. These test patterns are written into a pattern cache memory other than the first pattern cache memory 50 including the memory bank 40, that is, the second pattern cache memory 52. Specifically, PATs 31 to 34 are written in the pattern memory bank 42, and PATs 35 to 38 are written in the pattern memory bank 43.
[0056]
When the transfer control unit 34 receives the address signal # 15 from the address developing unit 22, the transfer control unit 34 reads the PAT 15 corresponding to the address # 15 from the pattern memory bank 41. The transfer control unit 34 reads the test patterns PAT16, PAT17, and PAT18 corresponding to the address signals # 16, # 17, and # 18 received after the address signal # 15 from the address developing unit 22 from the pattern memory bank 41 in the same manner. Let it come out. When the transfer control unit 34 receives the address signal # 15 from the address developing unit 22, the transfer control unit 34 reads the test patterns from the pattern memory 32 to the addresses # 19 to # 1C in parallel with the above operation, and performs the current reading. The test patterns PAT19 to PAT1C are written to another pattern memory bank in the first pattern cache memory 50 including the pattern memory bank 41, that is, the pattern memory bank 40.
[0057]
If no address signal is input from the jump transfer control unit 31, the transfer control unit 34 is in the same group as the pattern memory bank reading the test pattern while reading the test pattern in the same manner as described above. Subsequent test patterns are written to another pattern memory bank.
[0058]
Here, when the address developing unit 22 detects that the address jumps such as outputting # 31 after outputting # 1D, it outputs the address # 31 and switches the BKSL signal to “1” and outputs it. Further, the LST signal “1” is output to the jump transfer control unit 31. When the LST signal of “1” is input from the address expansion unit 22, the jump transfer control unit 31 extracts the address # 51 next to the previously extracted address from the address memory 33 and outputs it to the transfer control unit 34.
[0059]
When the transfer control unit 34 receives the address signal # 31 from the address development unit 22, the transfer control unit 34 reads the PAT 31 corresponding to the address # 31 from the pattern memory bank 42, and then the address signal # 31 and subsequent addresses # 31 from the address development unit 22. When 32, # 33, and # 34 are received, the test patterns PAT32, PAT33, and PAT34 corresponding to these address signals are read from the pattern memory bank 42 in the same manner. The test patterns PAT31, PAT32, etc. read in this way are selected by the multiplexers 44 and 46 and output to the pin data selector 66.
[0060]
In addition, when the transfer control unit 34 receives the jump destination address # 51 of the next jump from the jump transfer control unit 31, in parallel with the above operation, the test pattern after the address # 51 is read from the pattern memory 32, These test patterns are written into a pattern cache memory other than the second pattern cache memory 52 including the pattern memory bank 42 currently being read, that is, the first pattern cache memory 50. Specifically, PATs 51 to 54 are written in the pattern memory bank 40, and PATs 55 to 58 are written in the pattern memory bank 41.
[0061]
In the present embodiment, the test pattern after the next jump destination # 51 is transferred to the other two in less than half the time during which the test pattern in the pattern memory bank 42 including the test pattern # 31 to be generated is generated. It is necessary to transfer to the two pattern memory banks 40 and 41. For this reason, it is desirable to start the transfer almost simultaneously with the time when the test pattern after the next jump destination can be written to the two pattern memory banks as soon as possible, for example, when the test pattern at the jump destination is generated. .
[0062]
As described above, the test pattern written in the pattern memory banks 40 and 41 is stored in the corresponding pattern memory bank by the transfer control unit 34 when the address signal of the test pattern is input from the address development unit 22 to the transfer control unit. The data is read out from 40 and 41, selected by the multiplexers 44 and 46, and output to the pin data selector 66 without delay.
[0063]
Such an operation is performed until an instruction stored in the vector memory 12 is executed.
As described above, according to the present pattern generator, the next test pattern stored at a distant address in the pattern memory 32 can be generated without delay, and the same test pattern is stored in the pattern memory 32 in duplicate. Therefore, the capacity required for the pattern memory 32 can be reduced.
[0064]
FIG. 12 is a diagram showing a configuration of a pattern generator according to the second embodiment of the present invention. The functional elements different from those of the pattern generator according to the first embodiment shown in FIG. 9 will be described in detail. The pattern generator includes a sequence control unit 62 and a pattern generation unit 26. The sequence control unit 62 includes a vector memory 12, a read control unit 14, and an address expansion unit 22. The pattern generation unit 26 includes a pattern memory 32, a transfer control unit 34, pattern memory multiplexers 36, 37, 38, and 39, a pattern cache memory 54, and multiplexers 44, 45, and 46.
[0065]
FIG. 13 is a diagram showing an example of a pattern program stored in the vector memory 12 of the pattern generator according to the second embodiment of the present invention. The pattern program according to the present embodiment differs from the pattern program according to the first embodiment in the description format of the “START” and “JUMP” instructions. “START AB” is a command for starting a test from a test pattern corresponding to the address signal A and reading the test pattern corresponding to the address signal B to the cache memory.
[0066]
“JUMP A (value of jump source address signal) B (value of jump destination address signal) C (value of jump destination address signal)” follows the test pattern corresponding to address signal A. , A command for generating a test pattern corresponding to the address signal B and reading the test pattern corresponding to the address signal C to the cache memory. For example, “JUMP # 39 # 51 # 71” generates a test pattern corresponding to the address signal # 51 next to the test pattern corresponding to the address signal # 39, and caches the test pattern corresponding to the address signal # 71. This is an instruction to read into the memory.
[0067]
The address expansion unit 22 detects whether or not the address signal 24 jumps in the address expansion unit 22 of the first embodiment, and when the jump is detected, the LST of “1” indicating that a jump has occurred When the start address described in the START instruction is output instead of the signal output function, the address of the test pattern to be read described in the START instruction is output, and the jump source address signal value of the JUMP instruction is set. After the output, the function of outputting the address signal value of the next jump destination to the transfer control unit 34 is provided.
The transfer control unit 34 operates based on the address input from the address expansion unit 22 in the transfer control unit 34 according to the first embodiment, based on the address signal input from the jump transfer control unit 31. It is what you do. The pattern generator according to the present embodiment can perform the same operation as that of the pattern generator according to the first embodiment shown in FIG.
[0068]
FIG. 14 is a diagram showing a configuration of a pattern generator according to the third embodiment of the present invention. The functional elements different from the pattern generator according to the first embodiment will be described in detail. The pattern generator includes a sequence control unit 62 and a pattern generation unit 26. The sequence control unit 62 includes a vector memory 12, a read control unit 14, and an address expansion unit 22. The pattern generation unit 26 includes a pattern memory 32, an address memory 56, a transfer control unit 34, pattern memory multiplexers (MUX) 36, 37, and 38, a pattern cache memory 54, and multiplexers (MUX) 44 and 46. Have
[0069]
FIG. 15 is a diagram showing an example of a pattern program stored in the vector memory 12 of the pattern generator according to the third embodiment of the present invention. The pattern program according to the present embodiment differs from the pattern program according to the first embodiment in the description format of the “JUMP” instruction. “JUMPA (jump destination address signal value) B (jump source address signal value)” is an instruction for generating a test pattern corresponding to the address signal A after the test pattern corresponding to the address signal B. In the present embodiment, the jump destination is only # 11 and only the instruction “JUMP11 B” is described.
The pattern cache memory 54 has three memory banks 40, 41 and 42. In the present embodiment, each of the memory banks 40 to 42 can store four test patterns.
[0070]
The address memory 56 stores addresses ahead of the number of test patterns that can be stored in one memory bank from the jump destination address. In the present embodiment, the jump destination address is always # 11, and each memory bank 40-42 can store four test patterns, so # 15 is stored.
The address expansion unit 22 detects whether or not the address signal 24 jumps in the address expansion unit 22 of the first embodiment, and when the jump is detected, the LST of “1” indicating that a jump has occurred Instead of the function of outputting a signal, after outputting the address signal value of the jump source of the JUMP instruction, it has a function of outputting a signal “1” indicating the jump to the transfer control unit 34. The address expansion unit 22 has a function of outputting a jump destination address that is a jump destination in the initial processing. Further, the address developing unit 22 outputs the BKSL signal as “1” when outputting addresses # 11 to # 14, and outputs the BKSL signal as “0” when outputting other addresses. .
[0071]
The transfer control unit 34 further has a function of extracting an address from the address memory 56 based on the signal input from the address development unit 22 in the transfer control unit 34 of the first embodiment. In the transfer control unit 34 according to the embodiment, the operation performed based on the address signal input from the jump transfer control unit 31 is performed based on the address taken out from the address memory 56.
[0072]
FIG. 16 is a diagram illustrating the operation of the pattern generator according to the third embodiment of the present invention. First, initial processing for storing the test pattern in any one of the pattern memory banks is performed. In the initial processing, the read control unit 14 takes out the instruction “START # 0” from the vector memory 12 and transfers it to the address development unit 22. The address expansion unit 22 expands the instruction “START # 0” to output an address signal # 0, and further outputs a JUMP destination address signal # 11 included in the instruction.
[0073]
When receiving the address signal # 0, the transfer control unit 34 reads out the four test patterns PAT0 to PAT3 after the address # 0 from the pattern memory 32 and writes the test patterns in the pattern memory bank 40. Furthermore, when the transfer control unit 34 receives the address # 11 from the pattern memory 32, the transfer control unit 34 reads the test patterns PAT 11 to 14 of the address signals # 11 to # 14 from the pattern memory 32 and writes the test pattern to the pattern memory bank 42. Make it.
[0074]
When the initial process is completed, the test process is performed. In the test process, the read control unit 14 sequentially fetches instructions from the instruction “START # 0” from the vector memory 12 and transfers them to the address development unit 22. Upon receiving the instruction “START # 0”, the address expansion unit 22 expands the address and outputs an address signal # 0 and a BKSL signal of “0”. Next, the address expansion unit 22 sequentially expands addresses of subsequent instructions and outputs addresses # 1, # 11, # 12. At this time, when a jump occurs, for example, when outputting # 11 immediately after # 1, the address developing unit 22 outputs an LST signal of “1” indicating that the jump is performed to the transfer control unit 34. .
[0075]
When the transfer control unit 34 receives the address signals # 0 and # 1 from the address developing unit 22, the transfer control unit 34 reads the PAT0 and PAT1 corresponding to the addresses # 0 and # 1 from the pattern memory bank 40, and sends the address signal from the address developing unit 22. When # 11, # 12,... Are received, the test patterns PAT11, PAT12, etc. corresponding to the addresses # 11, # 12,.
When the transfer control unit 34 receives the LST signal “1” indicating jump from the address development unit 22, the transfer control unit 34 reads the test pattern corresponding to the address # 11 from the address memory 56 in parallel with the operation of reading the test pattern. 15 is read out, and the test patterns PAT15, PAT16, PAT17, and PAT18 corresponding to the addresses # 15, # 16, # 17, and # 18 after the address are read from the pattern memory 32, and the test pattern is transferred to # 11. The pattern memory bank 40 in which # 1 of the jump source has been written is written.
[0076]
Thereafter, when no jump occurs, when the test pattern in the pattern memory bank 40 is being read, the subsequent test pattern is written in the pattern memory bank 41, and the test pattern in the pattern memory bank 41 is read out. At the same time, the subsequent test pattern is written in the pattern memory bank 40. On the other hand, when a jump occurs, the address # 15 is taken out from the address memory 56 in the same manner as described above, and the test patterns PAT15, PAT16, The PAT 17 and the PAT 18 are read from the pattern memory 32, and the test pattern is read into a pattern memory bank other than the pattern memory bank in which the jump destination test pattern is written, for example, the pattern memory bank in which the jump source address is written. Let it be written. Thereby, these test patterns can be generated later without delay. Note that the above test patterns PAT15, PAT16, PAT17, and PAT18 may be always written in the same pattern memory bank (for example, the pattern memory bank 40), and in this way, the pattern memory bank of the test pattern of the jump destination The test pattern to be read out next to the test pattern stored in is always stored in the same pattern memory bank, and the information for specifying the pattern memory bank in which the test pattern to be read out next is stored is grasped. There is no need for an arrangement, and the apparatus configuration is simplified.
[0077]
Such an operation is performed until the instruction stored in the vector memory 12 is completed.
As described above, according to the present pattern generator, the next test pattern stored at a separate address in the pattern memory 32 is delayed with a simpler configuration than the pattern generators according to the first and second embodiments described above. It is not necessary to store the same test pattern in the pattern memory 32 redundantly, and the capacity required for the pattern memory 32 can be reduced.
[0078]
The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the first embodiment, when the address expansion unit 22 detects a jump in the address memory 33 in which the order from the head is associated with the jump destination address of the next jump, jump transfer is performed. The control unit 31 detects the jump destination address of the next jump from the beginning. However, the present invention is not limited to this. For example, in the address memory 33, the jump destination address and the next jump destination address. When the jump is detected by the address expansion unit 22, the jump destination address is output, and the jump transfer control unit 31 causes the next jump destination corresponding to the address from the address expansion unit 22 to be output. The address may be detected from the address memory 33. The point is that if a jump is detected, It is only necessary to detect the jump destination address.
[0079]
In the first and second embodiments, the test pattern after the jump destination address of the next jump is written to the pattern memory bank. However, the present invention is not limited to this, and the next jump destination You may make it write the test pattern of the jump destination address after an address to a pattern memory bank. In the first and second embodiments, the test pattern of the jump destination of the first jump is stored in the pattern memory bank after the test process is started. However, the present invention is not limited to this. In the initial processing, the first jump destination test pattern may be stored in the pattern memory bank.
[0080]
In the first and second embodiments, two groups are provided as the group of pattern memory banks. However, the present invention is not limited to this, and more groups may be provided. In the first and second embodiments, the number of pattern memory banks in one group is two. However, the present invention is not limited to this, and an arbitrary number of memory banks are provided in each group. May be.
[0081]
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.
[0082]
【The invention's effect】
As is clear from the above description, according to the pattern generator, pattern generation method, and test apparatus of the present invention, the capacity required for the pattern memory that stores the test pattern can be suppressed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a conventional pattern generator for storing a test pattern in an SRAM.
FIG. 2 is a diagram showing an example of a pattern program stored in a vector memory.
FIG. 3 is a diagram showing an example of a compressed pattern program stored in a vector memory.
FIG. 4 is a diagram illustrating an example of a test pattern stored in a pattern memory of a pattern signal generation unit.
FIG. 5 is a diagram illustrating the operation of a conventional pattern generator.
FIG. 6 is a diagram showing a configuration of a conventional pattern generator for storing a test pattern in a DRAM.
FIG. 7 is a diagram showing an example of a test pattern stored in a conventional pattern memory constituted by a DRAM.
FIG. 8 is a diagram showing an overall configuration of a test apparatus according to an embodiment of the present invention.
FIG. 9 is a diagram showing a configuration of a pattern generator according to the first embodiment of the present invention.
FIG. 10 is a diagram showing an example of a pattern program stored in a vector memory of the pattern generator according to the first embodiment of the present invention.
FIG. 11 is a diagram showing an operation of the pattern generator according to the first embodiment of the present invention.
FIG. 12 is a diagram showing a configuration of a pattern generator according to a second embodiment of the present invention. .
FIG. 13 is a diagram showing an example of a pattern program stored in a vector memory of a pattern generator according to the second embodiment of the present invention.
FIG. 14 is a diagram showing a configuration of a pattern generator according to a third embodiment of the present invention.
FIG. 15 is a diagram showing an example of a pattern program stored in a vector memory of a pattern generator according to the third embodiment of the present invention.
FIG. 16 is a diagram illustrating an operation of a pattern generator according to a third embodiment of the present invention.
[Explanation of symbols]
12 Vector memory
14 Read controller
22 Address expansion part
24 Address signal
26 Pattern generator
30 BKSL signal
31 Jump transfer controller
32 pattern memory
33, 56 address memory
34 Transfer control unit
36, 37, 38, 39 Multiplexer for pattern memory
40, 41, 42, 43 Pattern memory bank
44 First Pattern Multiplexer
45 Second Pattern Multiplexer
46 Multiplexer
50 First pattern cache memory
52 Second pattern cache memory
54 pattern cache memory
60 pattern generator
62 Sequence controller
66 pin data selector
72 Waveform Shaper
76 Electrical components
80 Device insertion part
84 Comparator

Claims (21)

A pattern generator for generating a test pattern used for testing an electrical component,
A pattern memory for storing a plurality of the test patterns in association with addresses;
A plurality of memory banks for storing the test patterns read from the pattern memory;
A vector memory for storing vector instructions defining the order in which the test patterns are generated;
A jump detection unit for detecting whether or not an address on the pattern memory of the test pattern to be generated jumps based on the vector instruction read from the vector memory;
An address detection unit for detecting a jump destination address to which the address further jumps after jumping to the jump destination address when it is detected by the jump detection unit;
A transfer control unit for reading out the test pattern after the address detected by the address detection unit from the pattern memory and transferring the test pattern to the memory bank;
A generation unit that generates the test pattern from the memory bank based on the vector instruction read from the vector memory ;
The transfer control unit is detected by the address detection unit while the test pattern stored in the memory bank storing the test pattern of the jump destination address is generated by the generation unit. A pattern generator for transferring the test pattern after the address to the memory bank different from the memory bank storing the test pattern of the jump destination address . 2. The pattern generator according to claim 1, wherein the address detection unit detects a jump destination address to which the address jumps next after jumping to the jump destination address. A jump portion where the address on the pattern memory of the test pattern to be generated jumps in the order specified by the vector instruction, and a jump destination where the address further jumps after jumping to the jump destination address of the jump portion An address storage unit for storing association information for associating addresses of
The address detecting unit detects a jump destination address corresponding to the jump portion detected when the jump is detected by the jump detecting unit, based on the association information in the address storage unit, to which the address further jumps. The pattern generator according to claim 1 or 2. The pattern generator according to claim 3, further comprising an address setting unit that sets the association information in the address storage unit. The pattern generator according to claim 4, wherein the address setting unit sets the association information based on an instruction from a user. The pattern generator according to claim 4, wherein the address setting unit sets the association information by analyzing the vector command. The pattern generator according to claim 6, wherein the address setting unit performs an analysis before the generation unit generates the test pattern. In the vector instruction, a jump source address, a jump destination address, and a jump destination address when the address jumps later are associated,
The pattern generator according to claim 7, wherein the address detection unit detects the jump destination address when the address jumps later from a vector instruction. The transfer control unit, the test pattern of the address after detected by the address detection unit, from claim 1, wherein the forwarding to the memory banks test pattern jump source address is stored The pattern generator according to any one of 8 . The plurality of memory banks are divided into a plurality of memory groups,
The transfer control unit is configured such that the test pattern after the address detected by the address detection unit is different from the memory group to which the memory bank in which the test pattern of the jump destination address is stored belongs to the memory group. 9. The pattern generator according to claim 1 , wherein the pattern generator is transferred to a memory bank. The transfer control unit transfers the test pattern after the address detected by the address detection unit to the memory bank of the memory group to which the memory bank in which the test pattern of the jump source address is stored belongs. pattern generator according to claim 1 0, characterized in that. Wherein the plurality of memory groups, the pattern generator according to claim 1 0 or 1 1, characterized in that each belong plurality of memory banks. The transfer control unit transfers the test pattern after the address detected by the address detection unit from the pattern memory to the memory bank almost simultaneously with the generation of the jump destination test pattern by the generation unit. pattern generator according to claim 1 1 2, characterized in that to start. The memory bank pattern generator according to claim 1 1 3, characterized in that a bipolar system or a random access memory metal Oxide Semiconductor system. A pattern generator for generating a test pattern used for testing an electrical component,
A pattern memory for storing a plurality of the test patterns in association with addresses;
A plurality of memory banks for storing the test patterns read from the pattern memory;
A vector memory for storing vector instructions defining the order in which the test patterns are generated;
A jump detection unit for detecting whether or not an address on the pattern memory of the test pattern to be generated jumps based on the vector instruction read from the vector memory;
An address detection unit for detecting an address of the test pattern to be generated after jumping to a jump destination address when it is detected that the jump is detected by the jump detection unit;
A transfer control unit that reads the test pattern after the address detected by the address detection unit from the pattern memory, and transfers the test pattern to the memory bank in which the test pattern of the jump source address was stored;
A pattern generator comprising: a generation unit that extracts and generates the test pattern from the memory bank based on the vector instruction read from the vector memory. The pattern generator according to claim 15 , wherein the address detection unit detects an address after a number that can be accommodated by one memory bank from a jump destination address. A testing device for testing electrical components,
A test pattern including an input test pattern given to the electrical component for the test and an expected value pattern expected to be output from the electrical component when the input test pattern is given to the electrical component is stored. Pattern memory,
A plurality of memory banks for storing the test patterns read from the pattern memory;
A vector memory for storing vector instructions defining the order in which the test patterns are generated;
A jump detection unit for detecting whether or not an address on the pattern memory of the test pattern to be generated jumps based on the vector instruction read from the vector memory;
An address detection unit for detecting a jump destination address to which the address further jumps after jumping to the jump destination address when it is detected by the jump detection unit;
A transfer control unit for reading out the test pattern after the address detected by the address detection unit from the pattern memory and transferring the test pattern to the memory bank;
Based on the vector instruction read from the vector memory, a generating unit that generates the test pattern from the memory bank; and
A pin data selector for rearranging the test pattern generated by the generator according to the pin arrangement of the electrical terminals of the electrical component;
A waveform shaper for shaping the waveform of the input test pattern included in the test pattern output from the pin data selector;
A device insertion unit that gives the input test pattern shaped by the waveform shaper to the electrical component and receives an output signal output from the electrical component;
A comparator for comparing the output signal received by the device insertion unit with the expected value pattern ;
The transfer control unit is detected by the address detection unit while the test pattern stored in the memory bank storing the test pattern of the jump destination address is generated by the generation unit. A test apparatus for transferring the test pattern after the address to the memory bank different from the memory bank storing the test pattern of the jump destination address . The test apparatus according to claim 17 , wherein the address detection unit detects a jump destination address to which an address jumps next after jumping to the jump destination address. A jump portion where the address on the pattern memory of the test pattern to be generated jumps in the order specified by the vector instruction, and a jump destination where the address further jumps after jumping to the jump destination address of the jump portion An address storage unit for storing association information for associating addresses of
The address detecting unit detects a jump destination address corresponding to the jump portion detected when the jump is detected by the jump detecting unit, based on the association information in the address storage unit, to which the address further jumps. The test apparatus according to claim 17 or 18 . A pattern generation method for generating a test pattern used for testing an electrical component,
Storing a plurality of the test patterns in a pattern memory in association with addresses;
An instruction storing step of storing in the vector memory a vector instruction defining the order in which the test patterns are generated;
A jump detection step for detecting whether an address on the pattern memory of the test pattern to be generated jumps based on the vector instruction read from the vector memory;
An address detecting step of detecting a jump destination address to which the address further jumps after jumping to the jump destination address when it is detected that the address on the pattern memory of the test pattern to be generated jumps;
A pattern transfer step of reading the test pattern after the address detected in the address detection step from the pattern memory and transferring it to a memory bank;
Generating the test pattern from the memory bank based on the vector instruction read from the vector memory ;
While the test pattern stored in the memory bank in which the test pattern of the jump destination address is stored is generated, the test pattern after the address detected in the address detection step is jumped. A pattern generation method comprising transferring to a memory bank different from the memory bank in which a test pattern of a previous address is stored . It said address detection step, the pattern generation method of claim 2 0, characterized in that for detecting the address of the jump destination address is subsequently jumps in after jumping to a jump destination address.

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