KR100219494B1 - Semiconductor memory apparatus for controlling special mode - Google Patents

Abstract

A semiconductor memory device for controlling a special mode according to the present invention is disclosed.

The apparatus includes a PWCBR generator for inputting / CAS, / RAS, and / WE signals to output a write enable CBR signal, a signal output from the PWCBR generator, a normal MRS address signal, and a special MRS address signal, An MRS enable signal generator for generating a first control signal for enabling the mode and a second control signal for disabling the special mode, the normal MRS address signal being controlled by the first control signal to set the normal mode And a special MRS generator in which the special MRS address signal is controlled by the second control signal so that the special mode is not set.

Therefore, as described above, according to the present invention, there is an effect of solving the problem that the special MRS address must be applied low when setting the normal MRS, so that no matter what information the special MRS address has, it does not affect the normal MRS.

Description

A semiconductor memory device controlling a special mode.

[0001] The present invention relates to a semiconductor memory device for controlling a special mode, and more particularly, to a semiconductor memory device for controlling a special mode (Special Mode Register Set) A test mode, and a semiconductor memory device. In a semiconductor memory device capable of setting the operation mode, the operation mode of the chip is determined in the WCBR (Write enable / CAS Before / RAS) cycle. Therefore, an enable signal (Enable signal) for setting an operation mode in the WCBR cycle is generated and the operation mode is set by using the enable signal.

1 is a diagram showing a configuration of a conventional MRS.

1, reference numeral 102 denotes a / CS buffer, 104 denotes a / CAS buffer, 106 denotes a / RAS buffer, 108 denotes a / WE buffer, 110 denotes an address buffer for a normal MRS field, 112 denotes a special MRS field Reference numeral 114 denotes a PWCBR (Pulse WCBR) generator, reference numeral 116 denotes an MRS enable signal generator, reference numeral 118 denotes a normal MRS generator, and reference numeral 120 denotes a special MRS generator.

/ CS is a signal indicating that the chip is selected, and the memory device becomes ready to read and write when this signal is active. / CAS is an address strobe (signal extracting pulse) on the side of the memory cell array, and / RAS is an address strobe on the side of the memory cell array. In dynamic RAM, since the row is read first and then the bit of the column is selected, the input of the address is multiplexed, that is, the row address is inputted first and then the address is inputted after the dress. Therefore, a signal for strobing these addresses is required, which are / RAS and / CAS signals, respectively. The / WE buffer 108 is a signal for specifying whether access is a read or write. When this signal is active, it indicates a write, and when it is inactive, it indicates a read. The slash (/) sign indicates that the negative logic is defined. The address for the normal MRS field is a signal input to the normal MRS generator 120 to set the normal mode. The address for the special MRS field is a signal input to the special MRS enable signal generator 122 for setting the special mode. / CS buffer 102, the CAS buffer 104, the / RAS buffer 106, the WE buffer 108, the normal MRS field address buffer 110 and the special MRS field address buffer 112, It is a storage place for temporarily storing one signal. The PWCBR generator 114 receives a signal output from the / CAS buffer 104, the RAS buffer 106, and the WE buffer 108 to generate a pulse for enabling CBR (/ CAS Before / RAS) And outputs it to the MRS enable signal generator 116. The MRS enable signal generator 116 receives a signal output from the address buffer 112 for the special MRS field and a signal output from the PWCBR to generate a control signal for activating the MRS generator. The normal MRS generator 118 receives the signal output from the MRS enable signal generator 116 and the signal output from the address buffer 110 for the normal MRS field to generate an enable signal for setting the normal mode. The special MRS generator 120 receives the signal output from the MRS enable signal generator 116 and the address signal 112 for the special MRS field to generate an enable signal for setting a special mode.

The operation of the conventional MRS enable signal generator shown in FIG. 1 will now be described.

First, when a chip select signal is input from the / CS buffer 102 to each of the buffers 104, 106, 108, 110 and 112, the / CAS buffer 104, the / RAS buffer 106 and the / WE buffer 108 Each output signal is input to the PWCBR generator 114. The PWCBR generator 114 generates a signal for enabling the CBR and outputs the generated signal to the MRS enable signal generator 116. [ The signals output from the normal MRS field address buffer 110 are input to the normal MRS generator 120 and some of the signals output from the special MRS field address buffer 112 are supplied to the MRS enable signal generator 116 And the remaining signals are input to the special MRS generator 122. [ Next, the MRS enable signal generator 116 receives the signals output from the PWCBR generator 114 and the special MRS field address buffer 112, and outputs a control signal for enabling the MRS generators 118 and 120 to the normal MRS Generator 118 and the special MRS generator 120, respectively.

2 shows a detailed configuration of the MRS enable signal generator shown in FIG.

2, reference numeral 22 denotes a NOR gate, reference numerals 24 and 28 denote an inverter, and reference numeral 26 denotes a NAND gate.

The operation of the MRS enable signal generator shown in FIG. 2 will be described below.

First, when the first address bar signal and the second address bar signal for the special MRS field (opposite phase to the address signal; all signals in the case of the normal MRS) are input to the NOR gate 22, the output becomes high, Inverted by inverter 24 and a low signal is output. On the other hand, in the PWCBR generator 25, only the high signal is applied, so that the NAND gate 26 outputs the low signal and the low signal is inverted by the inverter 28 to output the high signal.

3 is a diagram showing a detailed configuration of the normal MRS generator shown in FIG. In Fig. 3, reference numeral 32 denotes a transfer gate (transfer gate 1), and numerals 34 to 38 denote inverters.

The transfer gate 32 is a MOS transistor used for on / off control of a signal. The transfer gate 32 is controlled by the control signal output from the MRS enable signal generator shown in Fig.

The operation of the normal MRS generator shown in FIG. 3 will now be described.

When the normal MRS field address bar signal (low signal) is inputted to the transfer gate 32, the normal MRS field address bar signal passes the transfer gate 32 in a low state by the control signal (high signal). The signal output from the transfer gate 32 is inverted by the inverters 36 and 38 and becomes a high signal, so that the normal mode is set by the address for the normal MRS field.

FIG. 4 shows a detailed configuration of the special MRS generator shown in FIG. 1. FIG.

4, reference numeral 42 denotes a transfer gate, and reference numerals 44 to 48 denote inverters. The reference numerals are the same as those described in Fig.

The operation of the special MRS generator shown in FIG. 4 will be described below.

When a special MRS field address (low signal) is input to the transfer gate 42, the signal is equal to the level applied in FIG. 2 and FIG. 3, and the special mode is set in the same manner.

3 and 4, when the transfer gate control signal output from the MRS enable signal generator 116 is turned on at the same time by the transfer gates 32 and 42, The user is set to the desired mode.

1 and 2, the two transfer gates 32 and 42 are turned on by the control signal (high signal) output from the conventional MRS enable signal generator so that the normal mode and the special mode Is set at the same time, which results in the user being set up to an undesired mode (special MRS mode). Therefore, when setting the normal MRS, there is a problem that the address for the special MRS field must be applied low.

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device for controlling a special MRS mode (test mode) so that a normal MRS can be set regardless of a signal from a special MRS field address buffer .

1 is a diagram showing a configuration of a conventional MRS.

2 shows a detailed configuration of the MRS enable signal generator shown in FIG.

3 is a diagram showing a detailed configuration of the normal MRS generator shown in FIG.

FIG. 4 shows a detailed configuration of the special MRS generator shown in FIG. 1. FIG.

5 is a diagram illustrating a configuration of an MRS according to the present invention.

FIG. 6 is a diagram illustrating a detailed configuration of the MRS enable signal generator shown in FIG.

7 is a diagram showing a detailed configuration of the normal MRS generator shown in FIG.

FIG. 8 is a detailed block diagram of the special MRS generator shown in FIG.

According to an aspect of the present invention, there is provided a semiconductor memory device for controlling a special mode, comprising: a PWCBR generator for inputting / CAS, / RAS, and / WE signals to output a write enable CBR signal; An MRS enable signal for generating a first control signal for enabling the normal mode and a second control signal for disabling the special mode, receiving the signal output from the PWCBR generator, the normal MRS address signal, and the special MRS address signal, Signal generator; A normal MRS generator for setting the normal mode by controlling the normal MRS address signal by the first control signal; And a special MRS generator in which the special MRS address signal is controlled by the second control signal so that the special mode is not set.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 5 is a diagram illustrating a configuration of an MRS (mode register set) according to the present invention.

5, reference numeral 516 denotes an MRS enable signal generator according to the present invention.

The MRS enable signal generator 516 receives the signal output from the PWCBR generator 514, the signal output from the normal MRS field address buffer 510, and the signal output from the address buffer 512 for the special MRS field, And outputs a first control signal and a second control signal for controlling the MRS generator 518 and the special MRS generator 520, respectively. The remaining reference numerals are the same as those described in Fig.

The operation of the MRS enable signal generator 516 according to the present invention shown in FIG. 5 will now be described.

When a chip select signal is input to the buffers 504, 506, 508, 510, and 512 in the / CS buffer 502, the / CAS buffer 504, the / RAS buffer 506, and the / WE buffer 508 The output signal is input to the PWCBR generator 514, and the PWCBR generator generates a signal for enabling the CBR signal and outputs it to the MRS enable signal generator 516. Meanwhile, some of the signals output from the normal MRS field address buffer 510 are input to the MRS enable signal generator 516, and the remaining signals are input to the normal MRS generator 520. Some of the signals output from the address buffer 512 for the special MRS field are input to the MRS enable signal generator 516 and the remaining signals are input to the special MRS generator 520. Next, the MRS enable signal generator 516 receives signals output from the PWCBR generator 514, the normal MRS field address buffer 510, and the special MRS field address buffer 512 to enable the MRS And outputs the first control signal and the second control signal to the normal MRS generator 520 and the special MRS generator 522, respectively.

FIG. 6 is a diagram illustrating a detailed configuration of the MRS enable signal generator shown in FIG.

In FIG. 6, reference numeral 602 denotes a NOR gate, reference numerals 604, 608, 612 and 616 designate first to fourth inverters, reference numerals 606, 610 and 614 denote first to third NAND gates, reference numerals 614 to 618 denote first, And K1 to K3 nodes, respectively.

The operation of the apparatus shown in FIG. 6 will be described below.

First, the first, second and third address bar signals for the normal MRS field are input to the second NAND gate 610. At least one address bar signal is always low during the MRS desired by the user, 610) is high. Next, the node K1, which is a signal that has passed through the inverter 612, becomes low, so that the second control signal, which is a signal passed through the NAND gate 606 and the inverter 608, is disabled. On the other hand, since the first and second address bar signals for the special MRS field are both high in the normal MRS, the node K3, which is the signal passing through the NOR gate 602 and the inverter 604, becomes high. Also, in the WCBR cycle, the first control signal is enabled because the signal output from the PWCBR is high and both the K2 and K3 nodes 616 and 618 are high. When the second control signal is enabled, it is enabled only when the normal MRS (burst length, burst type, CAS latency) is not satisfied. Therefore, there is no case where the first control signal and the second control signal are simultaneously enabled. The combination of the respective gates and addresses shown in FIG. 6 may have different structures and arrangements. That is, when the circuit constituting the MRS enable signal generator is the normal MRS, the first control signal is enabled and the second control signal is disabled.

7 is a diagram showing a detailed configuration of the normal MRS generator shown in FIG. In Fig. 7, reference numeral 72 denotes a transfer gate, and reference numerals 74 to 78 denote an inverter.

The operation of the apparatus shown in FIG. 7 will now be described.

When the address bar signal (low signal) for the normal MRS field is input to the transfer gate 72, the transfer gate 72 is turned on because the first control signal is in an enabled state. Therefore, the address bar signal for the normal MRS field passes through the transfer gate 72, and the inverted signal is inverted again by the inverter 76 to output a high signal, whereby the normal mode is set.

FIG. 8 is a detailed block diagram of the special MRS generator shown in FIG.

In Fig. 8, reference numeral 82 denotes a transfer gate, and reference numerals 84 to 88 denote inverters.

The operation of the apparatus shown in FIG. 8 will be described below.

When a special MRS field address bar signal (high) is input to the transfer gate 82, the second transfer gate 82 is turned off because the second control signal is disabled. Therefore, the address bar signal for the special MRS field can not pass through the transfer gate 82.

7 and 8, the normal MRS generator and the special MRS generator cause the normal MRS field address signal to be set to the normal mode by the first control signal and the special MRS field address signal to be blocked by the second control signal , And can be realized in various structures. There may also be various combinations of addresses input to each MRS generator.

As described above, according to the present invention, it is possible to solve the problem that the special MRS address must be applied at a low level when setting the normal MRS, so that the special MRS address does not affect the normal MRS regardless of the information.

Claims (4)

A PWCBR generator for inputting / CAS, / RAS and / WE signals to output a write enable CBR signal; An MRS enable signal for generating a first control signal for enabling the normal mode and a second control signal for disabling the special mode, receiving the signal output from the PWCBR generator, the normal MRS address signal, and the special MRS address signal, Signal generator; A normal MRS generator for setting the normal mode by controlling the normal MRS address signal by the first control signal; And And a special MRS generator in which the special MRS address signal is controlled by the second control signal so that the special mode is not set, thereby controlling the special mode. The apparatus of claim 1, wherein the MRS enable signal generator comprises: A first NAND gate for receiving a predetermined number of normal MRS address signals and performing logical AND; A NOR gate for receiving a special MRS address signal and performing a logical sum; A second NAND gate for performing an AND operation on a signal output from the first NAND gate, a signal obtained by inverting a signal output from the NOR gate, and a signal output from the PWCBR generator; A first inverter for inverting a signal output from the second NAND gate and outputting the first control signal; A third NAND gate for performing an AND operation on a signal output from the NOR gate, a signal obtained by inverting a signal output from the first NAND gate, and a signal output from the PWCBR generator; And And a second inverter for inverting a signal output from the third NAND gate to output the second control signal to control the special mode. The apparatus of claim 1, wherein the normal MRS generator comprises: A transfer gate which is controlled so that a signal input from the normal MRS address is passed by the first control signal; And a latch circuit for temporarily storing a signal output from said transfer gate and setting a normal mode, wherein said special mode is controlled. The apparatus of claim 1, wherein the special MRS generator comprises: And a transfer gate which is controlled so that a signal input from the special MRS address is intercepted by the second control signal to control the special mode.