CN109039514B

CN109039514B - Method for improving IEEE1588 timestamp precision

Info

Publication number: CN109039514B
Application number: CN201810797841.8A
Authority: CN
Inventors: 徐宁
Original assignee: Fiberhome Telecommunication Technologies Co Ltd; Wuhan Fisilink Microelectronics Technology Co Ltd
Current assignee: Wuhan Binary Semiconductor Co ltd
Priority date: 2018-07-19
Filing date: 2018-07-19
Publication date: 2020-02-11
Anticipated expiration: 2038-07-19
Also published as: CN109039514A

Abstract

A method for improving IEEE1588 timestamp precision relates to the field of PTN/IPRAN systems, and comprises the following steps: in the receiving direction, correcting the receiving timestamp by adopting a receiving delay correction value; the receiving the delay correction value comprises in a receiving direction: FIFO delay, port rate correction value and clock domain switching related correction value; in the sending direction, correcting the sending timestamp by adopting a sending delay correction value; the transmission delay correction value comprises a FIFO delay and port rate correction value in the transmission direction; the invention can improve the precision of the time stamp, and compensate the time delay from the MAC to the PCS in real time, thereby achieving more accurate time synchronization.

Description

Method for improving IEEE1588 timestamp precision

Technical Field

The invention relates to the field of Packet Transport Network (PTN)/internet protocol access Network (IP) systems, in particular to a method for improving the precision of an IEEE1588 timestamp.

Background

IP is the development trend of future network services, and ethernet is the main development direction of IP-based bearer networks due to its superior performance/cost ratio, wide application and product support. How to solve the clock synchronization problem is an aspect to be considered when deploying carrier ethernet. Currently, there are two aspects to the synchronization requirements of packet networks:

(1) the packet network can carry TDM (Time Division multiplexing) services and provide a mechanism for recovering TDM service clocks, so that the TDM services still meet certain performance indexes after traversing the packet network.

(2) Packet networks can provide a high precision network reference clock, like TDM networks, to meet the synchronization requirements of network nodes or terminals.

In a packet transmission network, a unified standard protocol is needed to realize multi-vendor cooperation. However, the traditional NTP (Network Time Protocol) can only realize Time synchronization at ms level, and satellite synchronization methods such as GPS (global positioning System) have many limitations, and cannot meet more and more high-precision Time synchronization requirements.

Synchronous ethernet (SyncE) is therefore the latest standard solution. In SyncE, ethernet synchronizes its bit clock with a high quality, trackable primary reference clock signal in the same manner as SONET (Synchronous Optical Network)/SDH (Synchronous digital hierarchy).

In 2006, the international telecommunications union described the SyncE concept in its g.8261. In 2007, the performance requirements of SyncE were standardized in g.8262, specifying the minimum performance requirements for clocks used in synchronous ethernet network devices. The IEEE1588 standard was released in 2002, and a new version of IEEE1588, namely IEEE1588v2, was made in 2005. Its basic function is to keep the most accurate clock within the distributed network in sync with other clocks. It defines a Precision Time Protocol PTP (Precision Time Protocol) for sub-microsecond synchronization of clocks in sensors, actuators and other terminals in a standard ethernet or other distributed bus systems using multicast technology.

IEEE1588 obtains more accurate timing synchronization through the cooperation of hardware and software, does not need extra clock lines when transmitting time and clock signals, still uses the data lines of the original Ethernet to transmit the clock signals, simplifies networking connection and reduces cost. IEEE1588 defines a set of synchronization protocols based on messages in the technical specification, and by periodically issuing information packets with time stamps, the clocks of nodes on each network can be corrected, thereby realizing the synchronous operation of the whole system.

The IEEE1588 protocol requires that the time of the timestamp is the time when the device receives or sends a data packet on a transmission Medium, but for technical reasons, in general implementation, the timestamp can only be inserted and detected in a MAC (media Access Control) function module of the device, and therefore the inserted timestamp does not cover a delay from the MAC module of the device to a PCS (Physical Coding Sublayer), which brings an error of timestamp precision.

In order to solve the error, measures need to be taken to compensate the delay from the MAC module to the PCS part, and the currently adopted compensation mode is to insert a fixed compensation value, but this cannot accurately reflect the delay variation on the PCS, especially when there is FIFO (First Input First Output) buffering in the PCS.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method for improving the precision of an IEEE1588 timestamp, which is used for compensating the time delay from an MAC to a PCS part in real time, improving the precision of the timestamp and achieving more accurate time synchronization.

In order to achieve the above object, the present invention provides a method for improving the accuracy of IEEE1588 timestamp, comprising: in the receiving direction, correcting the receiving timestamp by adopting a receiving delay correction value; the receiving the delay correction value comprises in a receiving direction: FIFO delay, port rate correction values and clock domain switching related correction values.

On the basis of the technical scheme, the FIFO delay in the receiving direction is obtained by multiplying the FIFO real-time data depth in the receiving direction by the FIFO data rate coefficient in the receiving direction.

On the basis of the above technical solution, the port rate correction value in the receiving direction is equal to the receiving direction Serdes phase calculation correction value + receiving direction port rate correction coefficient + receiving direction port write error-receiving direction FIFO write rate correction value.

On the basis of the technical scheme, the Serdes phase calculation correction value represents the delay difference generated by different Serdes bit widths; the receiving direction port rate correction coefficient represents the fixed delay on the whole PCS receiving data channel and is related to the data rate; the receiving direction port writes error records as follows: starting from a frame start character SFD to a write interface of the FIFO in the receiving direction until the SFD writes in the receiving delay of the FIFO; the receiving direction FIFO writing rate correction value represents a correction value for correcting the receiving direction delay under different FIFO bit widths and clock frequencies.

On the basis of the technical scheme, the clock domain switching related correction value in the receiving direction is a correction value for generating time delay for inserting or deleting the IDLE code.

On the basis of the technical scheme, the clock domain switching related correction value is adjusted according to the clock frequency error measurement result;

when IDLE code insertion/deletion occurs, adopting a real-time measurement result of the clock frequency error;

when there is no IDLE code insertion/deletion, the smoothing result of the clock frequency error is employed.

On the basis of the technical scheme, the method is suitable for the Ethernet with the data channel rates of 100M, 1G, 10G and 25G.

The invention also provides a method for improving the precision of the IEEE1588 timestamp, which comprises the following steps: in the sending direction, correcting the sending timestamp by adopting a sending delay correction value; the transmission delay correction value comprises a FIFO delay and port rate correction value in the transmission direction.

On the basis of the technical scheme, the FIFO delay in the sending direction is obtained by the FIFO real-time data depth in the sending direction multiplied by the FIFO data rate coefficient in the sending direction.

On the basis of the technical scheme, the port rate correction value in the sending direction comprises a port rate correction coefficient in the sending direction and a Serdes phase calculation correction value; the port rate correction coefficient represents the fixed delay on the data channel sent by the PCS of the whole Ethernet physical coding sublayer and is related to the data rate; the Serdes phase calculation correction values for the transmit direction represent the delay differences that result from different Serdes bit widths.

The invention has the beneficial effects that:

1. by measuring the real-time delay of the PCS layer and transmitting the measurement information to the MAC module, the MAC module compensates according to the measurement when performing time stamp operation, so that the requirement of accurate nanosecond time synchronization is met.

2. In the receiving direction, under the condition of IDLE code insertion/deletion, the frequency error (ppm) is measured by two counters, one is accumulated under a line clock, and the other is accumulated under a system clock, so that the calculation accuracy can be increased, and a PTP clock can be adopted to sample the deviation of the accumulated value of the line clock and the system clock at the same time in real time, so that the measurement is more accurate.

3. The invention can be compatible with time stamps with different rates and is suitable for Ethernet with different data channel rates, such as 100M, 1G, 10G and 25G.

Drawings

FIG. 1 is a flow chart of a receiving direction of the first embodiment

Fig. 2 is a flow chart of the sixth embodiment in the transmission direction.

Detailed Description

The terms and explanations related to the present invention are as follows:

initial delay correction value: latency _ adj;

FIFO delay: latency _ adj _ fifo;

port rate correction value: latency _ adj _ speed;

FIFO real-time data depth: latency _ adj _ w;

FIFO data rate coefficient: speed _ multiplier;

port rate correction value: latency _ adj _ speed;

receive direction Serdes phase calculation correction value: phase _ calc _ adj _ reg;

port rate correction factor: latency _ adj _ speed _ const;

port write error: wren _ offset _ mac;

FIFO write rate correction value: wren _ offset _ adjust;

the intermediate delay correction value: latency _ adj _ reg;

clock frequency error smoothing result: ppm _ normal;

real-time measurement of clock frequency error: ppm;

receiving a delay correction value: rx _ latency _ adj;

the receiving direction deletes the time delay generated by the IDLE code: octet _ del _ num;

the receiving direction inserts the delay generated by the IDLE code: octet _ ins _ num;

sending a delay correction value: tx _ latency _ adj;

transmit direction Serdes phase calculation correction value: latency _ adj _ device _ const.

In the following description of the embodiments of the present invention, terms with the same name of transmitting direction and receiving direction are distinguished by transmitting or receiving in order to describe the content of the present invention more clearly.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

First embodiment

This embodiment provides a method for improving accuracy of an IEEE1588 timestamp, where in a receiving direction, a receiving delay modification value of a data channel is used to modify a receiving timestamp to compensate for a delay of a PTP frame, where the receiving delay modification value includes in the receiving direction: FIFO delay, port rate correction values and clock domain switching related correction values.

Since in the receive direction FIFO (read direction of FIFO), in order to adapt to deviations of the line side and the system measurement data rate, an IDLE byte (sliding code) is discarded or inserted when the pipeline of the receive direction FIFO is greater or less than a certain value, which has an effect on the latency of the FIFO.

Therefore, the clock domain switching related correction value in the reception direction is a correction value that causes a delay for inserting or deleting the IDLE code. The delay generated by deleting data in the receiving direction or the delay generated by inserting data in the receiving direction is determined by an inserting/deleting indication signal in the receiving direction FIFO; when the indication signal is inserted, the time delay generated by inserting the IDLE code in the receiving direction is adopted; when the indication signal is deleting, the time delay generated by deleting the IDLE code in the receiving direction is adopted.

Specifically, as shown in fig. 1, the receive delay correction value is calculated, and then the receive timestamp is corrected by using the receive delay correction value.

Receiving a receiving delay correction value, namely receiving direction FIFO delay, receiving direction port rate correction value and receiving direction deleting IDLE code generated delay;

that is, rx _ latency _ adj is the reception direction latency _ adj _ fifo + the reception direction latency _ adj _ speed-the reception direction octet _ del _ num.

Or, the receiving delay correction value is the receiving direction FIFO delay + the receiving direction port rate correction value + the delay generated by the receiving direction insert IDLE code;

that is, rx _ latency _ adj is the reception direction latency _ adj _ fifo + reception direction latency _ adj _ speed + reception direction octet _ ins _ num.

Second embodiment

In this embodiment, based on the first embodiment, the receive direction FIFO delay (receive direction latency _ adj _ FIFO) represents the dynamic delay generated by the data stored in real time in the receive direction FIFO.

Specifically, the receive direction FIFO latency is the receive direction FIFO real-time data depth x the receive direction FIFO data rate coefficient, i.e.,

the reception direction latency _ adj _ fifo is the reception direction latency _ adj _ w × the reception direction speed _ multiplexer. Wherein, the data rate coefficient of the reception direction lFIFO represents the equivalent delay size of the unit word length under different data rates.

Third embodiment

This embodiment is based on the second embodiment, and the port rate correction value in the reception direction, i.e., the reception direction Serdes phase calculation correction value + the reception direction port rate correction coefficient + the reception direction port write error-reception direction FIFO write rate correction value, that is,

the reception direction latency _ adj _ speed is the reception direction phase _ calc _ adj _ reg + the reception direction latency _ adj _ speed _ const + the reception direction wren _ offset _ mac-the reception direction wren _ offset _ adjust.

The receive direction Serdes phase calculation correction value (receive direction phase _ calc _ a dj _ reg) is a constant, and represents the delay difference caused by different Serdes bit widths. When different Serdes interface IPs are adopted for serial-parallel conversion, the time required by serial-parallel conversion is different due to the fact that different data bit widths are used, and therefore the delay difference is different.

The receiving direction port rate correction coefficient (receiving direction latency _ adj _ speed _ const) is a delay constant related to the rate of a receiving data channel, and represents a fixed delay on the whole PCS receiving data channel, and when the data channel works at 100M/1000M, the values of the delay constant are different. And when the data channel works at 1G, 10G or 25G, the delay constant can also select different values according to different rates.

The port write error in the receive direction (receive direction wren _ offset _ mac) records: starting from the arrival of the frame start symbol SFD (0xD5) at the write interface of the receive direction FIFO until the receive delay of the SFD writing into the receive direction FIFO; i.e., receive latency due to periods of no operations inserted on the asynchronous FIFO when the SFD (0xD5) enters the receive FIFO.

The receive delay includes several components, first, the receive direction FIFO needs to assemble the received data bytes into a data word (whose bit width is determined by the FIFO's data bit width) and then write into the receive direction FIFO, where the location of the SFD in this data word is determined by the time of arrival of the SFD. However, after the arrival of the SFD, it may be necessary to wait for the arrival of the subsequent data to complete the assembly of the data word, and thus the reception delay varies. Second, due to the different rates, at low rates the FIFO is not required to write every beat. Thus, the time from the arrival of the SFD to the completion of the assembly of the data word in which it is located to the actual writing of this data word into the FIFO, as required by the rate adaptation, varies, and the reception delay experienced by each SFD may vary.

The reception direction FIFO write rate correction value (wren _ offset _ adjust) indicates a correction value for correcting the reception delay at different data rates.

Fourth embodiment

On the basis of the third embodiment, in this embodiment, for the case where the insert/delete IDLE code occurs, the clock domain switching related correction value in the receiving direction may also take the clock frequency error measurement result (ppm) into consideration and be adjusted according to the clock frequency error measurement result.

In this embodiment, the clock frequency error measurement result is a real-time measurement result of the clock frequency error, and then, the reception delay correction value is the reception direction FIFO delay + the reception direction port rate correction value-the real-time measurement result of the clock frequency error-the delay generated by the reception direction delete IDLE code; that is to say that the first and second electrodes,

rx _ latency _ adj is the reception direction latency _ adj _ fifo + reception direction latency _ adj _ speed-ppm-reception direction octet _ del _ num.

Wherein, ppm is the frequency deviation of the line receiving clock and the system clock obtained by measurement. When measuring frequency deviation, two counters are adopted, one counter is accumulated under a line clock, and the other counter is accumulated under a system clock. Another independent PTP clock can be adopted to sample the deviation of accumulated values of the two counters at the same time in real time, and then the frequency deviation of the line receiving clock and the system clock is obtained. Because the adopted PTP clock can be independent of the line clock and the system clock, the measured frequency offset can be more accurate.

Fifth embodiment

On the basis of the third embodiment, in this embodiment, in the case where the IDLE code insertion/deletion does not occur, the clock domain switching related correction value in the receiving direction may also take the clock frequency error measurement result into consideration and be adjusted according to the clock frequency error measurement result.

In the present embodiment, the clock frequency error measurement result is a smoothed result of the clock frequency error (ppm _ normal). The difference between ppm _ normal and ppm in the fourth embodiment is that ppm is an instantaneous value of frequency offset when IDLE code insertion/deletion occurs, and ppm _ normal is a smoothed average value for correcting delay when IDLE code insertion/deletion does not occur.

Then, the receive delay correction value is receive direction FIFO delay + receive direction port rate correction value-real time measurement of clock frequency error-delay generated by the receive direction delete IDLE code; that is to say that the first and second electrodes,

rx _ latency _ adj ═ receive direction latency _ adj _ fifo + receive direction latency _ adj _ speed-ppm _ normal-receive direction octet _ del _ num.

Sixth embodiment

On the basis of any one of the above embodiments, in this embodiment, as shown in fig. 2, in the sending direction, the sending delay correction value is calculated first, and then the sending timestamp is corrected by using the sending delay correction value. The transmit latency modification value includes a transmit direction FIFO latency and a transmit direction port rate modification value.

The transmission direction delay correction value is transmission direction FIFO delay + transmission direction Serdes phase calculation correction value + transmission direction port rate correction coefficient; that is to say that the first and second electrodes,

tx _ latency _ adj is the transmission direction latency _ adj _ fifo + transmission direction latency _ adj _ device _ const + transmission direction latency _ adj _ speed _ const.

The transmission-direction FIFO delay (transmission direction latency _ adj _ FIFO) represents a dynamic delay caused by data stored in real time in the transmission-direction FIFO.

The transmit direction FIFO latency is the transmit direction FIFO real-time data depth x the transmit direction FIFO data rate coefficient, i.e.,

the transmission direction latency _ adj _ fifo is the transmission direction latency _ adj _ w × transmission speed _ multiplexer.

The transmit direction Serdes phase calculation correction value (latency _ adj _ device _ const) is a constant, has the same meaning as the receive direction Serdes phase calculation correction value (phase _ calc _ adj _ reg), and represents a delay difference generated by using different Serdes bit widths, but the measured value is different.

The transmission direction port rate correction coefficient (latency _ adj _ speed _ const) is a delay constant related to the rate of a transmission data channel, and represents the fixed delay on the transmission data channel of the entire physical coding sublayer PCS of the Ethernet, and when the data channel works at 100M/1000M, the values of the delay constant are different. This delay constant takes on different values. And when the data channel works at 1G, 10G or 25G, the delay constant can also select different values according to different rates.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.

Claims

1. A method for improving the precision of IEEE1588 timestamp, comprising:

in the receiving direction, correcting the receiving timestamp by adopting a receiving delay correction value;

the receiving the delay correction value comprises in a receiving direction: FIFO delay of the first-in first-out queue, port rate correction value and clock domain switching related correction value;

the port rate correction value in the receiving direction is equal to a receiving direction Serdes phase calculation correction value + a receiving direction port rate correction coefficient + a receiving direction port write error-a receiving direction FIFO write rate correction value;

the Serdes phase calculation correction values represent the delay differences produced by different Serdes bit widths; the receiving direction port writes error records as follows: starting from the frame start symbol SFD arriving at the write interface of the FIFO in the receive direction until the receive delay of the SFD writing into the FIFO.

2. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 1, wherein: the FIFO delay in the receiving direction is obtained by multiplying the real-time data depth of the FIFO in the receiving direction by the FIFO data rate coefficient in the receiving direction.

3. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 1, wherein:

the receiving direction port rate correction coefficient represents the fixed delay on the whole PCS receiving data channel and is related to the data rate;

the receiving direction FIFO writing rate correction value represents a correction value for correcting the receiving direction delay under different FIFO bit widths and clock frequencies.

4. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 1, wherein: the correction value related to the clock domain switching in the receiving direction is a correction value for generating a delay time for inserting or deleting an IDLE code.

5. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 4, wherein said clock domain switching related corrections value are adjusted based on a clock frequency error measurement;

6. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 1, wherein: the method is applicable to Ethernet networks with data channel rates of 100M, 1G, 10G and 25G.

7. A method for improving the precision of IEEE1588 timestamp, comprising:

in the sending direction, correcting the sending timestamp by adopting a sending delay correction value;

the transmission delay correction value comprises a FIFO delay and port rate correction value in the transmission direction;

the port rate correction value in the sending direction comprises a port rate correction coefficient in the sending direction and a Serdes phase calculation correction value;

the port rate correction coefficient represents the fixed delay on the data channel sent by the PCS of the whole Ethernet physical coding sublayer and is related to the data rate;

the Serdes phase calculation correction values for the transmit direction represent the delay differences that result from different Serdes bit widths.

8. The method of improving the accuracy of IEEE1588 timestamps as claimed in claim 7, wherein: the FIFO delay in the sending direction is obtained by the FIFO real-time data depth in the sending direction multiplied by the FIFO data rate coefficient in the sending direction.