CN107528654A - It is a kind of based on 1588 method for synchronizing time and device - Google Patents
It is a kind of based on 1588 method for synchronizing time and device Download PDFInfo
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- CN107528654A CN107528654A CN201610448854.5A CN201610448854A CN107528654A CN 107528654 A CN107528654 A CN 107528654A CN 201610448854 A CN201610448854 A CN 201610448854A CN 107528654 A CN107528654 A CN 107528654A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/067—Details of the timestamp structure
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of based on 1588 method for synchronizing time and system, it is related to the communications field, methods described includes：By carrying out detection process to the phase difference of system clock and line clock, the phase difference between the system clock and the line clock is obtained；Under line clock, the time difference of rising edge corresponding to the heading mark of 1588 messages and the rising edge of line clock current period is determined；Under system clock, the generation timestamp related to 1588 message；Using the phase difference and the time difference, the timestamp generated is compensated, is allowed to consistent with line clock.Compensated by a pair timestamp related to 1588 messages, make the timestamp after compensation consistent with line clock, reach the purpose of precise synchronization.
Description
Technical field
It is more particularly to a kind of based on 1588 method for synchronizing time and device the present invention relates to the communications field.
Background technology
With the continuous development of the communication technology, higher requirement is proposed to time synchronized performance, such as, recent people carry
What is gone out provides positioning service requirement using base station, and time precision requirement is in ± 200ns or so, the upgrade version of Long Term Evolution
The key technology multi-point cooperative transmission processing of (Long Term Evolution-Advanced, LTE-Advanced)
The relative time essence between adjacent base station is required in (Coordinated Multipoint Joint Processing, CoMP-JP)
Degree is in ± 500ns or so；Following 5th third-generation mobile communication technology (The 5th Generation Mobile
Communication Technology, 5G) system, it may be necessary to the superhigh precision time synchronized demand of hundreds of ns magnitudes；Again
Such as, Technique on Quantum Communication more at a specified future date is, it is necessary to the high time measurement technology of precision, to reduce the error code of quantum communication system
Rate, it is improved into code check, it may be necessary to the timing tracking accuracy within hundred ns.
At present, the precise synchronization realized based on 1588v2 technologies, the time synchronized demand of us magnitudes can only be met,
But the even more high-precision time synchronized demands of above-mentioned hundreds of ns can not be met.
The content of the invention
The technical problem that the technical scheme provided according to embodiments of the present invention solves is to overcome in existing simultaneous techniques to exist
Synchronization accuracy it is relatively low the problem of and defect.
What is provided according to embodiments of the present invention is a kind of based on 1588 method for synchronizing time, including：
According to system clock and line clock, the phase difference between the system clock and the line clock is obtained；
Under line clock, rising edge corresponding to the heading mark of 1588 messages and line clock current period are determined
The time difference of rising edge；
Under system clock, the generation timestamp related to 1588 message；
Using the phase difference and the time difference, the timestamp generated is compensated, is allowed to and line clock one
Cause.
Preferably, it is described under line clock, when determining rising edge corresponding to the heading mark of 1588 messages with circuit
Before the step of time difference of the rising edge of clock current period, in addition to：
Under line clock, the heading mark of 1588 message is generated, and the heading mark generated is sent
To system clock domain.
Preferably, it is described under line clock, when determining rising edge corresponding to the heading mark of 1588 messages with circuit
The step of time difference of the rising edge of clock current period, includes：
Under line clock, the current period of rising edge and the line clock corresponding to the heading mark is detected
Rising edge；
According to the rising of the current period of rising edge and the line clock corresponding to the heading mark detected
Edge, determine the time difference of the rising edge of the current period of rising edge and the line clock corresponding to the heading mark.
Preferably, it is described under system clock, include the step of generation related to 1588 message timestamp：
Under system clock, the heading mark is received, and by carrying out timestamp to the heading mark received
Sampling, obtains the timestamp related to 1588 message.
Preferably, it is described utilize the phase difference and the time difference, the timestamp generated is compensated, be allowed to
The consistent step of line clock includes：
Compare the phase difference and the time difference；
If the phase difference is more than the time difference, the timestamp and the phase difference are subtracted each other, after being compensated
Timestamp；
Otherwise, the timestamp and the phase difference, system clock cycle are subtracted each other, the timestamp after being compensated.
The storage medium provided according to embodiments of the present invention, it stores above-mentioned based on 1588 time synchronized side for realizing
The program of method.
What is provided according to embodiments of the present invention is a kind of based on 1588 time synchronism apparatus, including：
Phase difference detection module, for according to system clock and line clock, obtaining the system clock and the circuit
Phase difference between clock.
Rising edge detection module, under line clock, determine rising edge and line corresponding to the heading mark of 1588 messages
The time difference of the rising edge of road clock current period；
Timestamp sampling module, under system clock, generating the timestamp related to 1588 message；
Timestamp compensating module, for utilizing the phase difference and the time difference, the timestamp generated is mended
Repay, be allowed to consistent with line clock.
Preferably, in addition to：
PMA/PCS modules, under line clock, generating the heading mark of 1588 message, and it will be generated
Heading mark send to system clock domain.
Preferably, the rising edge detection module detects rising edge corresponding to the heading mark under line clock
With the rising edge of the current period of the line clock, and rising edge and institute according to corresponding to the heading mark detected
The rising edge of the current period of line clock is stated, determines working as rising edge corresponding to the heading mark and the line clock
The time difference of the rising edge in preceding cycle.
Preferably, the timestamp sampling module is used under system clock, receives the heading mark, and by right
The heading mark received carries out timestamp sampling, obtains the timestamp related to 1588 message.
Preferably, the timestamp compensating module phase difference and the time difference, if the phase difference is more than
The time difference, then the timestamp and the phase difference are subtracted each other, the timestamp after being compensated, otherwise by the timestamp
Subtract each other with the phase difference, system clock cycle, the timestamp after being compensated.
Technical scheme provided in an embodiment of the present invention has the advantages that：
Compensate, make by using the phase difference pair of the system clock and line clock timestamp related to 1588 messages
Timestamp after compensation is consistent with line clock, reaches the purpose of precise synchronization.
Brief description of the drawings
Fig. 1 is first embodiment of the invention offer based on 1588 method for synchronizing time block diagram；
Fig. 2 is second embodiment of the invention offer based on 1588 time synchronism apparatus block diagram；
Fig. 3 is the module frame chart based on 1588 time synchronism apparatus that third embodiment of the invention provides；
Fig. 4 be fourth embodiment of the invention provide sof between line clock and system clock when timing diagram；
Fig. 5 is timing diagrams of the sof of fourth embodiment of the invention offer after system clock；
Fig. 6 is the block diagram that device is applied to GE power ports that fourth embodiment of the invention provides.
Embodiment
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail, it will be appreciated that described below is excellent
Select embodiment to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 1 be first embodiment of the invention provide based on 1588 method for synchronizing time block diagram, as shown in figure 1, step
Including：
Step S101：According to system clock and line clock, the phase difference between system clock and line clock is obtained.
Specifically, by carrying out phase difference detection to system clock and line clock, when obtaining system clock and circuit
Phase difference between clock.
Step S102：Under line clock, rising edge and line clock corresponding to the heading mark of 1588 messages are determined
The time difference of the rising edge of current period.
It is determined that before the time difference, under line clock, the heading mark of 1588 messages is generated, and will be generated
Heading mark send to system clock domain.Then, under line clock, rising edge corresponding to the heading mark is detected
With the rising edge of the current period of line clock, and rising edge and the line according to corresponding to the heading mark detected
The rising edge of the current period of road clock, determine the current week of rising edge and the line clock corresponding to the heading mark
The time difference of the rising edge of phase.That is, under line clock, heading mark, and detection or measured message leader are generated
The time difference of will rising edge and line clock current period rising edge, to utilize the resulting time difference, determine offset.
Step S103：Under system clock, the generation timestamp related to 1588 message.
Under system clock domain, heading mark is received, and adopt by carrying out timestamp to the heading mark received
Sample, obtain the timestamp related to 1588 messages, i.e., under system clock domain, after receiving heading mark, the of system clock
Time corresponding to one rising edge.
Step S104：Using phase difference, the timestamp generated is compensated, is allowed to consistent with line clock.
Specifically, phase difference and time difference are compared, if phase difference is more than the time difference, by timestamp and phase difference phase
Subtract, the timestamp after being compensated；Otherwise, timestamp and phase difference, system clock cycle are subtracted each other, the time after being compensated
Stamp.
For message transmitting party to the timestamp after resulting compensation is added in 1588 message as described
The transmission time of 1588 messages.
Direction is received for message, preserves the timestamp after resulting compensation, the reception as 1588 messages received
Time.
Can be with it will appreciated by the skilled person that realizing that all or part of step in above-described embodiment method is
The hardware of correlation is instructed to complete by program, described program can be stored in computer read/write memory medium, should
Program upon execution, including step S101 to step S104.Wherein, described storage medium can be ROM/RAM, magnetic disc, light
Disk etc..
Fig. 2 be second embodiment of the invention provide based on 1588 time synchronism apparatus block diagram, as shown in Fig. 2 including：
Phase difference detection module, for according to system clock and line clock, obtaining between system clock and line clock
Phase difference.
Rising edge detection module, under line clock, determine rising edge and line corresponding to the heading mark of 1588 messages
The time difference of the rising edge of road clock current period.
Timestamp sampling module, under system clock, generating the timestamp related to 1588 message.
Timestamp compensating module, for utilizing phase difference and the time difference, the timestamp generated is compensated, made
It is consistent with line clock.
Also include：
PMA/PCS modules, under line clock, generating the heading mark of 1588 messages, and the report that will be generated
Literary leader will is sent to system clock domain.
The operation principle of described device is as follows：
Message receives direction：PMA/PCS modules receive signal from line interface and carry out respective handling, obtain receiving report
Text, and the heading mark of the reception message is generated, send to timestamp sampling module and rising edge detection module.Rising edge
Detection module passes through the rising of the current period of rising edge and line clock corresponding to detection messages leader will under line clock
Edge, determines the time difference of the rising edge of the current period of rising edge and the line clock corresponding to heading mark, and sends
To timestamp compensating module.Timestamp sampling module receives heading mark, the message header under system time to being received
Will carries out timestamp sampling, obtains the timestamp related to 1588 messages, and send to timestamp compensating module, the timestamp
After receiving heading mark, rising time corresponding to next cycle rising edge of system clock.Timestamp compensating module ratio
Compared with phase difference and time difference, if phase difference is more than the time difference, timestamp and phase difference are subtracted each other, the time after being compensated
Stamp, otherwise subtracts each other timestamp and phase difference, system clock cycle, the timestamp after being compensated.Finally, after preserving the compensation
Timestamp, the reception time as the reception message.Above-mentioned reception message is 1588 messages received.
Message transmitting party receives to, PMA/PCS modules when sending message, generates the heading mark for sending message,
And send to timestamp sampling module and rising edge detection module.Rising edge detection module passes through detection messages under line clock
The rising edge of the current period of rising edge and line clock corresponding to leader will, determine rising edge corresponding to heading mark and institute
The time difference of the rising edge of the current period of line clock is stated, and is sent to timestamp compensating module.Timestamp sampling module is received
To heading mark, timestamp sampling is carried out to the heading mark received under system time, obtained and 1588 message phases
The timestamp of pass, and sending to timestamp compensating module, after the timestamp receives heading mark, system clock it is next
Rising time corresponding to cycle rising edge.Timestamp compensating module compares phase difference and time difference, if phase difference is more than the time
Difference, then timestamp and phase difference are subtracted each other, the timestamp after being compensated, otherwise by timestamp and phase difference, system clock week
Phase subtracts each other, the timestamp after being compensated.Finally, the timestamp after the compensation will be added to and send in message, as the transmission
The transmission time of message.Above-mentioned transmission message is 1588 messages sent.
Provided by the invention precision is high based on 1588 time synchronism apparatus, can reach ns the levels even synchronization of ps levels.
Fig. 3 is the module frame chart based on 1588 time synchronism apparatus that third embodiment of the invention provides, such as Fig. 3 institutes
Show, including 1588 send and receive packets modules, 1588 packet parsings and timestamp processing module, interface modular converter, PMA/PCS modules,
Timestamp sampling module and clock circuit, in addition to the detection of the phase difference detection module of line clock and system clock, rising edge
Module, comparison module and timestamp compensating module.The timestamp compensating module of Fig. 2 embodiments is divided into two parts by the present embodiment,
A part is the comparison module for comparing phase difference and time difference, and a part is to compensate mould for compensating the timestamp of timestamp
Block.
Wherein, 1588 send and receive packets modules are responsible for sending and receiving for 1588 messages；1588 packet parsings and timestamp processing
After module parses 1588 messages, in the message that addition timestamp is sent to 1588 send and receive packets modules, storage comes from interface conversion
The timestamp of the message of module, timestamp obtain from timestamp compensating module；Interface modular converter is substantially carried out interface conversion,
PMA/PCS message is transformed into system clock domain；The signal received from line interface is converted into 8bi t by PMA/PCS modules
Data, interface modular converter is issued, the message received from interface modular converter is converted into signal and is sent to line interface, simultaneously
Heading the mark receive_sof and send_sof of PMA/PCS modules generation transmitting-receiving message give timestamp sampling module and entered
Row timestamp samples, and delivers to rising edge detection module and determine rising edge corresponding to receive_sof or send_sof and described
The time difference of the rising edge of the current period of line clock.The timestamp that timestamp sampling module is sampled is given birth to by system clock
Into；Phase difference detection module carries out phase difference detection to system clock and line clock, obtains the phase difference of the two, gives and compare
Module；Comparison module compares phase difference and time difference, when timestamp compensating module is according to the comparative result pair of the comparison module
Between stab sampling module timestamp accordingly compensated, obtain high-precision timestamp.Clock circuit is used for synchronous source device
Clock, and generate system clock.
Receive_sof and send_sof (being referred to as sof below) generates in circuit clock zone, and its rising edge typically can all compare
Line clock lags.And the sof of actual message should be with line clock rising edge alignment, so wanting compensated line clock and system
The phase difference of clock, rather than the sof of generation and system clock rising edge difference.
Specific compensation way：The time of sof hysteresis line clocks is designated as Δ t2, line clock and system clock phase difference
It is designated as Δ t1.Fig. 4 be fourth embodiment of the invention provide sof between line clock and system clock when timing diagram, such as
Shown in Fig. 4, as 0≤Δ t2<During Δ t1, time stab is t2- Δs t1；Fig. 5 is that the sof that fourth embodiment of the invention provides exists
Timing diagram after system clock, as shown in figure 5, working as Δ t2>During=Δ t1, time stab is t3-Tclk_sys- Δs t1, Tclk_
Sys is clk_sys clock cycle.
Direction is received for message：PMA/PCS modules are handled the signal received from line interface, and will be obtained
Message is received to send to interface modular converter；The heading mark receive_sof of message is generated, receive_sof is sent
To rising edge detection module and timestamp sampling module.Rising edge detection module measures receive_sof pairs under line clock
The rising edge answered and the time difference of the rising edge of the current period of the line clock, and send to comparison module.Timestamp is adopted
Egf block carries out timestamp sampling under system clock to the receive_sof that is received, when obtaining related to 1588 messages
Between stab, and send to timestamp compensating module, after the timestamp receives receive_sof, next cycle of system clock
Rising time corresponding to rising edge.Timestamp compensating module using comparison module to phase difference and the comparative result of time difference,
Timestamp from timestamp sampling module is compensated, obtains high-precision timestamp, that is to say, that if phase difference is more than
Time difference, then timestamp and phase difference are subtracted each other, the timestamp after being compensated, otherwise by timestamp and when phase difference, system
The clock cycle subtracts each other, the timestamp after being compensated, and the timestamp after the compensation is sent to 1588 packet parsings and timestamp processing
Module.Finally, 1588 packet parsings and timestamp processing module receive interface modular converter and are transformed into system from line clock domain
The reception message of clock zone, if it is 1588 messages to parse the message, after preserving the compensation obtained from timestamp compensating module
Timestamp, the reception time as 1588 message.
For message transmitting party to：1588 packet parsings and timestamp processing module are received from 1588 send and receive packets modules
Message is sent, and the message is sent to interface modular converter.The message is transformed into by interface modular converter from system clock domain
Behind line clock domain, send to PMA/PCS modules.PMA/PCS modules from interface modular converter receive send message when, generation should
The heading mark send_sof of message is sent, and is sent to rising edge detection module and timestamp sampling module.Rising edge is examined
Survey module measures the rising edge of the current period of rising edge and the line clock corresponding to send_sof under line clock
Time difference, and send to comparison module.Timestamp sampling module carries out the time under system clock to the send_sof received
Stamp sampling, the timestamp related to 1588 messages is obtained, and send to timestamp compensating module, the timestamp and receive
After send_sof, rising time corresponding to next cycle rising edge of system clock.Timestamp compensating module, which utilizes, compares mould
For block to phase difference and the comparative result of time difference, progress timestamp compensation specifically, will if phase difference is more than the time difference
Timestamp subtracts each other with phase difference, the timestamp after being compensated, otherwise subtracts each other timestamp and phase difference, system clock cycle,
Timestamp after being compensated, timestamp compensating module send the timestamp after compensating to 1588 packet parsings and timestamp
Processing module.Because message has certain length, therefore 1588 packet parsings and timestamp processing module are it is determined that the transmission report
After text is 1588 messages, timestamp after the compensation that will be obtained from timestamp compensating module is added in 1588 message, as
The transmission time of 1588 message.
Phase difference detection precision is higher, and timestamp precision is higher, and the precision of 1588 time synchronizeds is also higher.Phase difference detection
It can be realized using high-frequency clock or TDC technologies, 1588 synchronization accuracies can be made to reach ns levels, or even ps levels.
Fig. 6 be fourth embodiment of the invention provide device is applied to the block diagram of GE power ports, as shown in fig. 6, this is sent out
The device of bright embodiment is applied to GE power ports, and its hardware module part includes：
PMA/PCS modules：Direction is received, from GE power port reception signals, is AD converted, digital equalising, decodes, obtains
8bit parallel data, while generate and receive heading mark receive_sof；Sending direction, 8bit parallel datas are carried out
Encode, shaping, then DA is converted into analog signal, is sent by GE power ports, and generates and send heading mark send_
sof；Ensure send_sof/receive_sof, generating between position and GE power ports does not have fifo.
Interface modular converter：Clock zone and general line system are carried out, that is, is carried out between system clock domain and line clock domain
Signal is changed.
1588 packet parsings and timestamp processing module：It is responsible for packet parsing, after recognizing 1588 messages, carries out corresponding
Timestamp processing.
1588 send and receive packets modules：Transmission, response and termination including 1588 messages.
Timestamp sampling module：First, there is the Time Stamp Counter under a system 125M clock, work as receive_sof
Or liter recorded thereon compensates along timestamp, the timestamp of record, time of delivery (TOD) stamp compensating module during send_sof arrivals.
Phase difference detection module：The phase difference of detecting system 125M clocks and circuit 125M clocks, the phase difference is in clock
It is fixed value during locking, its detection needs high accuracy, can be realized with high-frequency clock or TDC technologies.
Rising edge detection module：Working as rising edge and the line clock corresponding to send_sof is determined under line clock
The time difference of the rising edge in preceding cycle.
Comparison module：Compare the time difference that the phase difference of phase difference detection module determination and rising edge detection module determine.
Timestamp compensating module：Sof generation and timestamp sampling use different low-frequency clocks, precision it is relatively low, it is necessary to
The phase difference of two clocks is compensated, phase difference precision is higher, and the timestamp after compensation is more accurate.During specific compensation, according to comparing
The comparative result of module, using no compensation way.
In the present embodiment, the precision of timestamp sampling is 8ns, when phase difference detection precision reaches 100ps, after compensation
Timestamp precision can bring up to 100ps.
Phaselocked loop and clock chip (equivalent to clock circuit)：Synchronous source device clock, and generate system clock.Clock
The stability of synchronization accuracy and caused system clock, directly affect phase difference detection precision, and then influence time stamp precision
And timing tracking accuracy, it is therefore desirable to high performance phaselocked loop and clock chip.
Although the present invention is described in detail above, the invention is not restricted to this, those skilled in the art of the present technique
Various modifications can be carried out according to the principle of the present invention.Therefore, all modifications made according to the principle of the invention, all should be understood to
Fall into protection scope of the present invention.
Claims (10)
1. it is a kind of based on 1588 method for synchronizing time, including：
According to system clock and line clock, the phase difference between the system clock and the line clock is obtained；
Under line clock, the rising of rising edge corresponding to the heading mark of 1588 messages and line clock current period is determined
The time difference on edge；
Under system clock, the generation timestamp related to 1588 message；
Using the phase difference and the time difference, the timestamp generated is compensated, is allowed to consistent with line clock.
2. it is according to the method for claim 1, described under line clock, determine corresponding to the heading mark of 1588 messages
Before the step of time difference of rising edge and the rising edge of line clock current period, in addition to：
Under line clock, the heading mark of 1588 message is generated, and the heading mark generated is sent to being
System clock zone.
3. it is according to the method for claim 2, described under line clock, determine corresponding to the heading mark of 1588 messages
The step of time difference of rising edge and the rising edge of line clock current period, includes：
Under line clock, the rising of the current period of rising edge and the line clock corresponding to the heading mark is detected
Edge；
According to the rising edge of the current period of rising edge and the line clock corresponding to the heading mark detected, really
The time difference of the rising edge of the current period of rising edge and the line clock corresponding to the fixed heading mark.
4. according to the method in claim 2 or 3, described under system clock, generation it is related to 1588 message when
Between stab the step of include：
Under system clock, the heading mark is received, and by carrying out timestamp sampling to the heading mark received,
Obtain the timestamp related to 1588 message.
5. according to the method for claim 1, described utilize the phase difference and the time difference, to the timestamp generated
Compensate, the step for being allowed to consistent with line clock includes：
Compare the phase difference and the time difference；
If the phase difference is more than the time difference, the timestamp and the phase difference are subtracted each other, after being compensated when
Between stab；
Otherwise, the timestamp and the phase difference, system clock cycle are subtracted each other, the timestamp after being compensated.
6. it is a kind of based on 1588 time synchronism apparatus, including：
Phase difference detection module, for according to system clock and line clock, obtaining the system clock and the line clock
Between phase difference.
Rising edge detection module, under line clock, when determining rising edge corresponding to the heading mark of 1588 messages with circuit
The time difference of the rising edge of clock current period；
Timestamp sampling module, under system clock, generating the timestamp related to 1588 message；
Timestamp compensating module, for utilizing the phase difference and the time difference, the timestamp generated is compensated, made
It is consistent with line clock.
7. device according to claim 6, in addition to：
PMA/PCS modules, under line clock, generating the heading mark of 1588 message, and the report that will be generated
Literary leader will is sent to system clock domain.
8. device according to claim 7, the rising edge detection module detects the message header under line clock
The rising edge of the current period of rising edge corresponding to will and the line clock, and according to the heading mark pair detected
The rising edge and the rising edge of the current period of the line clock answered, determine rising edge and institute corresponding to the heading mark
State the time difference of the rising edge of the current period of line clock.
9. the device according to claim 7 or 8, the timestamp sampling module is used under system clock, described in reception
Heading mark, and by carrying out timestamp sampling to the heading mark received, obtain related to 1588 message
Timestamp.
10. device according to claim 9, the timestamp compensating module phase difference and the time difference,
If the phase difference is more than the time difference, the timestamp and the phase difference are subtracted each other, the timestamp after being compensated,
Otherwise the timestamp and the phase difference, system clock cycle are subtracted each other, the timestamp after being compensated.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610448854.5A CN107528654B (en) | 2016-06-21 | 2016-06-21 | 1588-based time synchronization method and device |
| PCT/CN2017/087861 WO2017219881A1 (en) | 2016-06-21 | 2017-06-12 | Method and device for time synchronization based on 1588 standard |
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| CN201610448854.5A CN107528654B (en) | 2016-06-21 | 2016-06-21 | 1588-based time synchronization method and device |
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Cited By (9)
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| WO2019165965A1 (en) * | 2018-03-01 | 2019-09-06 | 中兴通讯股份有限公司 | Method, apparatus, and device for determining time information |
| CN110290580A (en) * | 2019-06-05 | 2019-09-27 | 深圳市英特瑞半导体科技有限公司 | A kind of method and its system based on 1588 agreement passing times |
| WO2020108202A1 (en) * | 2018-11-28 | 2020-06-04 | 中兴通讯股份有限公司 | Timestamp acquisition method and time synchronization system |
| CN111800212A (en) * | 2020-06-12 | 2020-10-20 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and device |
| CN112235067A (en) * | 2020-09-24 | 2021-01-15 | 烽火通信科技股份有限公司 | Centralized 1588 time synchronization method and time synchronization system |
| CN112953669A (en) * | 2019-12-11 | 2021-06-11 | 烽火通信科技股份有限公司 | Method and system for improving timestamp precision |
| CN113206665A (en) * | 2021-03-15 | 2021-08-03 | 新华三技术有限公司 | Signal sampling method and device |
| CN113904748A (en) * | 2021-09-24 | 2022-01-07 | 济南浪潮数据技术有限公司 | Clock synchronization method, system, device and medium |
| CN114422063A (en) * | 2021-12-13 | 2022-04-29 | 深圳市紫光同创电子有限公司 | Timestamp pulse synchronization method |
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| CN111245542A (en) * | 2018-11-28 | 2020-06-05 | 中兴通讯股份有限公司 | Method for acquiring time stamp and time synchronization system |
| CN110290580A (en) * | 2019-06-05 | 2019-09-27 | 深圳市英特瑞半导体科技有限公司 | A kind of method and its system based on 1588 agreement passing times |
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| CN112953669A (en) * | 2019-12-11 | 2021-06-11 | 烽火通信科技股份有限公司 | Method and system for improving timestamp precision |
| CN112953669B (en) * | 2019-12-11 | 2022-04-29 | 烽火通信科技股份有限公司 | Method and system for improving timestamp precision |
| CN111800212A (en) * | 2020-06-12 | 2020-10-20 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and device |
| CN111800212B (en) * | 2020-06-12 | 2022-04-15 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and device |
| CN112235067B (en) * | 2020-09-24 | 2022-03-25 | 烽火通信科技股份有限公司 | Centralized 1588 time synchronization method and time synchronization system |
| CN112235067A (en) * | 2020-09-24 | 2021-01-15 | 烽火通信科技股份有限公司 | Centralized 1588 time synchronization method and time synchronization system |
| CN113206665A (en) * | 2021-03-15 | 2021-08-03 | 新华三技术有限公司 | Signal sampling method and device |
| CN113904748A (en) * | 2021-09-24 | 2022-01-07 | 济南浪潮数据技术有限公司 | Clock synchronization method, system, device and medium |
| CN114422063A (en) * | 2021-12-13 | 2022-04-29 | 深圳市紫光同创电子有限公司 | Timestamp pulse synchronization method |
| WO2023109147A1 (en) * | 2021-12-13 | 2023-06-22 | 深圳市紫光同创电子有限公司 | Timestamp pulse synchronization method and apparatus, and electronic device and storage medium |
| CN114422063B (en) * | 2021-12-13 | 2023-08-29 | 深圳市紫光同创电子有限公司 | Time stamp pulse synchronization method |
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| WO2017219881A1 (en) | 2017-12-28 |
| CN107528654B (en) | 2020-06-05 |
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