CN111800212A - Timestamp jitter compensation method and device - Google Patents
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Abstract
The embodiment of the invention provides a timestamp jitter compensation method and a timestamp jitter compensation device, wherein the method comprises the following steps: performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain; based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain; and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation. According to the time stamp jitter compensation method and device provided by the embodiment of the invention, the jitter of the time stamp is effectively compensated by amplifying the error caused by the synchronization of the time stamp sampling identification signal of the system clock domain and then carrying out discrimination compensation.
Description
Technical Field
The present invention relates to the field of time synchronization technologies, and in particular, to a timestamp jitter compensation method and apparatus.
Background
With the advent of the 5G communication era, 5G communication has presented new requirements and challenges for time synchronization technology, and improving the accuracy of timestamps is a key to meeting the new requirements.
When the time stamp is processed, the problem of conversion from the time stamp sampling identification signal of a system clock domain or a local clock domain to the time stamp sampling identification signal of a 1588 clock domain exists, for a 1588 clock of 125MHz, the clock domain conversion error of the time stamp sampling identification signal is +/-8 ns, and the error can cause the jitter of the time stamp, so that the time synchronization performance is influenced.
In the prior art, a timestamp jitter compensation method includes increasing the frequency of a sampling clock, performing multiphase sampling and the like, but by increasing the frequency of the sampling clock and performing multiphase sampling, the time sequence requirement on an FPGA device is high, the selection requirement on components is high, and the cost is high.
Therefore, a new timestamp jitter compensation method is needed to solve the above problem.
Disclosure of Invention
In order to solve the problem that a clock domain conversion error of ± 8ns exists between a timestamp sampling identification signal of a system clock domain or a local clock domain and a timestamp sampling identification signal of a 1588 clock domain, which causes timestamp jitter, embodiments of the present invention provide a timestamp jitter compensation method and apparatus that overcome the above problem or at least partially solve the above problem.
In a first aspect, an embodiment of the present invention provides a timestamp jitter compensation method, including:
performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain;
and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
The clock synchronization is performed on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock, so as to obtain the timestamp sampling identification signal of the 1588 clock domain, and the clock synchronization method includes:
and if the 1588 clock is in a metastable state area during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the second clock period, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the second clock period as the timestamp sampling identification signal of the first 1588 clock domain.
The clock synchronization is performed on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock, so as to obtain the timestamp sampling identification signal of the 1588 clock domain, and the method further includes:
and if the 1588 clock is not in the metastable state region during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the first clock period, and marking the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the first clock period as a timestamp sampling identification signal of the second 1588 clock domain.
Wherein, according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation, comprises:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period.
Wherein, according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation, further comprising:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the phase of adding 1 clock cycle to the theoretical value x, keeping the timestamp unchanged.
Second aspect an embodiment of the present invention further provides a timestamp jitter compensation apparatus, including:
the 1588 clock synchronization module is used for performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
the system clock synchronization module is used for performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain based on a system clock to obtain a timestamp sampling identification signal of a second system clock domain;
and the timestamp compensation module is used for performing timestamp delay compensation according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain.
Wherein, the 1588 clock synchronization module comprises:
a metastable state area synchronizing unit, configured to, if the 1588 clock is in a metastable state area during clock synchronization, obtain a timestamp sampling identification signal of the 1588 clock domain in the second clock cycle in synchronization, and record the timestamp sampling identification signal of the 1588 clock domain obtained in the second clock cycle in synchronization as the timestamp sampling identification signal of the first 1588 clock domain
Wherein, the 1588 clock synchronization module further comprises:
and the non-metastable state area synchronization unit is used for synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the first clock cycle if the 1588 clock is not in the metastable state area during clock synchronization, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the first clock cycle as the timestamp sampling identification signal of the second 1588 clock domain.
Wherein the timestamp compensation module is specifically configured to:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period.
Wherein the timestamp compensation module is further to:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the phase of adding 1 clock cycle to the theoretical value x, keeping the timestamp unchanged.
Third aspect an embodiment of the present invention provides an electronic device, including:
a processor, a memory, a communication interface, and a bus; the processor, the memory and the communication interface complete mutual communication through the bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform one of the timestamp jitter compensation methods described above.
A fourth aspect of the present invention provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute a timestamp jitter compensation method as described above.
According to the timestamp jitter compensation method and device provided by the embodiment of the invention, the jitter of the timestamp is effectively compensated by amplifying the error caused by the synchronization of the timestamp sampling identification signal of the system clock domain and then carrying out identification compensation; compared with the mode of improving the frequency of the sampling clock and multi-phase sampling, the method has the advantages of low requirement on the time sequence of the FPGA, low requirement on the FPGA and capability of reducing the cost, and meanwhile, the mode has no limitation on the frequency, is wider in application range and has stronger compatibility.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for compensating for jitter of a timestamp according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating meta-stable region clock synchronization provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of non-metastable region clock synchronization provided by the embodiment of the invention;
fig. 4 is a schematic structural diagram of a time stamp jitter compensating apparatus according to an embodiment of the present invention;
fig. 5 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic flowchart of a timestamp jitter compensation method according to an embodiment of the present invention, as shown in fig. 1, including:
101. performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
102. based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain;
103. and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
It should be noted that the timestamp is one of the key factors of time synchronization, a timestamp mode and a timestamp requirement are specified in the 1588V2 protocol, 1588 is a precision clock synchronization protocol standard of a network measurement and control system defined by IEEE, in the whole 1588V2 network, all clocks are organized together according to a master-slave hierarchical relationship, and the reference time of the system is a highest-level clock. For the event message, time stamping is needed during receiving and sending, so that the line delay is convenient to calculate. The jitter of the time stamp can cause the jitter of the line delay, thereby affecting the performance index of the time synchronization. In view of the above scenario, embodiments of the present invention provide a way to compensate for time stamp jitter, so as to meet the time synchronization performance index.
Specifically, in step 101, the embodiment of the present invention first synchronizes the timestamp sampling identification signal of the first system clock domain from the system time domain to the 1588 clock domain. It should be understood that, the first system clock domain refers to a local clock domain of a sending or receiving device, and for convenience of description, in all embodiments of the present invention, a timestamp process of sending an event packet is taken as an example for description, and a sending process may be referred to for a process of receiving a timestamp, which is not specifically limited in this embodiment of the present invention. Then, a timestamp sampling identification signal of the first system clock domain, that is, a timestamp sampling identification signal generated by the local device at a frame header, for example, a leading byte when the local device sends the event packet, is named SOF _ sys in the embodiment of the present invention, and a real-time according to the timestamp sampling identification signal is used as a sending timestamp, but the timestamp sampling identification signal belongs to the system clock domain, and the signal needs to be transferred to the 1588 clock domain to obtain the timestamp sampling identification signal of the 1588 clock domain, which is denoted SOF _1588 in the embodiment of the present invention.
Further, in step 102, it is understood that a conversion error is introduced by the system time domain during the conversion process to the 1588 time domain, and the clock domain conversion, for example, a common 125MHz clock frequency, introduces an error of ± 8ns (1/125MHz), thereby causing a jitter of ± 8ns in the timestamp. To reduce this jitter, embodiments of the present invention employ amplifying the error and then compensating for the magnitude of the error. Specifically, in the embodiment of the present invention, the system clock is used to perform resynchronization on the SOF _1588 signal after 1588 clock synchronization, which is equivalent to lengthening the phase, thereby amplifying the error of clock domain conversion to obtain a timestamp sampling identification signal of the second system clock domain, which is denoted as SOF _1588_ SYS in the embodiment of the present invention.
Finally, in step 103, the timestamp sampling identification signal SOF _ SYS of the first system clock domain and the timestamp sampling identification signal SOF _1588_ SYS of the second system clock domain are compared to determine a phase difference existing after amplification, and then a certain delay compensation is performed on the timestamp according to the frequency of the clock cycle, so that the jitter of the timestamp is reduced, and a general compensation value is half of one clock cycle.
According to the timestamp jitter compensation method provided by the embodiment of the invention, the jitter of the timestamp is effectively compensated by amplifying the error caused by the synchronization of the timestamp sampling identification signal of the system clock domain and then carrying out identification compensation; compared with the mode of improving the frequency of the sampling clock and multi-phase sampling, the method has the advantages of low requirement on the time sequence of the FPGA, low requirement on the FPGA and capability of reducing the cost, and meanwhile, the mode has no limitation on the frequency, is wider in application range and has stronger compatibility.
On the basis of the foregoing embodiment, the performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain the timestamp sampling identification signal of the 1588 clock domain includes:
and if the 1588 clock is in a metastable state area during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the second clock period, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the second clock period as the timestamp sampling identification signal of the first 1588 clock domain.
As can be seen from the contents of the foregoing embodiments, in the embodiments of the present invention, firstly, a signal in a system clock domain is synchronized to a 1588 clock domain to obtain a timestamp sampling identification signal SOF _1588 in the 1588 clock domain for timestamp, so that in a process of time synchronization from the system clock domain to the 1588 clock domain, two possible scenarios may occur when a 1588 clock is in a metastable state region, one scenario is that a timestamp sampling identification signal of the 1588 clock domain cannot be directly synchronized in a current period when the 1588 clock is in the metastable state region, fig. 2 is a metastable state region clock synchronization schematic diagram provided by the embodiments of the present invention, as shown in fig. 2, clk _1588_ a cannot be synchronized in a metastable state region in a first clock period to obtain SOF _1588_ a, a timestamp sampling identification signal of the 1588 clock domain needs to be synchronized in a second clock period for differentiation, the embodiment of the invention refers to SOF _1588_ a as a timestamp sampling identification signal of a first 1588 clock domain.
On the basis of the foregoing embodiment, the clock synchronization is performed on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock, so as to obtain the timestamp sampling identification signal of the 1588 clock domain, and the method further includes:
and if the 1588 clock is not in the metastable state region during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the first clock period, and marking the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the first clock period as a timestamp sampling identification signal of the second 1588 clock domain.
As can be seen from the above description, in the embodiment of the present invention, the signal in the system clock domain is synchronized to the 1588 clock domain, so as to obtain the timestamp sampling identification signal SOF _1588 in the 1588 clock domain, for time stamping, then during time synchronization from the system clock domain to the 1588 clock domain, the state held by the 1588 clock, two possible scenarios may occur, the other being the case where the 1588 clock is in the non-metastable region, FIG. 3 is a schematic diagram of the non-metastable region clock synchronization provided by the embodiment of the present invention, as shown in FIG. 3, clk _1588_ b is not in the metastable region, SOF _1588_ b can be obtained directly in a first clock cycle, a timestamp sampling identification signal of a 1588 clock domain can be obtained in a second clock cycle, for differentiation, the embodiment of the present invention refers to SOF _1588_ b as a timestamp sampling identification signal of the second 1588 clock domain. On the basis of the foregoing embodiment, the performing timestamp delay compensation according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain includes:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period. The theoretical value X is a phase less than one clock cycle.
As can be seen from the contents of the above embodiments, in the embodiments of the present invention, the timestamp sampling identification signal SOF _1588_ a of the first 1588 clock domain and the timestamp sampling identification signal SOF _1588_ b of the second 1588 clock domain are obtained by respectively processing according to two situations whether clk _1588 is in the metastable state region, as shown in the content of fig. 3, after system clock synchronization is performed on SOF _1588_ b again, SOF _1588_ SYS _ b is obtained, that is, the timestamp sampling identification signal SOF the second system clock domain under the non-metastable state region, and is compared with the original timestamp sampling identification signal SOF _ SYS of the first system clock domain, there is a phase difference with a fixed value x, and x can be theoretically calculated according to different signal differences, for the phase error generated in such a situation, the embodiments of the present invention perform delay compensation on the phase error, so as to reduce the timestamp situation, the compensated delay is generally determined according to the signal clock period, for example, a 125MHz (8nm) clock frequency signal, then the compensation value can be set to +4nm, i.e., 4nm delay compensation is performed, so that the time stamp jitter is reduced to about ± 5ns, and the performance requirement of 5G ultra-high precision time synchronization can be met.
On the basis of the foregoing embodiment, the performing timestamp delay compensation according to an interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain further includes:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the phase of adding 1 clock cycle to the theoretical value x, keeping the timestamp unchanged.
As can be seen from the contents of the above embodiments, in the embodiments of the present invention, a timestamp sampling identification signal SOF _1588_ a of a first 1588 clock domain and a timestamp sampling identification signal SOF _1588_ b of a second 1588 clock domain are obtained by respectively processing according to two situations whether clk _1588 is in a metastable state region, as shown in the content of fig. 2, after system clock synchronization is performed on SOF _1588_ a again, SOF _1588_ SYS _ a, that is, a timestamp sampling identification signal of a second system clock domain in the metastable state region, is obtained, and is compared with an original timestamp sampling identification signal SOF _ SYS of a first system clock domain, a phase interval obtained is a theoretical value x +1, where +1 indicates one more cycle, but it should be noted that, timestamp jitter of a signal in the metastable state region is already within an allowable range, and may have adverse effects if delay compensation is performed again, therefore, for such a situation, the embodiment of the invention can ensure that the jitter of the timestamp can meet the performance requirement of 5G ultrahigh-precision time synchronization by only keeping the timestamp unchanged.
It can be seen from the above embodiments that, in the embodiments of the present invention, after amplifying the phase of the signal synchronization error, the phase compensation is performed on one of the situations caused by the error, so as to reduce the jitter of the timestamp.
Fig. 4 is a schematic structural diagram of a time stamp jitter compensating apparatus according to an embodiment of the present invention, as shown in fig. 4, including: 1588 clock synchronization module 401, system clock synchronization module 402, and timestamp compensation module 403, wherein:
the 1588 clock synchronization module 401 is configured to perform clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
the system clock synchronization module 402 is configured to perform clock synchronization on the timestamp sampling identification signal of the 1588 clock domain based on a system clock to obtain a timestamp sampling identification signal of a second system clock domain;
the timestamp compensation module 403 is configured to perform timestamp delay compensation according to an interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain.
Specifically, how to implement the technical solution of the embodiment of the timestamp jitter compensation method shown in fig. 1 through the 1588 clock synchronization module 401, the system clock synchronization module 402, and the timestamp compensation module 403 may be implemented, which has similar implementation principles and technical effects, and is not described herein again.
According to the time stamp jitter compensation device provided by the embodiment of the invention, the jitter of the time stamp is effectively compensated by amplifying the error caused by the synchronization of the time stamp sampling identification signal of the system clock domain and then carrying out discrimination compensation.
On the basis of the above embodiments, the 1588 clock synchronization module includes:
and the metastable state area synchronizing unit is used for synchronously obtaining the timestamp sampling identification signal of the first 1588 clock domain in the second clock period if the 1588 clock is in the metastable state area during clock synchronization.
On the basis of the above embodiment, the 1588 clock synchronization module further includes:
and the non-metastable state area synchronization unit is used for synchronously obtaining a timestamp sampling identification signal of a second 1588 clock domain in a first clock period if the 1588 clock is not in the metastable state area during clock synchronization.
On the basis of the foregoing embodiment, the timestamp compensation module is specifically configured to:
and if the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period.
On the basis of the foregoing embodiment, the timestamp compensation module is further configured to:
and if the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the theoretical value x plus 1, keeping the timestamp unchanged.
Fig. 5 is a block diagram of an electronic device according to an embodiment of the present invention, and referring to fig. 5, the electronic device includes: a processor (processor)501, a communication Interface (Communications Interface)502, a memory (memory)503, and a bus 504, wherein the processor 501, the communication Interface 502, and the memory 503 are configured to communicate with each other via the bus 504. The processor 501 may call logic instructions in the memory 503 to perform the following method: performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain; based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain; and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
An embodiment of the present invention discloses a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer can execute the methods provided by the above method embodiments, for example, the method includes: performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain; based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain; and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
Embodiments of the present invention provide a non-transitory computer-readable storage medium, which stores computer instructions, where the computer instructions cause the computer to perform the methods provided by the above method embodiments, for example, the methods include: performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain; based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain; and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to each embodiment or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of time stamp jitter compensation, comprising:
performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
based on a system clock, performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain to obtain a timestamp sampling identification signal of a second system clock domain;
and according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain, performing timestamp delay compensation.
2. The timestamp jitter compensation method of claim 1, wherein the clock synchronizing the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain the timestamp sampling identification signal of the 1588 clock domain comprises:
and if the 1588 clock is in a metastable state area during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the second clock period, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the second clock period as the timestamp sampling identification signal of the first 1588 clock domain.
3. The timestamp jitter compensation method of claim 2, wherein the clock synchronization is performed on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain the timestamp sampling identification signal of the 1588 clock domain, further comprising:
and if the 1588 clock is not in the metastable state region during clock synchronization, synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the first clock period, and marking the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the first clock period as a timestamp sampling identification signal of the second 1588 clock domain.
4. The timestamp jitter compensation method of claim 3, wherein the timestamp delay compensation according to the interval period between the timestamp sample identification signal of the first system clock domain and the timestamp sample identification signal of the second system clock domain comprises:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period.
5. The timestamp jitter compensation method of claim 4, wherein the timestamp delay compensation is performed according to an interval period between the timestamp sample identification signal of the first system clock domain and the timestamp sample identification signal of the second system clock domain, further comprising:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the phase of adding 1 clock cycle to the theoretical value x, keeping the timestamp unchanged.
6. A time stamp jitter compensating apparatus, comprising:
the 1588 clock synchronization module is used for performing clock synchronization on the timestamp sampling identification signal of the first system clock domain based on the 1588 clock to obtain a timestamp sampling identification signal of the 1588 clock domain;
the system clock synchronization module is used for performing clock synchronization on the timestamp sampling identification signal of the 1588 clock domain based on a system clock to obtain a timestamp sampling identification signal of a second system clock domain;
and the timestamp compensation module is used for performing timestamp delay compensation according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain.
7. The timestamp jitter compensation apparatus of claim 6, wherein the 1588 clock synchronization module comprises:
and the metastable state area synchronizing unit is used for synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the second clock period if the 1588 clock is in the metastable state area during clock synchronization, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the second clock period as the timestamp sampling identification signal of the first 1588 clock domain.
8. The timestamp jitter compensation apparatus of claim 7, wherein the 1588 clock synchronization module further comprises:
and the non-metastable state area synchronization unit is used for synchronously obtaining a timestamp sampling identification signal of the 1588 clock domain in the first clock cycle if the 1588 clock is not in the metastable state area during clock synchronization, and recording the timestamp sampling identification signal of the 1588 clock domain obtained synchronously in the first clock cycle as the timestamp sampling identification signal of the second 1588 clock domain.
9. The timestamp jitter compensation apparatus of claim 8, wherein the timestamp compensation module is specifically configured to:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is a theoretical value x, performing delay processing on the timestamp according to the clock period.
10. The timestamp jitter compensation apparatus of claim 9, wherein the timestamp compensation module is further configured to:
and if the phase interval between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain is the phase of adding 1 clock cycle to the theoretical value x, keeping the timestamp unchanged.
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