CN116671193B - Sampling method, sampling circuit and clock synchronization method of distributed network - Google Patents
Sampling method, sampling circuit and clock synchronization method of distributed network Download PDFInfo
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Abstract
The application provides a sampling method, a sampling circuit and a clock synchronization method of a distributed network, wherein the sampling method comprises the following steps: receiving time stamp information and second pulse information; sampling second pulse information by adopting a first clock signal and a second clock signal to respectively obtain a first sampling signal and a second sampling signal; the period of the first clock signal is the same as that of the second clock signal, and the phase difference is 180 degrees; determining a first sampling value of the first sampling signal at a sampling point and a second sampling value of the second sampling signal at the sampling point; comparing the difference between the first sampling value and the second sampling value, if the first sampling value is the same as the second sampling value, adjusting the time stamp information, and then performing clock synchronization based on the adjusted time stamp information; if the first sample value is different from the second sample value, clock synchronization is performed based on the time stamp information. The application adopts a double-phase sampling method, which can improve the sampling precision and further improve the precision of clock synchronization.
Description
Technical Field
The present application relates to the field of distributed network technologies, and in particular, to a sampling method, a sampling circuit, and a clock synchronization method for a distributed network.
Background
The precision clock synchronization protocol standard (standard for a precision clock synchronization protocol for networked measurement and control systems,IEEE 1588) of the network measurement and control system can accurately synchronize real-time clocks of all nodes in distributed network communication, in the IEEE 1588 synchronization system, each node of the distributed network is provided with a clock module and a processing module, wherein the processing module is used for carrying out related protocol processing of IEEE 1588 messages and collecting related time stamps, and sending the time stamps to the clock module, and the clock module is used for carrying out operation of clock information based on the time stamps so as to adjust a local real-time clock to realize clock synchronization. The clock module periodically transmits time stamp information and Pulse Per Second (PPS) information to the processing module, thereby synchronizing the real-time clock of the processing module with the clock module.
The IEEE 1588 synchronization system has very high precision requirement, and the precision is required to be nanosecond at present, wherein the sampling precision of PPS information is an important influencing factor of the precision of the whole IEEE 1588 synchronization system. In the related art, the sampling accuracy of PPS information is completely dependent on the clock frequency of the sampling clock, that is, the sampling accuracy of PPS information can be improved only by increasing the clock frequency of the sampling clock, for example, a sampling clock having a clock frequency of 1GHz is required to achieve the sampling accuracy of PPS information of 1ns. However, due to the problem of timing convergence, the clock frequency of the sampling clock cannot be infinitely increased, and the sampling accuracy of PPS information is difficult to increase.
Disclosure of Invention
The application provides a sampling method, a sampling circuit and a clock synchronization method of a distributed network, which are used for improving sampling precision.
In a first aspect, the present application provides a sampling method, comprising: receiving time stamp information and second pulse information; sampling second pulse information by adopting a first clock signal and a second clock signal to respectively obtain a first sampling signal and a second sampling signal; the periods of the first clock signal and the second clock signal are the same, and the phase difference between the first clock signal and the second clock signal is 180 degrees; taking a first jump edge of the first sampling signal as a sampling point, determining a first sampling value of the first sampling signal at the sampling point, and determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal; the first jump edge is a jump edge from a first value to a second value; comparing the difference between the first sampling value and the second sampling value, if the first sampling value is the same as the second sampling value, adjusting the time stamp information, and then performing clock synchronization based on the adjusted time stamp information; if the first sample value and the second sample value are different, clock synchronization is performed based on the time stamp information.
The sampling method provided by the embodiment of the application adopts the first clock signal and the second clock signal to sample the second pulse information, and a first sampling signal and a second sampling signal are respectively obtained; the periods of the first clock signal and the second clock signal are the same, the phase difference between the first clock signal and the second clock signal is 180 degrees, the jump edge position of the second pulse information can be determined according to the obtained first sampling signal and the second sampling signal, namely, the jump edge of the second pulse information and the sampling point are different by 0-0.5 period of the first clock signal or by 0.5-1 period of the first clock signal, namely, the sampling method in the embodiment of the application can determine which period of the first clock signal the jump edge of the second pulse information is located, and can further determine whether the jump edge of the second pulse information P is located in the first half period or the second half period of the period, so that the sampling precision can be reduced to 0.5 clock period, and the sampling precision is improved to be doubled.
In one possible implementation manner, the sampling the second pulse information by using the first clock signal and the second clock signal to obtain a first sampling signal and a second sampling signal respectively, including; determining a sampling value of second pulse information at each first jump edge of a first clock signal to obtain a first sampling signal; and determining a sampling value of second pulse information at each first jump edge of the second clock signal to obtain a second sampling signal.
In an actual application process, the phases of the first clock signal and the second clock signal may drift, so as to monitor the phases of the first clock signal and the second clock signal and adjust the phases of the first clock signal and the second clock signal in real time, the sampling method provided by the embodiment of the application may further include: sampling the detection signal for N times by adopting the first clock signal and the second clock signal to obtain N groups of sampling results; each set of sampling results includes a first sampling signal and a second sampling signal; wherein the detection signals are random signals uniformly distributed in the time domain; for each set of sampling results, performing: taking a first jump edge of the first sampling signal as a sampling point, determining a first sampling value of the first sampling signal at the sampling point, and determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal; the N groups of sampling results comprise: n1 sets of first sampling results and n2 sets of second sampling results; wherein, the first sampling value and the second sampling value in the first sampling result are the same; the first sampling value and the second sampling value in the second sampling result are different; and determining the phase shift amounts of the first clock signal and the second clock signal according to the total number N of the sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results, and adjusting the phases of the first clock signal and the second clock signal according to the phase shift amounts.
Because the detection signal is a random signal with uniformly distributed time domains, after the detection signal is sampled for N times, if the phases of the first clock signal and the second clock signal do not drift, the number N1 of the first sampling results is basically consistent with the number N2 of the second sampling results in the N groups of sampling results, and if the phases of the first clock signal and the second clock signal drift, the phase drift amount of the first clock signal and the second clock signal can be reflected through the total number N of the sampling results, the number N1 of the first sampling results and the second sampling result N2. Then, the phases of the first clock signal and the second clock signal are adjusted according to the phase shift amount so that the phase difference between the first sampling signal and the second sampling signal is maintained at 180 °.
In one possible implementation, the phase shift amount S of the first clock signal and the second clock signal may be determined according to the following formula:
S＝(n1-n2)*360°/(2*N)。
In one possible implementation, the clock frequency of the first clock signal may be 1GHz; the detection signal may be a signal obtained by frequency division of a clock signal with a clock frequency of 999M Hz, i.e. the detection signal may be a pseudo-random signal. The signal after frequency division is used as the detection signal, so that the period of the detection signal is larger, and the high phase and the low phase of the detection signal can be ensured to be sampled.
In a second aspect, the present application further provides a clock synchronization method of a distributed network, where each node of the distributed network includes a clock module and a processing module. The clock synchronization method may include: the clock module sends the time stamp information and the second pulse information to the processing module; the processing module executes any sampling method to sample the second pulse information; if the first sampling value obtained by the sampling of the processing module is the same as the second sampling value, the processing module adds 1 clock cycle to the data of the time stamp information and then updates the data into the internal real-time clock; if the first sampling value and the second sampling value obtained by the sampling of the processing module are different, the processing module directly updates the data of the time stamp information into the internal real-time clock.
In the embodiment of the application, the processing module adopts the sampling method to sample the second pulse information, and the sampling accuracy of the sampling method is higher, so that the second pulse information acquired by the processing module is more accurate, and the time synchronization of the processing module is more accurate.
In a third aspect, the present application also provides a sampling circuit, which may include: the device comprises a first sampling module, a second sampling module, a first sampling value extraction module and a second sampling value extraction module; the first sampling module is used for receiving the first clock signal and the second pulse information, sampling the second pulse information by adopting the first clock signal and outputting a first sampling signal; the second sampling module is used for receiving a second clock signal and second pulse information, sampling the second pulse information by adopting the second clock signal and outputting a second sampling signal; the first sampling value extraction module is electrically connected with the first sampling module and is used for determining a first sampling value of a first sampling signal at a sampling point and outputting the first sampling value; the sampling point is a first jump edge of a first sampling signal, and the first jump edge is a jump edge from a first value to a second value; and the second sampling value extraction module is electrically connected with the second sampling module and is used for determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal and outputting the second sampling value.
The sampling circuit provided by the embodiment of the application adopts the first sampling module and the second sampling module to sample the second pulse information respectively, so that a first sampling signal and a second sampling signal can be obtained, a first sampling value of the first sampling signal at a sampling point can be obtained through the first sampling value extraction module, a second sampling value of the first sampling signal at the sampling point can be obtained through the second sampling value extraction module, and then, according to the first sampling value and the second sampling value, the cycle of a first clock signal with the difference of 0-0.5 times or the cycle of a first clock signal with the difference of 0.5-1 times can be determined on the jump edge of the second pulse information.
In one possible implementation manner, in order to monitor phases of the first clock signal and the second clock signal, the sampling circuit provided by the embodiment of the present application may further include: the detection signal generation module and the counting module; the detection signal generation module is electrically connected with the first sampling module and the second sampling module and is used for generating detection signals; the counting module is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the total number N of sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results.
According to the sampling circuit provided by the embodiment of the application, the total number N of the sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results are counted by the counting module, so that the phase shift amounts of the first clock signal and the second clock signal can be determined, and further, the phases of the first clock signal and the second clock signal can be adjusted according to the phase shift amounts, so that the phase difference between the first sampling signal and the second sampling signal is kept at 180 degrees.
In one possible implementation manner, the counting module may include: a first counter, a second counter, and a third counter; the first counter is electrically connected with the first sampling value extraction module and is used for counting the total number N of sampling results; the second counter is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the number of the first sampling results; the third counter is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the number of second sampling results.
In a possible implementation manner, the sampling circuit provided by the embodiment of the present application may further include: and an enable switch electrically connected with the counting module. The enabling switch is used for receiving an enabling control signal, when the enabling control signal is valid, the control counting module starts counting, and when the enabling control signal is invalid, the control counting module stops counting. In specific implementation, the method of calculating the average value by counting a plurality of times can be adopted to reduce the influence of errors on the adjustment result.
Drawings
FIG. 1 is a flow chart of a sampling method according to an embodiment of the present application;
FIG. 2 is a timing chart corresponding to a sampling method according to the embodiment of the present application;
FIG. 3 is another timing diagram of a sampling method according to an embodiment of the present application;
FIG. 4 is a timing chart showing the phase shifting of the first clock signal and the second clock signal;
FIG. 5 is a timing diagram of a first clock signal and a detection signal;
FIG. 6 is a schematic diagram of a node in a distributed network according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a sampling circuit according to an embodiment of the present application;
fig. 8 is a schematic diagram of another structure of a sampling circuit according to an embodiment of the present application.
Reference numerals:
P-second pulse information; clk 1-a first clock signal; clk 2-a second clock signal; q1-a first sampling signal; q2-the second sampled signal; a-sampling points; 201-a clock module; 202-a processing module; u1-a first interface; u2-a second interface; u3-third interface; 31-a first sampling module; 311-a first register; 32-a second sampling module; 321-a second register; 33-a first sampling value extraction module; 331-a third register; 332-a first not gate device; 333-a first and gate device; 34-a second sampling value extraction module; 341-fourth register; a 35-detection signal generation module; 351-a fifth register; 352-a second not gate device; 36-a counting module; 361-a first counter; 362-a second counter; 363-third counter; 364-a second and gate device; 365-third and gate device; 366-a third NOT device; 37-enable switch.
Detailed Description
The sampling method provided by the embodiment of the application can be applied to an IEEE 1588 synchronous system to improve the sampling precision of PPS information in the IEEE 1588 synchronous system, thereby improving the precision of the IEEE 1588 synchronous system. Of course, the sampling method provided by the embodiment of the present application may also be applied to other scenes, and the sampling method in the present application may also sample other signals, which is not limited herein to the application scene of the sampling method provided by the embodiment of the present application.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the embodiment of the present application, "and/or" describing the association relationship of the association object indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. At least one in reference to the present application means one or more; plural means two or more. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.
Fig. 1 is a flowchart of a sampling method provided by an embodiment of the present application, fig. 2 is a timing chart corresponding to the sampling method provided by the embodiment of the present application, and in combination with fig. 1 and fig. 2, the sampling method in the embodiment of the present application may include:
s101, receiving time stamp information and second pulse information;
S102, sampling second pulse information P by adopting a first clock signal clk1 and a second clock signal clk2 to respectively obtain a first sampling signal Q1 and a second sampling signal Q2; the periods of the first clock signal clk1 and the second clock signal clk2 are the same, and the phase difference between the first clock signal clk1 and the second clock signal clk2 is 180 °. It should be noted that the phase difference between the first clock signal clk1 and the second clock signal clk2 is 180 ° in the embodiment of the present application, which means that the phase difference between the first clock signal clk1 and the second clock signal clk2 is 180 ° within a certain deviation range, or it can be understood that the phase difference between the first clock signal clk1 and the second clock signal clk2 is approximately 180 °. Moreover, the first clock signal clk1 and the second clock signal clk2 need to be kept synchronous, so as to ensure higher sampling accuracy. Alternatively, in order to make the sampling accuracy higher, the clock frequency of the first clock signal clk1 may be 1 ghz or 500 mhz, and of course, the clock frequency of the first clock signal clk1 may also be other values, which are not limited herein.
S103, taking the first jump edge of the first sampling signal Q1 as a sampling point A, determining a first sampling value of the first sampling signal Q1 at the sampling point A, and determining a second sampling value of the second sampling signal Q2 at the sampling point A of the first sampling signal Q1. It should be noted that, in the embodiment of the present application, the sampling points a refer to the first transition edges of the first sampling signal Q1, where the first transition edges are transition edges from the first value to the second value, for example, the first transition edges may be rising edges, that is, transition edges from the low level (0) to the high level (1), and of course, the first transition edges may also be falling edges, that is, transition edges from the high level (1) to the low level (0), and for convenience of explanation, the first transition edges are all described in the present application as rising edges.
S104, comparing the difference between the first sampling value and the second sampling value, if the first sampling value is the same as the second sampling value, and if the jump edge of the second pulse information P is different from the sampling point A by 0.5-1 periods of the first clock signal clk1, adjusting the time stamp information, and then performing clock synchronization based on the adjusted time stamp information; if the first sampling value and the second sampling value are different, the jump edge of the second pulse information P is different from the sampling point A by 0-0.5 periods of the first clock signal clk1, and clock synchronization is performed based on the time stamp information.
In the distributed network, each node may include a clock module and a processing module, and the above steps S101 to S104 may be performed in the processing module, that is, the clock module periodically transmits the time stamp information and the second pulse information to the processing module, and the processing module triggers the processing module to perform the above steps S101 to S104 when receiving the time stamp information and the second pulse information.
The sampling method provided by the embodiment of the application adopts the first clock signal and the second clock signal to sample the second pulse information, and a first sampling signal and a second sampling signal are respectively obtained; the periods of the first clock signal and the second clock signal are the same, the phase difference between the first clock signal and the second clock signal is 180 degrees, the jump edge position of the second pulse information can be determined according to the obtained first sampling signal and the second sampling signal, namely, the jump edge of the second pulse information and the sampling point are different by 0-0.5 period of the first clock signal or by 0.5-1 period of the first clock signal, namely, the sampling method in the embodiment of the application can determine which period of the first clock signal the jump edge of the second pulse information is located, and further determine whether the jump edge of the second pulse information P is located in the first half period or the second half period of the period. In the related art, a clock signal is used for sampling the second pulse information, and only the period in which the jump edge of the second pulse information is located can be determined, so that the sampling precision is one clock period.
If the first sampling value is the same as the second sampling value, adjusting the time stamp information, and then performing clock synchronization based on the adjusted time stamp information; if the first sample value and the second sample value are different, clock synchronization is performed based on the time stamp information. The embodiment of the application can more accurately determine the jump edge of the second pulse information, and further, can more accurately synchronize clocks.
With continued reference to fig. 1 and fig. 2, in the above sampling method provided by the embodiment of the present application, the step S102 may include:
the sample value of the second pulse information P at each first transition edge of the first clock signal clk1 is determined to obtain a first sample signal Q1, for example, in fig. 2, the sample value of the second pulse information P at each first transition edge of the first clock signal clk1 is respectively: 0.1, and obtaining the timing sequence of the first sampling signal Q1 according to the determined sampling values.
Determining the sampling value of the second pulse information P at each first transition edge of the second clock signal clk2, to obtain a second sampling signal Q2, for example, in fig. 2, the sampling value of the second pulse information P at each first transition edge of the second clock signal clk2 is respectively: 0.1, and obtaining the timing sequence of the second sampling signal Q2 according to the determined sampling values.
As shown in fig. 2, the transition edge of the second pulse information P is different from the sampling point a by 0 to 0.5 periods of the first clock signal, that is, the transition edge of the second pulse information P is located in the area T2 in the drawing, where the first sampling value of the first sampling signal Q1 at the sampling point a is 1, and the second sampling value of the second sampling signal Q2 at the sampling point a is 0, that is, the first sampling value is different from the second sampling value. Fig. 3 is another timing chart of the sampling method according to the embodiment of the present application, as shown in fig. 3, the transition edge of the second pulse information P is different from the sampling point a by 0.5-1 period of the first clock signal clk1, that is, the transition edge of the second pulse information P is located in the area T1 in the drawing, where the first sampling value of the first sampling signal Q1 at the sampling point a is 1, and the second sampling value of the second sampling signal Q2 at the sampling point a is 1, that is, the first sampling value is the same as the second sampling value. Therefore, in the above step S104, it is possible to determine whether the transition edge of the second pulse information P is different from the sampling point by 0 to 0.5 periods of the first clock signal clk1 or by 0.5 to 1 periods of the first clock signal clk1 by comparing the magnitudes of the first sampling value and the second sampling value. That is, the sampling method in the embodiment of the present application not only can determine in which period of the first clock signal clk1 the transition edge of the second pulse information P is located, but also can further determine whether the transition edge of the second pulse information P is located in the first half period or the second half period of the period, thereby improving the sampling accuracy.
Taking the timing diagrams shown in fig. 2 and 3 as an example, the first sampling value is 1 regardless of whether the transition edge of the second pulse information P is located in the area T1 or the area T2, in the step S104, the difference between the first sampling value and the second sampling value may be determined by determining a specific value of the second sampling value, for example, when the second sampling value is 1, the first sampling value may be determined to be the same as the second sampling value, and when the second sampling value is 0, the first sampling value may be determined to be different from the second sampling value. Of course, in the above step S104, the difference between the first sampling value and the second sampling value may be compared in other manners, which is not limited herein.
In the practical application process, the phase of the first clock signal and the phase of the second clock signal may drift, and fig. 4 is a timing chart after the phase of the first clock signal and the phase of the second clock signal drift, as shown in fig. 4, the phase of the first clock signal clk1 and the phase of the second clock signal clk2 drift, so that the difference between the sizes of the area T1 and the area T2 is larger, the area T1 becomes smaller, and the area T2 becomes larger, that is, the determined difference between the transition edge of the second pulse information and the sampling point is no longer 0 to 0.5 cycles of the first clock signal, or 0.5 to 1 cycles of the first clock signal, thereby affecting the sampling precision of the second pulse information.
In order to monitor the phases of the first clock signal and the second clock signal and adjust the phases of the first clock signal and the second clock signal in real time, the sampling method provided by the embodiment of the application may further include:
Sampling the detection signal for N times by adopting the first clock signal and the second clock signal to obtain N groups of sampling results; each set of sampling results includes a first sampling signal and a second sampling signal; wherein the detection signals are random signals uniformly distributed in the time domain;
for each set of sampling results, performing: taking a first jump edge of the first sampling signal as a sampling point, determining a first sampling value of the first sampling signal at the sampling point, and determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal;
the N groups of sampling results comprise: n1 sets of first sampling results and n2 sets of second sampling results; wherein, the first sampling value and the second sampling value in the first sampling result are the same; the first sampling value and the second sampling value in the second sampling result are different; and determining the phase shift amounts of the first clock signal and the second clock signal according to the total number N of the sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results, and adjusting the phases of the first clock signal and the second clock signal according to the phase shift amounts.
That is, the steps S102 to S104 are performed N times with the detection signal as the second pulse information, and after N times of sampling is performed on the detection signal because the detection signal is a random signal with uniformly distributed time domains, if the phases of the first clock signal and the second clock signal do not drift, the number N1 of the first sampling result and the number N2 of the second sampling result are substantially identical in N sets of sampling results, and if the phases of the first clock signal and the second clock signal drift, the phase drift amount of the first clock signal and the second clock signal can be reflected by the total number N of sampling results, the number N1 of the first sampling result and the second sampling result N2. Then, the phases of the first clock signal and the second clock signal are adjusted according to the phase shift amount, so that the phase difference between the first sampling signal and the second sampling signal is kept 180 degrees, for example, the phase of the first clock signal may be adjusted correspondingly according to the phase shift amount, or the second clock signal may be adjusted, or both may be adjusted simultaneously, which is not limited herein.
Optionally, in the above sampling method provided by the embodiment of the present application, the phase shift amount S of the first clock signal and the second clock signal may be determined according to the following formula:
S＝(n1-n2)*360°/(2*N)。
For example, after sampling the detection signal N times, the total number N of sampling results is 1000, where the number N1 of the first sampling results is 600, and the number N2 of the second sampling results is 400, and according to the above formula, it is known that the phase shift amounts s=36° of the first clock signal and the second clock signal.
The total number N of sampling results corresponds to one period of the first clock signal, and if the phases of the first clock signal and the second clock signal do not drift, the number of the first sampling results is the same as the number of the second sampling results, that is, n1=n2=n/2. If the phases of the first clock signal and the second clock signal drift, the number of the first sampling results is different from the number of the second sampling results, and the variation amount of the first sampling results (or the second sampling results) is (n 1-n 2)/2 compared with the case when the phases of the first clock signal and the second clock signal do not drift.
The total phase (360 °) of one period of the first clock signal is divided into N parts, and if the variation amount of the number N1 of the first sampling results (or the number N2 of the second sampling results) is 1, the corresponding phase shift amount is 360 °/N, so that the product of the variation amount (N1-N2)/2 of the number N1 of the first sampling results (or the number N2 of the second sampling results) and the phase shift amount corresponding to the variation amount of 1 is 360 °/N can be determined, that is, s= { (N1-N2)/2 }) of the phase shift amount S of the first clock signal and the second clock signal is 360 °/N.
In a specific implementation, in the sampling method provided by the embodiment of the present application, a clock frequency of the first clock signal may be 1GHz; the detection signal may be a signal obtained by frequency division of a clock signal with a clock frequency of 999M Hz, i.e. the detection signal may be a pseudo-random signal. The signal after frequency division is used as the detection signal, so that the period of the detection signal is larger, and the high phase and the low phase of the detection signal can be ensured to be sampled. Fig. 5 is a timing chart of the first clock signal and the detection signal, as shown in fig. 5, the period of the first clock signal is 1ns, the first clock signal clk1 is aligned with the edge of the detection signal P1 at the first rising edge of the first clock signal clk1, the first clock signal clk1 is different from the edge of the detection signal P1 by 1/999ns at the second rising edge of the first clock signal clk1, the first clock signal clk1 is different from the edge of the detection signal P1 by 2/999ns at the third rising edge of the first clock signal clk1, the first clock signal clk1 is different from the edge of the detection signal P1 by i+1th rising edge of the first clock signal clk1 by i/999ns, and the first clock signal clk1 is aligned with the edge of the detection signal P1 again at the first 1000 rising edge of the first clock signal clk 1. Therefore, the detection signal P1 is uniformly distributed in one period of the first clock signal clk1 with 1/999ns granularity, and thus, the detection signal P1 is sampled N times, so that the phase drift amounts of the first clock signal and the second clock signal can be reflected according to the total amount N of the sampling results, the number N1 of the first sampling results, and the second sampling result N2.
Based on the same technical concept, the embodiment of the application further provides a clock synchronization method of the distributed network, and fig. 6 is a schematic structural diagram of one node in the distributed network in the embodiment of the application, as shown in fig. 6, each node in the distributed network includes a clock module 201 and a processing module 202, and real-time clocks are set in the clock module 201 and the processing module 202. The clock module 201 is electrically connected with the processing module 202 through a first interface U1 and a second interface U2, wherein the first interface U1 is a single-wire interface, the second interface U2 is a two-wire bidirectional bus interface, the first interface U1 can be used for transmitting second pulse information, and the second interface U2 can be used for transmitting time stamp information. The different nodes can be connected by electric signals through a third interface U3, and the third interface U3 can be used for transmitting protocol messages of IEEE 1588.
In a distributed network, one node of a plurality of nodes serves as a master node (master), the rest of nodes serve as slave nodes (slave), and the master node can synchronize reference time to all the slave nodes. The processing module of the master node sends an IEEE 1588 protocol message to the processing module of the slave node, the slave node can collect a time stamp according to the received protocol message and send the time stamp to the clock module, the clock module of the slave node can determine the time deviation between the slave node and the master node according to the time stamp, the slave node can obtain the frequency deviation between the slave node and the master node after receiving the protocol message for many times, and the clock module of the slave node can adjust the real-time clock according to the time deviation and the frequency deviation of the slave node, so that the clock module of the slave node and the reference time of the master node are synchronized. And then, the processing module in the slave node sends the time stamp to the clock module, the clock module adjusts the real-time clock according to the time stamp and the reference time, and then, the clock module sends the time stamp information and the second pulse information to the processing module, and the processing module adjusts the real-time clock according to the time stamp information and the second pulse information, so that the processing module and the clock template realize clock synchronization.
The clock synchronization method provided by the embodiment of the application can comprise the following steps:
Referring to fig. 6, the clock module 201 transmits the time stamp information and the second pulse information to the processing module 202;
The processing module 202 performs the above-mentioned sampling method, that is, at least performs the above-mentioned step S101 to the above-mentioned step S104, and samples the second pulse information;
If the first sampling value obtained by the sampling of the processing module 202 is the same as the second sampling value, the processing module 202 adds 1 clock cycle to the data of the time stamp information and updates the data into the internal real-time clock; if the first sampling value and the second sampling value obtained by the processing module 202 are different, the processing module 202 directly updates the data of the time stamp information to the internal real-time clock.
In the embodiment of the application, the processing module 202 samples the second pulse information by adopting the sampling method, and the sampling accuracy of the sampling method is higher, so that the second pulse information acquired by the processing module 202 is more accurate, and further, the time synchronization of the processing module 202 is more accurate.
Based on the same technical concept, the embodiment of the present application further provides a sampling circuit, and fig. 7 is a schematic structural diagram of the sampling circuit provided by the embodiment of the present application, as shown in fig. 7, where the sampling circuit in the embodiment of the present application may include:
The first sampling module 31 is configured to receive the first clock signal clk1 and the second pulse information P, sample the second pulse information P with the first clock signal clk1, and output a first sampling signal Q1;
The second sampling module 32 is configured to receive the second clock signal clk2 and the second pulse information P, sample the second pulse information P with the second clock signal clk2, and output a second sampling signal Q2;
the first sampling value extraction module 33 is electrically connected to the first sampling module 31, and is configured to determine a first sampling value Q1 of the first sampling signal Q1 at the sampling point, and output the first sampling value Q1; the sampling point is a first jump edge of the first sampling signal Q1, and the first jump edge is a jump edge from a first value to a second value;
The second sampling value extraction module 34 is electrically connected to the second sampling module 32, and is configured to determine a second sampling value Q2 of the second sampling signal Q2 at the sampling point of the first sampling signal Q1, and output the second sampling value Q2.
The sampling circuit provided by the embodiment of the application adopts the first sampling module and the second sampling module to sample the second pulse information respectively, so that a first sampling signal and a second sampling signal can be obtained, a first sampling value of the first sampling signal at a sampling point can be obtained through the first sampling value extraction module, a second sampling value of the first sampling signal at the sampling point can be obtained through the second sampling value extraction module, and then, according to the first sampling value and the second sampling value, the cycle of a first clock signal with the jump edge of the second pulse information being different from the sampling point by 0-0.5 or the cycle of the first clock signal with the difference from 0.5-1 can be determined.
With continued reference to fig. 7, the first sampling module 31 may include a plurality of first registers 311. The second sampling module 32 may include a plurality of second registers 321. The first sample value extraction module 33 may include: a third register 331, a first not gate device 332, and a first and gate device 333. The second sample value extraction module 34 may include a fourth register 341.
Fig. 8 is another schematic structural diagram of a sampling circuit according to an embodiment of the present application, as shown in fig. 8, in order to monitor phases of a first clock signal and a second clock signal, the sampling circuit according to an embodiment of the present application may further include:
The detection signal generating module 35 is electrically connected to the first sampling module 31 and the second sampling module 32, and is configured to generate the detection signal P1, for example, the detection signal generating module 35 may divide the clock signal with a clock frequency of 999 mhz by two to obtain the detection signal P1. The detection signal generation module 35 may include: a fifth register 351 and a second not device 352.
The counting module 36 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34, and is configured to count the total number N of sampling results, the number N1 of the first sampling results, and the number N2 of the second sampling results.
According to the sampling circuit provided by the embodiment of the application, the total number N of the sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results are counted by the counting module, so that the phase shift amounts of the first clock signal and the second clock signal can be determined, and further, the phases of the first clock signal and the second clock signal can be adjusted according to the phase shift amounts, so that the phase difference between the first sampling signal and the second sampling signal is kept at 180 degrees.
Optionally, in the above sampling circuit provided by the embodiment of the present application, with continued reference to fig. 8, the counting module 36 includes: a first counter 361, a second counter 362, and a third counter 363;
the first counter 361 is electrically connected to the first sampling value extraction module 33, and is configured to count the total number N of sampling results, the first sampling value extraction module 33 is configured to determine a first sampling value Q1 of the first sampling signal Q1 at the sampling point, and the first counter 361 may determine the total number N of sampling results according to the number of first sampling values Q1 output by the first sampling value extraction module 33.
The second counter 362 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34, and is used for counting the number n1 of the first sampling results. The second counter 362 is electrically connected to the first sampling value extraction module 33 and the second sampling value extraction module 34 through the second and gate device 364, and counts once when detecting that the first sampling value q1 output by the first sampling value extraction module 33 is the same as the second sampling value q2 output by the second sampling value extraction module 34, to finally obtain the number n1 of first sampling results.
The third counter 363 is electrically connected to the first sampling value extraction module 33 and the second sampling value extraction module 34, and is configured to count the number n2 of the second sampling results. The third counter 363 is electrically connected to the first sampling value extraction module 33 and the second sampling value extraction module 34 through the third and gate device 365, and the second sampling value extraction module 34 is electrically connected to the third and gate device 365 through the third not gate device 366, and when detecting that the first sampling value q1 output by the first sampling value extraction module 33 is different from the second sampling value q2 output by the second sampling value extraction module 34, the number n2 of second sampling results is finally obtained.
In addition, with continued reference to fig. 8, the sampling circuit provided by the embodiment of the present application may further include: an enable switch 37 electrically connected to the counting module 36, the enable switch 37 is configured to receive the enable control signal En, control the counting module 36 to start counting when the enable control signal En is active, and control the counting module 36 to stop counting when the enable control signal En is inactive. In specific implementation, the method of calculating the average value by counting a plurality of times can be adopted to reduce the influence of errors on the adjustment result.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.
Claims (10)
1. A method of sampling comprising:
Receiving time stamp information and second pulse information;
Sampling the second pulse information by adopting a first clock signal and a second clock signal to respectively obtain a first sampling signal and a second sampling signal; wherein the periods of the first clock signal and the second clock signal are the same, and the phase difference between the first clock signal and the second clock signal is 180 degrees;
Taking a first jump edge of the first sampling signal as a sampling point, determining a first sampling value of the first sampling signal at the sampling point, and determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal; the first jump edge is a jump edge from a first value to a second value;
comparing the difference between the first sampling value and the second sampling value, if the first sampling value is the same as the second sampling value, adjusting the time stamp information, and then performing clock synchronization based on the adjusted time stamp information; and if the first sampling value and the second sampling value are different, performing clock synchronization based on the time stamp information.
2. The sampling method according to claim 1, wherein the sampling the second pulse information with a first clock signal and a second clock signal to obtain a first sampling signal and a second sampling signal, respectively, includes;
Determining a sampling value of the second pulse information at each first jump edge of the first clock signal to obtain the first sampling signal;
and determining a sampling value of the second pulse information at each first jump edge of the second clock signal to obtain the second sampling signal.
3. The sampling method of claim 1, further comprising:
sampling the detection signal for N times by adopting the first clock signal and the second clock signal to obtain N groups of sampling results; each set of the sampling results comprises a first sampling signal and a second sampling signal; wherein the detection signals are random signals uniformly distributed in the time domain;
For each set of the sampling results, performing: taking a first jump edge of the first sampling signal as a sampling point, determining a first sampling value of the first sampling signal at the sampling point, and determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal;
The N groups of sampling results comprise: n1 sets of first sampling results and n2 sets of second sampling results; wherein the first sampling value and the second sampling value in the first sampling result are the same; the first sampling value and the second sampling value in the second sampling result are different; and determining the phase drift amounts of the first clock signal and the second clock signal according to the total number N of the sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results, and adjusting the phases of the first clock signal and the second clock signal according to the phase drift amounts.
4. A sampling method according to claim 3, wherein the amount of phase shift S of the first clock signal and the second clock signal is determined according to the following formula:
S＝(n1-n2)*360°/(2*N)。
5. a sampling method according to claim 3, wherein the clock frequency of the first clock signal is 1GHz;
The detection signal is a signal obtained by frequency division of a clock signal with the clock frequency of 999M Hz.
6. A clock synchronization method of a distributed network, wherein each node of the distributed network comprises a clock module and a processing module;
the clock synchronization method comprises the following steps:
the clock module sends the time stamp information and the second pulse information to the processing module;
The processing module performs the sampling method according to any one of claims 1 to 5, and samples the second pulse information;
If the first sampling value obtained by the sampling of the processing module is the same as the second sampling value, the processing module adds 1 clock cycle to the data of the time stamp information and then updates the data into an internal real-time clock; and if the first sampling value obtained by the sampling of the processing module is different from the second sampling value, the processing module directly updates the data of the time stamp information into an internal real-time clock.
7. A sampling circuit, comprising:
the first sampling module is used for receiving a first clock signal and second pulse information, sampling the second pulse information by adopting the first clock signal and outputting a first sampling signal;
The second sampling module is used for receiving a second clock signal and the second pulse information, sampling the second pulse information by adopting the second clock signal and outputting a second sampling signal;
The first sampling value extraction module is electrically connected with the first sampling module and is used for determining a first sampling value of the first sampling signal at a sampling point and outputting the first sampling value; the sampling point is a first jump edge of the first sampling signal, and the first jump edge jumps from a first value to a second value;
And the second sampling value extraction module is electrically connected with the second sampling module and is used for determining a second sampling value of the second sampling signal at the sampling point of the first sampling signal and outputting the second sampling value.
8. The sampling circuit of claim 7, further comprising:
The detection signal generation module is electrically connected with the first sampling module and the second sampling module and is used for generating detection signals;
the counting module is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the total number N of sampling results, the number N1 of the first sampling results and the number N2 of the second sampling results.
9. The sampling circuit of claim 8, wherein the counting module comprises: a first counter, a second counter, and a third counter;
The first counter is electrically connected with the first sampling value extraction module and is used for counting the total number N of the sampling results;
The second counter is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the number of the first sampling results;
The third counter is electrically connected with the first sampling value extraction module and the second sampling value extraction module and is used for counting the number of the second sampling results.
10. The sampling circuit of claim 8, further comprising: and an enabling switch electrically connected with the counting module.
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| PCT/CN2021/074484 WO2022160283A1 (en) | 2021-01-29 | 2021-01-29 | Sampling method, sampling circuit, and clock synchronization method of distributed network |
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