CN104660359A - Clock frequency offset detection method, device and equipment - Google Patents
Clock frequency offset detection method, device and equipment Download PDFInfo
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- CN104660359A CN104660359A CN201310595219.6A CN201310595219A CN104660359A CN 104660359 A CN104660359 A CN 104660359A CN 201310595219 A CN201310595219 A CN 201310595219A CN 104660359 A CN104660359 A CN 104660359A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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Abstract
The invention provides a clock frequency offset detection method, device and equipment, and belongs to the field of communication. In a communication network, the clock frequency offset detection method comprises the following steps: firstly, according to the state of each clock terminal of a clock node to be detected, determining a clock terminal to be detected of the clock node; secondly, judging whether a clock source corresponding to the clock terminal to be detected can be locked or not, and if the clock source corresponding to the clock terminal to be detected cannot be locked, acquiring a time synchronization message of the clock terminal to be detected as a frequency offset detection signal; finally, according to the frequency offset detection signal, acquiring a frequency offset value of the clock terminal to be detected. According to the clock frequency offset detection method, frequency offset detection can be performed on a synchronous clock in the communication network, without using other instruments and equipment, so that whether clock synchronization is achieved or not and whether a false synchronization phenomenon exists or not are judged, and the frequency offset detection on a network clock can be achieved more accurately and simply.
Description
Technical field
The present invention relates to the communications field, be specifically related to method, device and equipment that a kind of clock frequency deviation detects.
Background technology
In various telecommunication service, PTN network and SDH transport network, for guaranteeing the integrality of timing transmission, net synchronizing quality be there are certain requirements.In the synchronous system of net, by locking the method for upper level timing reference input step by step, finally require that whole net locks same clock reference source.
The clock synchronous of the whole network finally can be realized by the pattern locking upper level timing reference input step by step.Under normal circumstances, after clock synchronous, business there will not be the error code caused because clock there is frequency deviation.But, when needing to understand between 2 in clock network whether there is frequency deviation, when whether really locking, need a kind of frequency deviation detection technique.In addition, when the business of Internet Transmission creates error code, when the display of point-to-point analysis clock lock situation locks, also can be detected by frequency deviation and determine whether there is clock vacation lock phenomenon.
In traditional clock is safeguarded, can only be watched by clock status and whether locking, unrealized FREQ frequency deviation performance monitoring, therefore really can not judge whether the clock quality in network meets the requirements.When business damaged phenomenon has appearred in scene, can only be measured by meter locale, just can determine whether it is the fault caused because of frequency deviation, when equipment also cannot realize not relying on instrument, measure frequency deviation, detect cumbersome, complicated operation.
Summary of the invention
The technical problem underlying that the embodiment of the present invention will solve is to provide a kind of clock frequency deviation detection method, device and equipment, and measuring synchronised clock frequency departure in solution communication network needs test instrumentation and the problem of complex operations.
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of clock frequency deviation detection method, comprising:
The clock port to be measured of this clock node is determined according to the state of each clock port of clock node to be measured;
Judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal;
The frequency deviation value of described clock port to be measured is obtained according to described frequency deviation detection signal.
In an embodiment of the present invention, the described frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal comprises:
In Preset Time, obtain described frequency deviation detection signal frequency deviation phase place and;
The frequency deviation value of described clock port to be measured is calculated according to described offset phase with the time value of described default detection time.
In an embodiment of the present invention, described in Preset Time, obtain the frequency deviation phase place of described frequency offset signal and comprise:
Within the detection time of presetting, gather the timestamp of each time synchronized message;
Carry out filtering according to described timestamp and calculate offset phase;
Calculate each offset phase obtained in described default detection time offset phase and.
In an embodiment of the present invention, whether the described clock source judging that described clock port to be measured is corresponding can be locked and comprise:
Judge whether the frequency deviation of the clock signal of described clock port to be measured is greater than losing lock frequency deviation threshold value;
Or judge that whether the crystal oscillator producing described clock source is aging.
In an embodiment of the present invention, when the described clock source judging that described clock port to be measured is corresponding whether can be locked the frequency deviation comprising the clock signal judging described clock port to be measured whether be greater than losing lock frequency deviation threshold value time, comprising:
The clock signal of described acquisition clock port to be measured;
In default gate time, synchronous counting is carried out to the clock signal of described clock port to be measured and default reference clock signal, obtain the first umber of pulse of the clock signal of described clock port to be measured in this default gate time and the second umber of pulse of described reference clock signal, until timing reaches default gate time;
Calculate the frequency deviation value of the difference between the first umber of pulse and described second umber of pulse as described clock port to be measured;
Judge whether described frequency deviation value is greater than losing lock frequency deviation threshold value.
In an embodiment of the present invention, the clock signal of described acquisition clock port to be detected is Article 1 effective downstream clock signal of described clock port to be measured.
In an embodiment of the present invention, described method also comprises: after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, whether the described frequency deviation value relatively obtained is greater than the first default frequency deviation threshold value, if so, then reports Threshold Crossing Alert; And/or after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, compare the described frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then report losing lock alarm.
In an embodiment of the present invention, determine that clock port to be measured comprises according to the state of each clock port of clock node to be measured:
Be from the clock port of clock port and/or passive clock port as clock port to be measured using at least one state in each for clock node to be measured clock port.
In an embodiment of the present invention, the time synchronized message of described clock port to be measured comprises:
When described clock port to be measured is from clock port, obtain this time synchronized message from clock port as frequency deviation detection signal;
When described clock port to be measured is passive clock port, trigger the time synchronized message between this clock port to be measured master clock port corresponding with it, obtain the time synchronized message of this clock port to be measured as frequency deviation detection signal.
For solving the problems of the technologies described above, the invention provides a kind of clock frequency deviation checkout equipment, comprising: at least one processor,
Described processor is used for the clock port to be measured determining this clock node according to the state of each clock port of clock node to be measured;
Described processor is also for judging whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal; And the frequency deviation value of described clock port to be measured is obtained according to described frequency deviation detection signal.
For solving the problem, the invention provides a kind of clock frequency deviation checkout gear, described device comprises selects module, judge module and detection module:
Described selection module is used for determining clock port to be measured according to the port status of each clock of clock node to be measured;
Described judge module is for judging whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal;
Described detection module is used for the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal.
In an embodiment of the present invention, described detection module comprises acquisition submodule and frequency offset calculation submodule:
Described acquisition submodule be used in Preset Time, obtain described frequency deviation detection signal frequency deviation phase place and;
Described frequency offset calculation submodule is used for calculating the frequency deviation value of described clock port to be measured according to described offset phase with the time value of described default detection time.
In an embodiment of the present invention, described acquisition submodule comprises collecting unit, filter unit and computing unit:
Described collecting unit is used for, within the detection time of presetting, gathering the timestamp of each time synchronized message successively;
Described filter unit is used for carrying out filtering according to described timestamp and calculates offset phase;
Described computing unit for calculate each offset phase obtained in described default detection time offset phase and.
In an embodiment of the present invention, described judge module comprises collection submodule, counting submodule, calculated difference submodule and losing lock judge submodule:
Described collection submodule is for obtaining the clock signal of described clock port to be measured;
Described counting module is used for carrying out synchronous counting to the clock signal of described clock port to be measured and default reference clock signal in default gate time, obtain the first umber of pulse of the clock signal of described clock port to be measured in this default gate time and the second umber of pulse of described reference clock signal, until timing reaches default gate time;
Described mathematic interpolation submodule is for calculating the frequency deviation value of the difference between the first umber of pulse and described second umber of pulse as described clock port to be measured;
Described losing lock judges that submodule is for judging whether described frequency deviation value is greater than losing lock frequency deviation threshold value.
In an embodiment of the present invention, described device also comprises reporting module, for after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, compares the described frequency deviation value obtained and whether is greater than the first default frequency deviation threshold value, if so, then Threshold Crossing Alert is reported; And/or after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, compare the described frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then report losing lock alarm.
The invention has the beneficial effects as follows:
Clock frequency deviation detection method provided by the invention, device and equipment, determine the clock port to be measured of this clock node according to the state of each clock port of clock node to be measured; Then judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of clock port to be measured as frequency deviation detection signal; The last frequency deviation value obtaining clock port to be measured according to frequency deviation detection signal.This testing process without any need for supporting test instrumentation; And the operation that relatively existing use test instrument carries out detecting is more simple, also can not to be forbidden etc. the result of factor impact test because of test instrumentation, the test result therefore obtained is also more accurate.
Accompanying drawing explanation
The clock frequency deviation detection method schematic flow sheet that Fig. 1 provides for an embodiment of the present invention;
The clock signal distributed architecture schematic diagram that Fig. 2 provides for an embodiment of the present invention;
The PTP message distributed architecture schematic diagram that Fig. 3 provides for an embodiment of the present invention;
Fig. 4 for an embodiment of the present invention provide based on clock signal detection method schematic flow sheet one;
Fig. 5 for an embodiment of the present invention provide based on PTP message frequency deviation detection method schematic flow sheet one;
The clock signal frequency deviation detection method schematic flow sheet two that Fig. 6 provides for an embodiment of the present invention;
The apparatus structure schematic diagram of the detection frequency deviation of clock that Fig. 7 provides for an embodiment of the present invention.
Embodiment
By reference to the accompanying drawings the embodiment of the present invention is described in further detail below by embodiment.
At present in order to realize the method for clock synchronization of ad employing by locking upper level timing reference input step by step, finally require that whole net locks same clock reference source.If to need to judge in network that whether when really locking, and needs a kind of frequency deviation detection technique at 2.The embodiment of the present invention provides a kind of clock frequency deviation detection method, can realize simply accurately detecting the frequency deviation of clock, is further detailed below in conjunction with concrete method.
Shown in Figure 1, the clock frequency deviation detection method that the present embodiment provides, it comprises the following steps:
Step S101: the port status according to each clock of node to be measured determines clock port to be measured, that is using at least one in each for node to be measured clock port from clock port and/or passive clock port as port to be measured.By observing each node of network clocking, determine the port status of each node, as being master clock port, from clock port, passive clock port.Select at least there is one from clock port or passive clock port as port to be measured.If there is no, this node just can not as node to be measured.
Step S102: judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of clock port to be measured as frequency deviation detection signal.Wherein, judge whether clock source that clock port to be measured is corresponding can be locked to comprise: judge whether the frequency deviation of the clock signal of clock port to be measured is greater than losing lock frequency deviation threshold value or judges that whether the crystal oscillator producing clock source is aging.Further, when clock port to be measured is from clock port, obtain this time synchronized message from clock port as frequency deviation detection signal; When clock port to be measured is passive clock port, trigger the time synchronized message between this clock port to be measured master clock port corresponding with it, obtain the time synchronized message of this clock port to be measured as frequency deviation detection signal.
Step S103: the frequency deviation value obtaining clock port to be measured according to frequency deviation detection signal, is included in default detection time, gathers the timestamp of each time synchronized message successively; Carry out filtering according to gathered timestamp and calculate offset phase; Calculate the offset phase of each offset phase that obtains within the detection time of presetting and; According to calculating offset phase and calculating the frequency deviation value of this clock port to be measured with the time value of this detection time of presetting.
Further, support that, to webmaster reported data, report cycle gives tacit consent to 15 minutes, comprises maximum, minimum value, mean value; Support real-time query, support Threshold Crossing Alert, and alarming threshold value can be set.Specifically be included in after obtaining the frequency deviation value of clock port to be measured according to detection signal, compare the frequency deviation value obtained and whether be greater than the first default frequency deviation threshold value, if so, then report Threshold Crossing Alert; And/or after the frequency deviation value obtaining clock port to be measured according to detection signal, compare the frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then report losing lock alarm.
Further, this function operation, in active detecting pattern, is supported manually to be set to open/block system.
In above-mentioned steps 102, judge whether the clock source that this clock port to be measured is corresponding can be locked, judge that whether the crystal oscillator producing clock source is aging, can directly observe by artificial or undertaken by other detection methods or instrument, further, judge whether the frequency deviation of the clock signal of clock port to be measured is greater than losing lock frequency deviation threshold value and physical layer clocks signal can be adopted as detection, by carrying out frequency deviation performance monitoring to the clock signal of physical layer.Can manually specify, just refer to that artificial selection will detect the clock signal in the signal which port comes in or automatically detect, can according to SSM algorithm according to present node, select an optimum clock from all taking out clock, automatic detection just detects this and optimum takes out clock.Composition graphs 2 is described in detail further: as shown in Figure 2,1 clock source and 4 nodes are had: node 21 i.e. NE21, node 22 i.e. NE22, node 23 i.e. NE23, node 24 i.e. NE24 in clock zone, it should be noted that for the node 24 i.e. port one of NE24 and Port1 port be that port 2 i.e. Port2 port is passive clock port from clock port.Wherein, the solid arrow between figure interior joint represents to be configured with between 2 takes out clock, and consistent with the direction of transfer of present clock.Wherein, the dotted arrow between figure interior joint represents to be configured with between 2 takes out clock, but clock Pending The Entry Into Force.Further, node NE21, NE22, NE23 have the clock signal in a direction, namely be the clock of taking out of port one and Port1 port be node current clock signal, calculating present node downstream clock signal according to SSM protocol stack, is clock signal to be detected with Article 1 effective downstream clock signal.That is with its downstream clock signal, Article 1 effective downstream clock signal is as detection clock signal.Node NE24 is had to the clock signal of both direction: the clock of taking out of the Port1 port of (1) node NE24 is node current clock signal; (2) port 2 of the node NE24 i.e. clock of taking out of Port2 port is clock signal in node priority list.If adopt the port one of node NE24 and the clock of taking out of Port1 port to be node current clock signal, just using Article 1 effective downstream clock signal of the downstream clock signal of node NE24 as detection clock signal; If the clock of taking out adopting the Port2 port of node NE24 is clock signal in node priority list, survey clock signal with regard to finger prosthesis regular inspection and namely trigger this by the clock synchronous between the port master clock port corresponding with it, obtain the clock signal of this passive clock port as detection signal.Need to it should be noted that the Port2 port of node NE22, NE23 is as master clock port.
Further, comprise the following steps composition graphs 4 when whether the frequency deviation comprising the clock signal judging clock port to be measured is greater than losing lock frequency deviation threshold value be described when judging whether clock source that clock port to be measured is corresponding can be locked:
Step S401: the clock signal obtaining clock port to be measured, wherein obtain clock signal and comprise artificial appointment, just refer to that artificial selection will detect the clock signal in the signal which port comes in or automatically detect, be exactly that present node can according to SSM algorithm, select an optimum clock from all taking out clock, automatic detection just detects this and optimum takes out clock.
Step S402: in default gate time, synchronous counting is carried out to the clock signal of clock port to be measured and default reference clock signal, obtain the first umber of pulse of the clock signal of clock port to be measured in this default gate time and the second umber of pulse of reference clock signal, until timing reaches default gate time.Be specially and the clock signal of clock port to be measured is latched with the reference clock signal preset, namely the clock signal wherein latching port to be measured and the reference clock signal preset latch the clock signal of port to be measured and the reference clock signal preset, namely to while the clock signal of port to be measured and the reference clock signal preset to its rising clock along or decline clock along that is needing to carry out genlocing to two signals.Clock signal of system is the clock of Devices to test itself.Further, time counter can be clock signal of system, also can be frequency division or the frequency-doubled signal of system clock source.When latching successfully, start timing, obtain the first umber of pulse of the clock signal of clock port to be measured in this detection time and the second umber of pulse of reference clock signal, until timing reaches default detection time, specifically be included in detection time, when locking successfully, just start clock signal to be detected and the umber of pulse passed through of reference clock signal i.e. the number of times of rising edge or trailing edge.When timing arrives the detection time of presetting, the umber of pulse just reading the clock signal of clock port to be measured is at that time the first umber of pulse, and the umber of pulse of reference clock signal is the second umber of pulse.
Step S403: calculate the frequency deviation value of the difference between the first umber of pulse and the second umber of pulse as clock port to be measured.
Step S404: judge whether frequency deviation value is greater than losing lock frequency deviation threshold value.Be specially value step S403 being calculated gained, by comparing with the losing lock frequency deviation threshold value preset, if its value is greater than default losing lock frequency deviation threshold value just send losing lock warning.
In above-mentioned steps 102, obtain sync message and be specially when clock port to be measured is for during from clock port, obtain this time synchronized message from clock port as frequency deviation detection signal; When clock port to be measured is passive clock port, trigger the time synchronized message between this clock port to be measured master clock port corresponding with it, obtain the time synchronized message of this clock port to be measured as frequency deviation detection signal.Composition graphs 3 is described in detail further: as shown in Figure 3, and it is that namely the time synchronized message of 1588 time synchronized sends 1588 messages namely from the message of passitive port from the message of slaver port or device trigger that detection messages specifically comprises detection messages.Wherein, master port (master Port): the port issuing lock in time, from port (slavePort): the port receiving lock in time, passive port (passive Port): the port neither receive lock in time, also externally not issuing lock in time.Composition graphs 3 is described in detail further: as shown in Figure 3, has 6 nodes in clock zone: node 11 i.e. NE11, node 12 i.e. NE12, node 13 i.e. NE13, node 14 i.e. NE14, node 15 i.e. NE15, node 16 i.e. NE16.Wherein, the line between figure interior joint represents and is configured with 1588 time synchronized between 2, and two ports of line are PTP port.Wherein, the direction of arrow of line is PTP time synchronized direction.Wherein, the dotted line between figure interior joint represents to there is passive port between 2.It should be noted that here using port one as Port1 port, port 2 as Port2 port, the PTP port status of current each node port:
NE11 Port1:master
NE11 Port2:master
NE12 Port1:slave
NE12 Port2:master
NE12 Port3:master
NE13 Port1:slave
NE14 Port1:slave
NE14 Port2:passive
NE15 Port1:slave
NE15 Port2:master
NE16 Port1:slave
NE16 Port2:master
As seen from the figure slaver port is existed for node NE12, NE13, NE15, NE16, that is there is the time synchronized message of 1588 time synchronized, can directly using the message of its slaver port as the message of measured signal i.e. Port1 port; Not only slaver port is existed but also there is passive port for node NE14, so not only the message of slaver port can have been selected but also can select the message of passive port, message for passive port needs by device trigger that it sends 1588 messages, detect its message again, both trigger adjacent node NE16Port2:master and send message to it, that is for node NE14, both can by the time synchronized message of 1588 time synchronized of detection node NE14Port1, also can 1588 messages by device trigger of detection node NE14Port2.
Above-mentioned steps 103 was also included within detection time, the phase deviation value that writing time is synchronous and offset value, cumulative obtain phase place and, appraising frequency bias value is according to detection time and phase place and calculate, detection time is current time is T0, and after elapsed time T, the time is T0+T.The further comprising the steps composition graphs 5 that comprises is described:
Step S501: within the detection time of presetting, gather the timestamp of each time synchronized message successively.
Step S502: carry out filtering according to timestamp and calculate offset phase.
Step S503: calculate the offset phase of individual offset phase that obtains in detection time of presetting with.
Step S504: according to calculating offset phase and calculating the frequency deviation value of clock port to be measured with the time value of the detection time of presetting.
The present embodiment is specifically described with Fig. 2 interior joint 24 and composition graphs 6 and such as carries out appraising frequency bias with the node NE24 in Fig. 2, and wherein detection signal monitor mode is selected current detection signal FREQ frequency deviation performance monitoring that is to from port signal.Wherein, detecting clock signal is current reference clock signal, and the clock signal namely entrained by node NE24Port1 port is as detection signal.Time counter, reference signal is node NE24 clock signal of system, and the frequency-doubled signal after locking is as time counter.Time counter, reference signal is node NE24 system clock, and the frequency-doubled signal after locking is as time counter.Further, clock signal of system is the clock signal of Devices to test itself.Further, time counter can be system clock source, also can be frequency division or the frequency-doubled signal of system clock source, also can be clock signal of system.Concrete enforcement comprises the following steps:
Step S601: extract test signal from from clock port (NE24Port1 port), that is extracting clock signal from NE24Port1 port is detection signal, namely using the Article 1 of its port effective downstream clock signal as detection signal.
Step S602: latch the initial rising clock edge of detection signal, initialization time counter, time counter is set to 0.That is need synchronously to process detection signal and reference clock signal simultaneously, carry out the accuracy ensureing data measured simultaneously.
Step S603: during N number of pulse of detection signal, read time counter, time counter current value is M.That is within detection time, in other words within a period of time, arrive the detection time of specifying and presetting in other words, the umber of pulse of detection signal and reference signal is added up, detection signal, the umber of pulse namely detecting clock signal is the first umber of pulse is N, reference signal i.e. reference clock signal, namely time counter current number, namely the umber of pulse of reference signal is the second umber of pulse M.
Step S604: calculate current frequency offset value according to N and M value, that is according to the first obtained above umber of pulse M and the second umber of pulse N, calculating its difference is frequency deviation value, it is namely the frequency deviation value of current detection clock signal, namely present port clock signal is relative to the frequency deviation value of master port, namely relative to the frequency deviation value of master clock port clock signal.
Frequency offset calculation in like manner for other nodes and other ports can realize, and just the acquisition of the port clock signal of detection signal is had certain difference, does not affect the solution of the present invention.
Report testing result further, after obtaining frequency deviation result, equipment reported result, to webmaster, reports content to be detect appraising frequency bias value and the detection clock information signal of clock signal relative system clock.
Further, for the network of deployment 1588 time synchronized, to adjacent 2 node devices, when input reference frequency deviation is excessive or crystal oscillator is aging, cannot locked clock source, when causing carrying out clock synchronous, or learn cannot carry out clock synchronous according to the losing lock warning reported, the PTP event message between supporting by adjacent node realizes appraising frequency bias and inspection of crossing the border.Another embodiment composition graphs 3, Fig. 5 are described in detail, and will carry out appraising frequency bias in embodiment to the node NE14 in Fig. 3.Two PTP port statuss of NE14 are that slave and passive is namely from port status and passive port status respectively, so carry out frequency deviation detection to the slave port of NE14 and passive port in the present embodiment, specifically comprise: the PTP port status obtaining node NE14, respectively: (1) NE14port2:passive
（2）NE14port1：slaver。Wherein, the frequency deviation for NE14port2 port detects namely for the detection of passive port: record current time T0, completes detection after the time have passed through T time, and namely the moment of time arrival T0+T completes detection; Record current time while, intialization phase deviation and: Theta(unit is ns)=0; Device trigger sends 1588 messages, detects and responds the message from passitive port (i.e. NE14port2 port); Service time, counter gathered t1, t2, t3, t4 timestamp, and filtering calculates offset and Offset=[t2-t1-t4+t3]/2; Cumulative each offset value, Theta=Theta+offset; Judge whether current time arrives T0+T; Further, when current time does not arrive T0+T, repeat the detection of offset value and add up; Further, when current time arrives T0+T, the frequency deviation completing this detects; Calculate frequency deviation value, f=Theta/T, unit is ppb.
Wherein, for NE14port1 port frequency deviation detect namely for the detection of passive port: record current time while, intialization phase deviation and: Theta(unit is ns)=0; Detection messages is the time synchronized message of 1588 time synchronized, detects and responds the message from slaver port (i.e. NE14port1 port); Service time, counter gathered t1, t2, t3, t4 timestamp, and namely filtering calculate offset; The offset value that Offset=[t2-t1-t4+t3]/2 is cumulative each, Theta=Theta+offset; Judge whether current time arrives T0+T; Further, when current time does not arrive T0+T, repeat the detection of offset value and add up; Further, when current time arrives T0+T, the frequency deviation completing this detects; Calculate frequency deviation value, f=Theta/T, unit is ppb.
Report testing result further; Report testing result specifically to comprise and report frequency deviation value and detected signal information.Specifically comprise further and report content to be the appraising frequency bias value (ppb) of reference source relative system clock and detect clock source information, report content to be slaver port relative to the appraising frequency bias value of master and corresponding ptp logical port number or report content to be passive port relative to the appraising frequency bias value of master and corresponding ptp logical port number.
The present invention also provides a kind of clock frequency deviation checkout gear, and as shown in Figure 7, device comprises: select module, judge module, detection module, wherein: select module to be used for determining clock port to be measured according to the port status of each clock of clock node to be measured; Judge module is for judging whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of clock port to be measured as frequency deviation detection signal; Detection module is used for the frequency deviation value obtaining clock port to be measured according to frequency deviation detection signal.Further, module is selected to determine that clock port to be measured comprises according to the port status of each clock of clock node to be measured: using at least one in each for clock node to be measured clock port from clock port and/or passive clock port as clock port to be measured.
Further, the time synchronized message that judge module obtains clock port to be measured comprises: when clock port to be measured is for during from clock port, obtain this time synchronized message from clock port as frequency deviation detection signal; When clock port to be measured is passive clock port, trigger the time synchronized message between this clock port to be measured master clock port corresponding with it, obtain the time synchronized message of this clock port to be measured as frequency deviation detection signal.
Comprise at above-mentioned detection module and obtain submodule and frequency offset calculation submodule, wherein, obtain submodule and be used in Preset Time, obtain frequency deviation detection signal frequency deviation phase place and; Frequency offset calculation submodule is used for calculating the frequency deviation value of clock port to be measured according to offset phase with the time value of the detection time of presetting.Further, comprise collecting unit, filter unit and computing unit at described acquisition submodule, wherein, collecting unit is used for, within the detection time of presetting, gathering the timestamp of each time synchronized message; Filter unit is used for carrying out filtering according to timestamp and calculates offset phase; Computing unit for calculate in default detection time each offset phase obtained offset phase and.
Comprising collection submodule at above-mentioned judge module, counting submodule, calculated difference submodule and losing lock judge submodule, wherein, gathering submodule for obtaining the clock signal of clock port to be measured; Counting submodule is used for carrying out synchronous counting to the clock signal of clock port to be measured and default reference clock signal in default gate time, obtain the first umber of pulse of the clock signal of clock port to be measured in this default gate time and the second umber of pulse of reference clock signal, until timing reaches default gate time; Mathematic interpolation submodule is for calculating the frequency deviation value of the difference between the first umber of pulse and the second umber of pulse as clock port to be measured; Losing lock judges that submodule is for judging whether frequency deviation value is greater than losing lock frequency deviation threshold value.
Further, in said apparatus, also comprise reporting module, for after the frequency deviation value obtaining clock port to be measured according to frequency deviation detection signal, compare the frequency deviation value obtained and whether be greater than the first default frequency deviation threshold value, if so, then report Threshold Crossing Alert; And/or after the frequency deviation value obtaining described clock port to be measured according to frequency deviation detection signal, compare the frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then go up losing lock alarm.
The present invention also provides a kind of clock frequency deviation checkout equipment, and this frequency deviation checkout equipment comprises at least one processor.Wherein processor is used for the clock port to be measured determining this clock node according to the state of each clock port of clock node to be measured; And judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of clock port to be measured as frequency deviation detection signal; And the frequency deviation value of clock port to be measured is obtained according to frequency deviation detection signal.The corresponding program command of the concrete adjustable use of processor in the present embodiment realizes above-mentioned functions, and the clock frequency deviation checkout equipment now in the present embodiment also can comprise further for stored program instruction and the memory called for processor.
The embodiment of the present invention provides a kind of storage medium, and described storage medium is according to the execution that gives an order:
The clock port to be measured of this clock node is determined according to the state of each clock port of clock node to be measured;
Judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal;
The frequency deviation value of described clock port to be measured is obtained according to described frequency deviation detection signal.
Should be understood that, the present embodiment frequency deviation checkout equipment can be any hardware entities device of concrete memory function in clock synchronous network and processing capacity.Such as in GPS network network, realize clock synchronous between each base station, this frequency deviation checkout equipment can be arranged in each base station, also can arrange and detect the clock synchronous of this network in the terminal.In local network again such as in office, this checkout equipment can be arranged in the server, also can be arranged in each technology terminal and detect to the clock synchronous of local network.
The all or part of step that one of ordinary skill in the art will appreciate that in said method is carried out instruction related hardware by program and is completed, and program can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can use one or more integrated circuit to realize.Correspondingly, each module/unit in above-described embodiment can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
These are only the preferred embodiments of the present invention; certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection range that all should belong to the claim appended by the present invention.
Claims (15)
1. a clock frequency deviation detection method, is characterized in that, comprising:
The clock port to be measured of this clock node is determined according to the state of each clock port of clock node to be measured;
Judge whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal;
The frequency deviation value of described clock port to be measured is obtained according to described frequency deviation detection signal.
2. clock frequency deviation detection method as claimed in claim 1, is characterized in that, the described frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal comprises:
In Preset Time, obtain described frequency deviation detection signal frequency deviation phase place and;
The frequency deviation value of described clock port to be measured is calculated according to described offset phase with the time value of described default detection time.
3. clock frequency deviation detection method as claimed in claim 2, is characterized in that, described in Preset Time, obtains the frequency deviation phase place of described frequency offset signal and comprises:
Within the detection time of presetting, gather the timestamp of each time synchronized message;
Carry out filtering according to described timestamp and calculate offset phase;
Calculate each offset phase obtained in described default detection time offset phase and.
4. clock frequency deviation detection method as claimed in claim 1, it is characterized in that, whether the described clock source judging that described clock port to be measured is corresponding can be locked and comprise:
Judge whether the frequency deviation of the clock signal of described clock port to be measured is greater than losing lock frequency deviation threshold value;
Or judge that whether the crystal oscillator producing described clock source is aging.
5. clock frequency deviation detection method as claimed in claim 4, it is characterized in that, when the described clock source judging that described clock port to be measured is corresponding whether can be locked the frequency deviation comprising the clock signal judging described clock port to be measured whether be greater than losing lock frequency deviation threshold value time, comprising:
Obtain the clock signal of described clock port to be measured;
In default gate time, synchronous counting is carried out to the clock signal of described clock port to be measured and default reference clock signal, obtain the first umber of pulse of the clock signal of described clock port to be measured in this default gate time and the second umber of pulse of described reference clock signal, until timing reaches default gate time;
Calculate the frequency deviation value of the difference between the first umber of pulse and described second umber of pulse as described clock port to be measured;
Judge whether described frequency deviation value is greater than losing lock frequency deviation threshold value.
6. frequency deviation of clock method as claimed in claim 5, it is characterized in that, the clock signal of described acquisition clock port to be detected is Article 1 effective downstream clock signal of described clock port to be measured.
7. the clock frequency deviation detection method as described in any one of claim 1-6, it is characterized in that, described method also comprises: after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, whether the described frequency deviation value relatively obtained is greater than the first default frequency deviation threshold value, if so, then Threshold Crossing Alert is reported; And/or after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, compare the described frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then report losing lock alarm.
8. the clock frequency deviation detection method as described in any one of claim 1-6, is characterized in that, determines that clock port to be measured comprises according to the state of each clock port of clock node to be measured:
Be from the clock port of clock port and/or passive clock port as clock port to be measured using at least one state in each for clock node to be measured clock port.
9. clock frequency deviation detection method as claimed in claim 8, it is characterized in that, the time synchronized message of described clock port to be measured comprises:
When described clock port to be measured is from clock port, obtain this time synchronized message from clock port as frequency deviation detection signal;
When described clock port to be measured is passive clock port, trigger the time synchronized message between this clock port to be measured master clock port corresponding with it, obtain the time synchronized message of this clock port to be measured as frequency deviation detection signal.
10. a clock frequency deviation checkout equipment, is characterized in that, comprising: at least one processor;
Described processor is used for the clock port to be measured determining this clock node according to the state of each clock port of clock node to be measured;
Described processor is also for judging whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal, and obtain the frequency deviation value of described clock port to be measured according to described frequency deviation detection signal.
11. 1 kinds of clock frequency deviation checkout gears, is characterized in that, described device comprises selects module, judge module and detection module:
Module is selected to be used for determining clock port to be measured according to the port status of each clock of clock node to be measured;
Judge module is for judging whether the clock source that this clock port to be measured is corresponding can be locked; As no, then obtain the time synchronized message of described clock port to be measured as frequency deviation detection signal;
Detection module is used for the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal.
12. clock frequency deviation checkout gears as claimed in claim 11, is characterized in that, described detection module comprises acquisition submodule and frequency offset calculation submodule:
Described acquisition submodule be used in Preset Time, obtain described frequency deviation detection signal frequency deviation phase place and;
Described frequency offset calculation submodule is used for calculating the frequency deviation value of described clock port to be measured according to described offset phase with the time value of described default detection time.
13. clock frequency deviation checkout gears as claimed in claim 12, it is characterized in that, described acquisition submodule comprises collecting unit, filter unit and computing unit:
Described collecting unit is used for, within the detection time of presetting, gathering the timestamp of each time synchronized message successively;
Described filter unit is used for carrying out filtering according to described timestamp and calculates offset phase;
Described computing unit for calculate each offset phase obtained in described default detection time offset phase and.
14. clock frequency deviation checkout gears as claimed in claim 13, is characterized in that, described judge module comprises collection submodule, counting submodule, calculated difference submodule and losing lock judge submodule:
Described collection submodule is for obtaining the clock signal of described clock port to be measured;
Described counting submodule is used for carrying out synchronous counting to the clock signal of described clock port to be measured and default reference clock signal in default gate time, obtain the first umber of pulse of the clock signal of described clock port to be measured in this default gate time and the second umber of pulse of described reference clock signal, until timing reaches default gate time;
Described mathematic interpolation submodule is for calculating the frequency deviation value of the difference between the first umber of pulse and described second umber of pulse as described clock port to be measured;
Described losing lock judges that submodule is for judging whether described frequency deviation value is greater than losing lock frequency deviation threshold value.
15. clock frequency deviation checkout gears as described in claim 9-14, it is characterized in that, described device also comprises reporting module, for after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, whether the described frequency deviation value relatively obtained is greater than the first default frequency deviation threshold value, if so, then Threshold Crossing Alert is reported; And/or after the frequency deviation value obtaining described clock port to be measured according to described frequency deviation detection signal, compare the described frequency deviation value obtained and whether be greater than the second default frequency deviation threshold value, if so, then report losing lock alarm.
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| CN201310595219.6A CN104660359B (en) | 2013-11-21 | 2013-11-21 | A kind of method, apparatus and equipment of clock frequency deviation detection |
| PCT/CN2014/075381 WO2015074371A1 (en) | 2013-11-21 | 2014-04-15 | Clock frequency offset detection method, apparatus and device |
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| CN201310595219.6A CN104660359B (en) | 2013-11-21 | 2013-11-21 | A kind of method, apparatus and equipment of clock frequency deviation detection |
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| CN104660359B (en) | 2019-01-11 |
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