JP5649555B2 - Control system and time synchronization method - Google Patents

Description

  The present invention relates to a control system and a time synchronization method, and more particularly, to a control system in which a plurality of arithmetic devices for controlling plant facilities and the like are connected via a transmission line, and a time synchronization method for each arithmetic device.

  FIG. 1 is a block diagram showing the configuration of a control system and a computing device according to the prior art, and FIG. 2 is a flowchart for explaining processing operations for synchronizing the times of a plurality of computing devices constituting the control system. The configuration of the control system and the time synchronization method of the arithmetic device according to the prior art will be described with reference to FIG.

  As shown in FIG. 1, the control system according to the prior art includes a plurality of arithmetic devices A2 to C4 to which control objects A5 to C7 of a plurality of parts in a plant facility or the like are connected, and these arithmetic devices A2. Communication path 100 to 103 (in the example shown in FIG. 1, an optical communication path) is connected to POC1, which is a control monitoring apparatus used by the user for monitoring control of .about.C4 and having system time information as master time. And are configured so as to be communicable via each other. The user can monitor and control the arithmetic devices A2 to C4 through the communication paths 100 to 103 using the POC1. In the example shown in FIG. 1, the entire communication path is shown as being connected in a loop shape, but the network needs to be configured in a loop shape, including the embodiment of the present invention. Absent.

  Each of the arithmetic devices A2 to C4 includes a processor 201 including middleware 2011, an LSI 202, and an optical signal transmission / reception unit 203, as represented by the arithmetic device A2. The LSI 202 has a time timer called a system time timer 2021 inside. The system time timer 2021 is a system in which the middleware 2011 in the processor 201 refers to a time when performing task processing for performing control of each control target, etc., and is periodically transmitted from the POC 1 The time is stored by the middleware 2011, and then time is measured by itself. Each arithmetic unit uses a time transmitted from POC 1 because a task that is not processed may occur if the value of the system time timer 2021 changes in a time zone in which a task for the control target exists. Thus, when performing time synchronization between the arithmetic devices A2 to C4, it is necessary to designate a time zone in which no task exists. The time zone in which the task does not exist can be known by monitoring each computing device from the POC 1 by the user who is an administrator. Therefore, the time zone is designated about once a day in the time zone. When the middleware 201 receives the system time information 205 from the POC 1 via the optical signal transmission / reception unit 203, the middleware 201 stores the time in a system time tie 2021 in the LSI 202.

  Next, the processing operation for setting the system time to the system time timer 2021 in order to synchronize the time of the arithmetic unit will be described with reference to FIG.

(1) First, the user transmits the time information possessed by the POC 1 to the computing device A 2 via the communication path 100 about once a day as described above using the POC 1. In the arithmetic device A2, the optical signal transmitting / receiving unit 203 receives the time information from the POC1, and provides it as the system time information 205 to the middleware 2011 in the processor 201 of the arithmetic device A2 (step F1).

(2) The middleware 2011 that has obtained the system time information 205 stores the system time information 205 obtained from the optical signal transmission / reception unit 203 in the system time timer 2021 in the LSI 202 as the system time information 204 (step F2).

(3) The system time information is stored in the system time timer of the arithmetic devices B3 and C4 by the same procedure as the processing of steps F1 and F2 described above (step F3).

  The system time is set in the system time timer 2021 of each arithmetic device by the processing described above. However, since the time synchronization processing is performed by software that is middleware, the time synchronization accuracy depends on the processing load of each arithmetic device, and the time error between the arithmetic devices is specified. (The delay in the communication path and the delay in the time setting process can be defined as an error). For this reason, the time between each arithmetic unit cannot be synchronized.

  Generally, when a problem occurs in a customer's plant equipment, the company that delivered the equipment is responsible for analyzing the cause of the problem and explaining the cause. For this reason, in order to analyze the occurrence of problems in facilities consisting of multiple arithmetic devices and controlled objects, it is important to understand the causes of the problems in chronological order. Are synchronized and corrected.

  When synchronizing / correcting the system time of each computing device, by synchronizing / correcting the system time, a program that operates by referring to the system time on the computing device may lose its operation timing and become an obstacle. In order to solve this problem, when a highly accurate time synchronization means such as IEEE 1588 is used, the software load increases, and the control processing for the original plant of the arithmetic unit may be damaged. Create a point. In addition, although it is possible to use a time synchronization method using GPS, this method has a problem that it is expensive in terms of equipment costs due to wiring installation.

  In the time synchronization processing according to the conventional technology described above, the time error between the arithmetic devices cannot be defined. Therefore, when a failure occurs in the control objects A2 to C4, the failure information is used for analyzing the failure. The problem that it becomes impossible to arrange in time series. In addition, as described above, it is possible to increase the accuracy of time synchronization by making software, but in that case, the software load on the arithmetic unit increases, which adversely affects plant control, which is the original main purpose. This will cause the problem of being affected.

  In view of the points described above, the object of the present invention is to be able to synchronize the system time among a plurality of arithmetic devices without degrading the performance of the original control processing of each arithmetic device. The object is to provide a control system in which a plurality of arithmetic devices for controlling plant facilities and the like are connected via a communication path, and a time synchronization method for each arithmetic device.

  According to the present invention, the object is to provide a control system in which a plurality of arithmetic devices are connected to each other through a communication path, and a control target is connected to each of the plurality of arithmetic devices. Each includes a processor, a system time timer, an independent network time timer dedicated to time synchronization, a frame generation means, and a frame reception means, and one of the plurality of arithmetic devices is designated as a time master. The other arithmetic device is designated as a time slave, and the processor of the arithmetic device that is the time master acquires the time of the system time timer at a constant cycle, stores it in the network time timer, and keeps counting time, The frame generation means acquires time information of the network time timer, and acquires the time of the acquired network time timer Generating a frame including information, and broadcasting the generated frame to the arithmetic device that is the time slave at a constant cycle, and the frame receiving means of the arithmetic device that is the time slave transmits the frame that has been broadcast. This is achieved by receiving the time information in the frame and storing the time information in the network time timer in the self-processing device so as to keep the time.

  According to the present invention, each computing device can synchronize the network time among a plurality of computing devices without degrading the performance of the original control processing, thereby causing a problem with the equipment to be controlled. When they occur, problem factors can be understood in chronological order, which can be used for investigating the cause.

It is a block diagram which shows the structure of the control system and arithmetic unit by a prior art. It is a flowchart explaining the processing operation | movement which synchronizes the time of the some arithmetic device which comprises the control system by a prior art. It is a block diagram which shows the structure of the control system by one Embodiment of this invention, and each arithmetic unit. It is a flowchart explaining the processing operation | movement which synchronizes the time of the some arithmetic device which comprises the control system by embodiment of this invention. It is a figure explaining the collection method of the time information when a failure occurs in the control object of the arithmetic unit in the control system according to the embodiment of the present invention shown in FIG. It is a block diagram which shows the structure of the control system by each other Embodiment of this invention, and each arithmetic unit. It is a flowchart explaining the processing operation | movement which synchronizes the time of the some arithmetic device which comprises the control system by other embodiment of this invention. It is a figure explaining the collection method of the time information when the failure occurs in the control object of the arithmetic unit in the control system according to another embodiment of the present invention shown in FIG. It is a block diagram which shows the structure of the flame | frame production | generation part in an arithmetic unit. It is a flowchart explaining the processing operation | movement of the flame | frame production | generation in the arithmetic unit containing a flame | frame production | generation part. It is a block diagram which shows the structure of the frame receiver in an arithmetic unit. It is a flowchart explaining the processing operation | movement of the frame reception in the arithmetic unit containing a frame receiving part.

  Embodiments of a control system and a time synchronization method for each arithmetic device according to the present invention will be described below in detail with reference to the drawings. In the following description, even components having the same name are different in the reference numerals given to the components for each figure, but are the same components as long as they have the same name.

  FIG. 3 is a block diagram showing the configuration of the control system and each arithmetic device according to one embodiment of the present invention, and FIG. 4 is a flowchart for explaining the processing operation for synchronizing the times of a plurality of arithmetic devices constituting the control system. Since the configuration of the control system and each arithmetic unit shown in FIG. 3 is not significantly different from that of FIG. 1 described above, only the points different from FIG. 1 will be described below.

  The configuration of the control system according to the embodiment of the present invention shown in FIG. 3 is the same as that of the prior art described with reference to FIG. 1, and the configuration of each arithmetic unit is different. That is, each of the arithmetic devices A9 to C11, as represented by the arithmetic devices A9 and B10, in the LSI 901 of the arithmetic device A9, in addition to the system time timers 9011 and 10011, a network time timer 9012 provided exclusively for time synchronization. , 10012, and a frame receiver 9013, 1003 and frame generators 9014, 10014 are added to the conventional technique. In the embodiment of the present invention, by adding network time timers 9012 and 10012 dedicated to time synchronization, time synchronization is possible without changing the values of the system time timers 9011 and 1011).

  The control system according to the embodiment of the present invention having the configuration as described above can be realized at low cost because there are few changes and new additions from the control system according to the prior art.

  Next, the processing operation for setting the time in the network time timer 9012 in order to synchronize the time of the arithmetic unit A9 will be described with reference to FIG.

(1) First, the user uses the POC 8 to transmit time information possessed by the POC 8 to the arithmetic unit A9 via the communication path 107. In the arithmetic device A9, the optical signal transmitting / receiving unit 903 receives the time information from the POC 8, and provides it to the middleware 9021 in the processor 902 of the arithmetic device A9 as the system time information 907 (step F4).

(2) The middleware 9021 that has obtained the system time information 907 stores the system time information 907 obtained from the optical signal transmission / reception unit 903 in the system time timer 9011 in the LSI 901 as the system time information 904 (step F5).

(3) The system time information is stored in the system time timer of the arithmetic devices B10 and C11 by the same procedure as the processing of steps F4 and F5 described above (step F6).

  The processing so far is the same as the processing from F1 to F3 in FIG. 2 described as processing in the prior art.

(4) Next, the user designates one of the arithmetic devices from the POC 8 as the time master. Here, the description is continued assuming that the arithmetic device A9 is designated as the time master, but the user can designate any arithmetic device as the time master. The arithmetic devices B10 and C11 not designated as the time master become time slaves (step F7).

(5) The middleware 9021 of the arithmetic device A9 designated as the time master reads the system time from the system time timer 9011 at a fixed period (about once every 4 seconds) and collects system time information 905, and the time information Is stored in the network time timer 9012. Thereafter, the network time timer 9012 keeps counting itself. By this processing, the network time timer 9012 can take a value close to the system time timer 9011 (step F8).

(6) Thereafter, the frame generation unit 9014 of the LSI 901 of the arithmetic device A9 acquires the time of the network time timer 9012 as the network time information 908, attaches the network time information 908 to the transmission frame, and generates the time information frame 909. The frame is broadcast from the optical signal transmission / reception unit 903 to the arithmetic devices B10 and C11 which are time slaves (step F9).

(7) In the arithmetic device B10 that is a time slave, the optical signal transmission / reception unit 1003 receives the time information frame 909, and the network time information of the received time information frame 909 is transmitted to the network time timer via the frame reception unit 10013 in the LSI 1001. Then, the network time timer 10012 keeps measuring the time. Similarly, the arithmetic device C11 stores the network time information in the network time timer. The transmission frame used here is a frame used for purposes other than time synchronization in the prior art, and is not newly added in the embodiment of the present invention. The time information frame 909 is obtained by attaching network time information 908 to a conventional transmission frame. In the embodiment of the present invention, since a transmission frame that has been used conventionally is used, it is possible to use the control system according to the prior art shown in FIG. 1 and the control system according to the embodiment of the present invention in combination. . Detailed configurations of the frame receiver 9013 and the frame generator 9014 will be described later (step F10).

  FIG. 5 is a diagram for explaining a method of collecting time information when a failure occurs in the control target of the arithmetic device in the control system according to the embodiment of the present invention shown in FIG. FIG. 5 shows the same control system as that shown in FIG. 3 except that main memory information necessary for explaining the collection of time information is added, and unnecessary frame generators and receivers are added. It is omitted. Since the time information collection method is the same in the arithmetic devices A16 to C18, only the arithmetic device A16 will be described here.

  When the middleware 16021 in the processor 1602 of the arithmetic device A16 receives the failure information 1609 of the control target A19 from the control target A19, the system time is read from the system time timer 16031 in the LSI 1603, and the read time information 1607 and the network time timer The network time is read from 16032 and the read time information 1608 is collected and stored in the network time storage area 16011, system time storage area 16012, and failure information storage area 16013 in the main memory 1601 together with the failure information. The information stored at this time is stored as a table in the main memory 1601, and the failure information can be associated with the network time and the system time. The arithmetic devices B17 and 18 also perform the same processing as described above when a failure occurs in the control target. By collecting the time in this way, even when a failure occurs in the controlled objects A19, B20, C21, the failure information can be arranged in time series according to the synchronized network time. In this case, the system time is used only to specify the time when the task is working or the time when the task is working.

  Next, referring back to FIG. 3, the accuracy of time synchronization in the embodiment of the present invention will be described.

  The communication paths 107 to 110 that connect the arithmetic devices 9 to 11 are communication paths that guarantee real-time properties, and can define a relay delay of a frame. In addition, since the frames used as the time information frames 909 and 1006 are frames transmitted from the frame generation unit 9014 at a fixed cycle, the arithmetic devices B10 and C11 that are time slaves synchronize the time at a fixed cycle. Can do. By synchronizing the time with a fixed period, it is possible to reduce the influence of the variation of the OSC that is a clock oscillator included in the independent network time timer of each of the arithmetic devices B10 and C11. The above-mentioned fixed period is a value that can be arbitrarily determined by the user within a certain range. Accordingly, the time synchronization accuracy of the network time timer can be made extremely high and the accuracy can be defined. In addition, since the transmission of the time information frame is performed by broadcast by hardware, the software load on each of the arithmetic devices A9 to C11 can be minimized. Note that the time accuracy of the timer is determined by the accuracy of each OSC and the time accuracy of the broadcast.

  FIG. 6 is a block diagram showing a configuration of a control system and each arithmetic device according to another embodiment of the present invention. In the configuration of the control system and arithmetic unit shown in FIG. 6, the configuration of the system and the configuration of the LSI, processor, and optical transceiver in each arithmetic unit are the same as those in FIG. The change point is that the signal transmitted from the optical transmission / reception unit 2403 of the arithmetic device B24, which is a time slave, to the middleware 24021 serves as a network time read trigger in the example shown in FIG. In addition, since the arithmetic unit B24 and the arithmetic unit C25 have the same configuration, the configuration of the arithmetic unit C25 is not illustrated.

  FIG. 7 is a flowchart for explaining a processing operation for synchronizing the times of a plurality of arithmetic devices constituting a control system according to another embodiment of the present invention, which will be described next.

(1) First, the user uses the POC 22 to transmit time information possessed by the POC 22 to the arithmetic unit A23 via the communication path 120. In the arithmetic device A23, the optical signal transmission / reception unit 2303 receives the time information from the POC 22, and provides it to the middleware 23021 in the processor 2302 of the arithmetic device A23 as the system time information 2308 (step F11).

(2) The middleware 23021 that has obtained the system time information 2308 stores the system time information 2308 obtained from the optical signal transmission / reception unit 2303 in the system time timer 23011 in the LSI 2301 as the system time information 2304. Further, the system time information is stored in the system time timers of the arithmetic devices B10 and C11 by the same procedure as described above (step F12).

  The processing so far is the same as the processing in F1 to F3 in FIG. 2 described as processing in the prior art.

(3) Next, the user designates one of the arithmetic devices from the POC 22 as the time master. Here, the description is continued assuming that the arithmetic device A23 is designated as the time master, but the user can designate any arithmetic device as the time master. The arithmetic devices B10 and C11 not designated as the time master become time slaves (step F13).

(4) The middleware 23021 of the arithmetic unit A23 designated as the time master reads the system time from the system time timer 23011 at a regular cycle (about once every 4 seconds) and collects the system time information 2305, and the time information 2306 is stored in the network time timer 9012. By this processing, the network time timer 9012 takes a value close to the system time timer 9011 (step F14).

(5) Next, the frame generation unit 23014 of the LSI 2301 of the arithmetic device A23 acquires the time of the network time timer 23012 as the network time information 2307, attaches the network time information 2307 to the transmission frame, and generates a time information frame 2309. Then, the frame is broadcast from the optical signal transmitting / receiving unit 2303 to the arithmetic devices B24 and C25 which are time slaves (step F15).

(6) In the arithmetic device B24 which is a time slave, the optical signal transmission / reception unit 2403 receives the time information frame 2309, and the network time information of the received time information frame 2309 is received via the frame reception unit 24013 in the LSI 2401. It is stored as network time information 2406 in 24012, and the network time timer 24012 keeps measuring time. Similarly, the arithmetic device C25 stores the network time information in the network time timer (step F16).

(7) The recommended cycle, which is a cycle that does not affect task processing that causes the task processing to be lost when the system time of calculation transmission that is a time slave is updated using the POC 22 For example, the network time information read trigger 2407 is issued to the arithmetic devices B24 and C25 that are time slaves in about 4 seconds. Although the value of the recommended period described above varies depending on the system configuration, as described above, since the time synchronization accuracy can be defined in the embodiment of the present invention, the user can calculate the recommended period (step) F17).

(8) The network time information read trigger is received by the optical signal transmission / reception unit 2403 of the arithmetic device B24 which is a time slave, and the received network time information read trigger is sent from the optical signal transmission / reception unit 2403 to the middleware 24021 in the processor 2402. It is passed as the network time information read trigger 2407. When the middleware 24021 receives the network time information read trigger 2407, the middleware 24021 acquires the network time from the network time timer 24012 in the LSI 2401 as the read information 2405 of that time, and stores it in the system time timer 24011. In the arithmetic device C25, the same processing as that of the arithmetic device B24 is performed (step F18).

  In the control system according to the second reception of the present invention described with reference to FIG. 6, the system time timers of the arithmetic units A23 to C25 are synchronized. Therefore, when a failure occurs in each control target A26 to C28, When collecting the time information at the time, collecting the system time only from the system time timer of each computing device without collecting the network time read information, the faults that occurred can be arranged in time series. The time information frame 2309 used for time synchronization is the same as the frame used in the control system shown in FIG. 3, and the relay delay is also the same. For this reason, the time synchronization accuracy is the same as that of the control system shown in FIG.

  FIG. 8 is a diagram for explaining a method of collecting time information when a failure occurs in the control target of the arithmetic device in the control system according to another embodiment of the present invention shown in FIG. FIG. 8 shows the same control system as the control system shown in FIG. 6. However, main memory information necessary for explaining the collection of time information is added, and unnecessary frame generators and receivers are added. It is omitted. Since the time information collection method is the same in the arithmetic devices A30 to C32, only the arithmetic device A30 will be described here.

  When the middleware 30021 in the processor 3002 of the arithmetic device A30 receives the fault information 131 of the control target A33 from the control target A33, the middleware 30021 reads the system time from the system time timer 30032 in the LSI 3003, and the read time information 3006 is used as the fault information 131. At the same time, the system time information 3004 and the failure information 3005 are stored in the system time storage area 30011 and the failure information storage area 30012 in the main memory 3001.

  The information stored at this time is stored as a table in the main memory, the failure information can be associated with the system time, and a failure has occurred in the control objects A to C by using the collected system time. Sometimes, the failure information can be arranged in time series.

  FIG. 9 is a block diagram showing the configuration of the frame generation unit in the arithmetic unit, and FIG. 10 is a flowchart for explaining the frame generation processing operation in the arithmetic unit including the frame generation unit. Next, the configuration of the frame generation unit and The processing operation will be described.

  As described above, the arithmetic unit 36 includes a processor 3601, an LSI 3602, and an optical signal transmission / reception unit 3608. A middleware 36011 is provided in the processor 3601, and a system time timer 36021, a network time timer 36022, a network time control register 36023, and a frame generation unit 36024 are provided in the LSI 3602. The network time control register 36023 stores information indicating whether the own arithmetic device is a time master or a time slave. The frame generation unit 36024 includes a time information generation unit 360241 and a CRC calculation unit 360242.

  Next, with reference to the flow shown in FIG. 10, the processing operation of frame generation in the arithmetic device including the frame generation unit will be described.

(1) The middleware 36011 in the arithmetic device 36 serving as the time master reads the system time from the system time timer 36021 in the LSI 3602 to acquire the time information 3603 and stores the acquired time information in the network time timer 36022. (Step F19).

(2) Next, the time information of the network time timer 36022 and the information in the network time control register 36023 are transferred to the time information generation unit 360241 in the frame generation unit 36024, respectively. Shows the time master). The time master bit information described above is information indicating whether the arithmetic device is a time master or a time slave, and time master bit information (master) indicates that the arithmetic device is a time master, The time master bit information (slave) indicates that the arithmetic device is a time slave (step F20).

(3) The time information generation unit 360241 is attached to the network time information 3604 transmission frame and attached to the time information attachment frame 3606 on condition that the information from the network time information control register 36023 is time master bit information (master) 3605. And the generated frame is transmitted to the CRC calculation unit 360242 (step F21).

(4) The CRC calculation unit 360242 calculates a CRC value from the received time information attachment frame 3606, and generates a time information transmission frame 3607 (step F22).

(5) The generated time information frame 3607 is transmitted from the LSI 3602 at regular intervals via the optical signal transmission / reception unit 3608 and the communication path 134 (step F23).

  FIG. 11 is a block diagram showing the configuration of the frame receiving unit in the arithmetic unit, and FIG. 12 is a flowchart for explaining the frame receiving processing operation in the arithmetic unit including the frame receiving unit. Next, the configuration of the frame receiving unit and The processing operation will be described. Note that the frame generation unit is provided in each of all the arithmetic devices, but the frame reception unit receives the frame only in the frame reception unit in the arithmetic device that is the time slave.

  As described above, the arithmetic unit 37 includes a processor 3701, an LSI 3702, and an optical signal transmission / reception unit 3708. A middleware 37011 is provided in the processor 3701), and a system time timer 37021, a network time control register 37022, and a frame receiving unit 37023 are provided in the LSI 3702. The network time control register 37022 stores information indicating whether the own computing device is a time master or a time slave. The frame reception unit 37023 includes a frame analysis unit 370234, a time information reception unit 370231, a CRC analysis unit 370233, and a time information storage analysis unit 370232.

  Next, with reference to the flow shown in FIG. 12, the processing operation of frame reception in the arithmetic device including the frame reception unit will be described.

(1) When the time information frame 3710 received by the optical signal reception unit 3703 is transmitted, the frame analysis unit 370234 transmits the time information 3706 in the frame to the time information reception unit 370231, and the CRC information 3708 in the frame. Is transmitted to the CRC analysis unit 370233, and the time master bit information (master) 3709 in the frame is transmitted to the time information storage analysis unit 370232 (step F23).

(2) The network control register 37022 transmits time master bit information (slave) 3707 to the time storage analysis unit 370232. Then, the time information storage analysis unit 370232 indicates that the CRC information 3708 is normal, the time master bit information in the time information frame 3710 indicates the master, and the time master bit information from the network control register 37022 indicates the slave. Only the strobe signal 3705 is transmitted to the network time timer 37021 (steps F24 and F25).

(3) The time information receiving unit 370231 transmits the network time information 3704 to the network time timer 37021. The network time timer 37021 is transmitted from the time information receiving unit 370231 only when the strobe signal 3705 is received. The network time information 3704 is stored in its own timer (step F26).

  Each process in the above-described embodiment of the present invention is configured by a program and can be executed by a CPU included in the present invention. These programs are stored in a recording medium such as an FD, CDROM, or DVD. It can be provided and can be provided by digital information via a network.

8 POC
9 to 10 arithmetic devices A to C
107-110 Communication path 12-14 Control object A-C
901, 1001 LSI
902, 1002 Processor 903, 1003 Optical signal transmission / reception unit 9011, 1011 System time timer 9012, 10012 Network time timer 9013, 1003 Frame reception unit 9014, 10014 Frame generation unit 9021, 1001 Middleware 3001 Main memory 36023 Network time control register 3702231 Time information Reception unit 370232 Time information storage analysis unit 370233 CRC analysis unit 370234 Frame analysis unit

Claims (5)

In a control system in which a plurality of arithmetic devices are connected to each other through a communication path, and a control target is connected to each of the plurality of arithmetic devices,
Each of the plurality of arithmetic units includes a processor, a system time timer, an independent network time timer dedicated to time synchronization, a frame generation unit, and a frame reception unit. Is designated as the time master, other computing devices are designated as time slaves,
The processor of the arithmetic unit that is the time master acquires the time of the system time timer at a constant cycle, stores the time in the network time timer, and keeps counting time,
The frame generation unit acquires time information of the network time timer, generates a frame including the acquired network time timer time information, and broadcasts the generated frame to the arithmetic device that is the time slave at a constant cycle. And
The frame receiving means of the arithmetic device that is the time slave receives the broadcast-transmitted frame, stores the time information in the frame in the network time timer in the own arithmetic device, and continues the time measurement. Feature control system.   When a failure occurs in the control target connected to the plurality of arithmetic devices, the processor of each arithmetic device stores the fault information of the control target in the main memory, the time information of the system time timer, and the 2. The control system according to claim 1, wherein time information of a network time timer dedicated to time synchronization is stored, and faults occurring in each control object are arranged in time series based on the time information of the network time timer. . The frame receiving means of the arithmetic device that is the time slave receives the broadcast-transmitted frame, stores the time information in the frame in the network time timer, and keeps counting time,
2. The control system according to claim 1, wherein the processor of the arithmetic device that is the time slave stores the time information of the network timer in a system time timer at an arbitrary cycle and continues the time measurement.   When a fault occurs in a control target connected to the plurality of arithmetic units, the processor of each arithmetic unit stores the fault information of the control target in the main memory and the time information of the system time timer. 4. The control system according to claim 3, wherein faults occurring in each control target are arranged in time series based on time information of the system time timer. In the time synchronization method of the plurality of arithmetic devices in a control system configured such that a plurality of arithmetic devices are connected to each other through a communication path and a control target is connected to each of the plurality of arithmetic devices.
Each of the plurality of arithmetic units includes a processor, a system time timer, an independent network time timer dedicated to time synchronization, a frame generation unit, and a frame reception unit. Is designated as the time master, other computing devices are designated as time slaves,
The processor of the arithmetic unit that is the time master acquires the time of the system time timer at a constant cycle, stores the time in the network time timer, and keeps counting time,
The frame generation unit acquires time information of the network time timer, generates a frame including the acquired network time timer time information, and broadcasts the generated frame to the arithmetic device that is the time slave at a constant cycle. And
The frame receiving means of the arithmetic device that is the time slave receives the broadcast-transmitted frame, stores the time information in the frame in the network time timer in the own arithmetic device, and continues the time measurement. A time synchronization method of an arithmetic device characterized by the above.

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