WO2016106908A1

WO2016106908A1 - Method and system for synchronizing clocks in sdh network

Info

Publication number: WO2016106908A1
Application number: PCT/CN2015/071528
Authority: WO
Inventors: 王立文
Original assignee: 北京东土科技股份有限公司
Priority date: 2014-12-31
Filing date: 2015-01-26
Publication date: 2016-07-07
Also published as: CN104579534A; CN104579534B

Abstract

A method and system for synchronizing clocks in an SDH network. In the method, a slave clock device determines, according to a PTP synchronization message transmitted between itself and a primary master clock device and stored time delay between itself and the primary master clock device, a master and slave clock deviation value between itself and the primary master clock device, and performs time tick with the primary master clock device when it is determined that the master and slave clock deviation value is within the range of a set first threshold value, and otherwise performs time tick with other standby master clock devices. Since in the embodiments of the present invention the slave clock device establishes a time tick channel with master clock devices in a plurality of different SDH paths at the same time, during the time tick, it can be determined whether the current time tick process is accurate according to the currently calculated master and slave clock deviation value, so as to determine whether a fault occurs to the time tick channel and the master clock devices, thereby ensuring the accuracy of the time tick.

Description

Clock synchronization method and system in SDH network

This application claims priority to Chinese Patent Application No. 201410857121.8, entitled "A Data Transmission Method and System Based on Distributed FTP", filed on December 31, 2014, the entire contents of which are hereby incorporated by reference. Combined in this application.

Technical field

The present invention relates to the field of industrial Ethernet technologies, and in particular, to a clock synchronization method and system in a Synchronous Digital Hierarchy (SDH) network.

Background technique

Figure 1 is a schematic diagram of the structure of the PTP clock synchronization in the current SDH network. When the primary and secondary clock devices are initially set up, both the master clock device and the slave clock device are connected to the GPS antenna, because both the master clock device and the slave clock device are at this time. It is communicating with the GPS satellite, so the master clock device and the slave clock device are synchronized at this time. At this time, the master clock device continuously sends the synchronization packet to the slave clock device, and receives the synchronization packet from the clock device. After a period of measurement, the link delay of the master clock device to the slave clock device is determined according to the sending and receiving time stamp. The Delay is saved as the inherent link delay of the master clock device to the slave clock device.

When the GPS antenna on the slave clock device is removed, and the synchronization packet sent by the master clock device is received from the clock device, the deviation from the master clock device is determined by comparison with the saved Delay, thereby realizing the timing.

When the SDH link changes, the primary clock device fails, or the clock device itself has a problem. The previously measured Delay will lose its meaning. At this time, the slave clock device cannot determine whether it needs to adjust the clock at this time. As a result, the slave clock device fails.

Although there are multiple master clock devices in the existing PTP network, only one of them is the master clock device at a time, and the other is the standby master clock device. As the standby master clock device, before it is upgraded to the master clock device, The PTP synchronization packet is not sent out. The existence of the standby primary clock device cannot be used to time the slave clock device when the link changes. Therefore, the existing clock timing method in the SDH network has certain drawbacks, and the accurate timing of the slave clock device cannot be guaranteed.

Summary of the invention

In view of the above problems, the present invention has been made in order to provide a clock synchronization method and system in an SDH network that overcomes the above problems or at least partially solves the above problems.

An embodiment of the present invention provides a clock synchronization method in an SDH network, where a clock device establishes a time channel with a master clock device in at least three SDH paths, and the method includes:

The slave clock device determines the master-slave clock offset value offset0 between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved primary master clock device to its own delay Delay0;

Determining whether the master-slave clock offset value offset0 is within a set first threshold range;

When it is within the set first threshold range, the timing is performed according to the master-slave clock offset value saved for the master master clock device;

Otherwise, determining the master-slave clock offset value between the other standby master clock device and itself, and determining that the master-slave clock offset value is within the set first threshold range, according to the master-slave clock saved for the standby master clock device The deviation value is timed.

In order to ensure the accuracy of the clock pairing, the entire mastering process can be detected as the standby master clock when the original master clock device is restored. The method further includes:

Transmitting a PTP synchronization message by the slave clock device and the primary master clock device multiple times;

Determining, according to the multiple PTP synchronization messages, a delay of the primary master clock device and itself;

When the absolute value of the difference of the consecutive preset number of delays is within the set delay threshold range, the corresponding master clock device is updated for its corresponding delay.

In order to effectively improve the link fault and the timeliness of the fault detection of the clock device, the method further includes:

The active primary clock device determines the delay of the slave clock device and itself according to the PTP packet transmitted between the slave clock device and the slave clock device;

Determining whether the difference between the delay and the saved delay between the slave clock device and itself is within a set second threshold range;

When the difference exceeds the set second threshold range, the notification information of the link change is sent to the slave clock device.

In order to ensure the accuracy of the clock pair, the method in the embodiment of the present invention further includes:

The active primary clock device determines the delay between each slave clock device and itself according to the PTP message transmitted multiple times with the slave clock device;

When the difference between consecutive preset number of times delays is within a set third threshold range, the primary master clock device stops transmitting notification information to the slave clock device and updates its corresponding for the slave clock device Delay.

In order to ensure the accuracy of the time alignment, the determining the master-slave clock offset value package between the other standby master clock devices and themselves include:

The slave clock device sequentially determines the master-slave clock offset value between each slave master clock device and itself according to the priority of each master clock device according to the priority of each master clock device determined according to the BMC algorithm.

An embodiment of the present invention provides a clock synchronization system in an SDH network, where the system includes: a slave clock device and a master clock device when the slave clock is paired through different time channels;

The slave clock device is configured to determine a master-slave clock offset value between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved primary master clock device to its own delay Delay0. Offset0; determining whether the master-slave clock offset value offset0 is within a set first threshold range; when it is within the set first threshold range, according to the master-slave clock offset value saved for the master master clock device Performing the counterclockwise; otherwise, determining the master-slave clock offset value between the other standby master clock device and itself, and determining that the master-slave clock bias value is within the set first threshold range, according to the saved for the standby master clock device The master-slave clock bias value is timed;

Each master clock device is configured to perform PTP synchronization packet transmission with the slave clock device.

In order to ensure the accuracy of the clock pairing time, the entire timing process can be detected as the standby master clock when the original master clock device is restored, and the slave clock device is also used for multiple times with the master master clock device. Transmitting a PTP synchronization message; determining, according to the plurality of PTP synchronization messages, a delay each time the primary master clock device and itself are; when the absolute value of the difference of the preset preset number of delays is at a set delay When the threshold is within the range, the corresponding primary clock device is updated for its corresponding delay.

The master clock device is further configured to determine the delay of the slave clock device and itself according to the PTP packet transmitted between the slave clock device and the time delay for detecting the fault of the slave device. Whether the difference between the delay and the saved delay between the slave clock device and itself is within a set second threshold range; when the difference exceeds the set second threshold range, the difference is sent to the slave clock device Notification information for link changes.

In order to ensure the accuracy of the clock pairing, the master clock device is further configured to determine a delay between each slave clock device and itself according to a PTP message transmitted multiple times with the slave clock device; When the difference between the set times delay is within the set third threshold range, the primary master clock device stops transmitting the notification information to the slave clock device and updates its corresponding delay for the slave clock device.

The slave clock device is specifically configured to determine, according to the priority of each master clock device based on the BMC algorithm, the priority of each standby master clock device, and sequentially determine each spare master clock according to the priority of each master clock device. The master-slave clock offset value between the device and itself.

The embodiment of the invention provides a clock synchronization method and system in an SDH network, in which a clock channel is established from a clock device and a master clock device in at least three SDH paths, and the slave clock device is based on the current master. Transmitting a PTP synchronization message between the clock devices, and saving the time delay Delay0 of the primary master clock device to its own, determining Determining whether the master-slave clock offset value offset0 is within a set first threshold range, and when the master-slave clock offset value offset0 is within a set first threshold range, according to Performing a check for the primary master clock device to save, otherwise, determining a master-slave clock offset value between the other slave master clock device and itself, and determining that the master-slave clock offset value is within the set first threshold range, The timing is based on the master-slave clock offset value saved for the alternate master clock device. Since in the embodiment of the present invention, the clock device establishes a time channel simultaneously with the master clock device in the plurality of different SDH paths, and the delay and the master-slave clock of the master clock device to itself are saved for each master clock device. The deviation value, so in the process of the time, it can determine whether the current timing process is accurate according to the currently calculated master-slave clock deviation value, thereby determining whether the time channel and the master clock device are faulty, and when there is a problem in the time alignment It is also possible to use other alternate master clocks in time to ensure the accuracy of the time.

The above description is only an overview of the technical solutions of the present invention, and the above-described and other objects, features and advantages of the present invention can be more clearly understood. Specific embodiments of the invention are set forth below.

DRAWINGS

Various other advantages and benefits will become apparent to those skilled in the art from a The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting. Throughout the drawings, the same reference numerals are used to refer to the same parts. In the drawing:

FIG. 1 is a schematic structural diagram of a PTP clock synchronization in an SDH network;

FIG. 2 is a structural diagram of establishing a time channel of a slave clock device and multiple master clock devices according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a clock synchronization process in an SDH network according to an embodiment of the present invention;

4 is a detailed process of clock synchronization in an SDH network according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a clock synchronization system in an SDH network according to an embodiment of the present invention.

detailed description

In order to effectively ensure the accuracy of the time alignment, the embodiment of the invention provides a clock synchronization method and system in an SDH network.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the embodiments of the present invention have been shown in the drawings, the embodiments Rather, these embodiments are provided so that this disclosure will be more fully understood and the scope of the disclosure will be fully disclosed.

The embodiments of the present invention will be described below with reference to the accompanying drawings.

In the embodiment of the present invention, in order to achieve accurate timing of the slave clock device, the slave clock device establishes a time channel with the master clock device in at least three SDH paths, as shown in FIG. 2, the slave clock device and the plurality of masters. The clock device establishes a structure diagram of the time channel. As shown in FIG. 2, the slave clock device establishes a time channel with three master clock devices that travel different SDH network paths.

At the beginning of the time, the slave clock device and the three master clock devices are connected with a GPS antenna. Since the master clock device and the slave clock device both communicate with the GPS satellite, the master clock device and the slave clock device are Synchronous.

The three master clock devices send PTP synchronization packets to the slave clock device through their corresponding time channels. After a period of time, the slave clock device learns the delay of the link between the master clock devices and the master clock device. The individual delays are saved locally for each master clock device. Specifically, as shown in FIG. 2, a delay Delay0 between the slave clock device and the master master clock device is saved, and the first standby master clock device and the second standby master clock device are respectively saved The delay between Delay1 and Delay2.

In addition, in order to ensure the accuracy of time alignment, in the embodiment of the present invention, the slave clock device determines the master between each master clock device and itself according to the delay of each master clock device recorded for each master clock device and itself. The slave clock offset value offset, where offset=T1-T2-Delay, where T1 is the time at which the master clock device sends a sync message, and T2 is the time at which the slave clock device receives the sync message, and the delay is the master clock device to the slave clock device. Delay. At this time, the master clock device and the slave clock device are connected with a GPS antenna, that is, the master clock device and the slave clock device are synchronized, so the master-slave clock offset value offset is 0 at this time.

In the embodiment of the present invention, the master clock is determined based on the BMC algorithm for the multiple master clock devices in the embodiment of the present invention, because the slave clock device establishes a time channel with the master clock device at the same time. Priority of the device. The master clock device with the highest priority is used as the master clock device. The master clock devices of other priorities are used as the backup master clock device. The priority of each standby master clock device is recorded for subsequent operations. Used for all time.

Correspondingly, in order to facilitate the accuracy of the subsequent timing, and to identify the cause of the error in the timing process, and accurately locate the fault that occurs in the timing process, in the embodiment of the present invention, each master clock device transmits between the slave clock device and the slave clock device. PTP synchronization message, determining the link delay from the clock device to itself, and each master clock device records the determined delay of the slave clock device to itself, for example, for the primary master clock device, determining the slave clock The delay of the device to itself is recorded locally as Delay_sm0. The first standby master clock device determines the delay from the clock to itself. The delay is locally recorded as Delay_sm1, and the corresponding second standby master clock device The delay in locally recording the slave clock device to itself is Delay_sm2.

FIG. 3 is a schematic diagram of a clock synchronization process in an SDH network according to an embodiment of the present invention, where the process includes the following steps:

S301: The slave clock device synchronizes the packet according to the PTP transmitted between the master clock device and the saved master master clock. The delay Delay0 of the device to the slave clock device determines the master-slave clock offset value offset0 between the master master clock device and itself.

Specifically, in the embodiment of the present invention, only one primary clock device is used at a certain time, and other master clock devices that establish a time channel with the slave clock device are standby master clock devices. During the time synchronization process, both the primary master clock device and the standby master clock device perform PTP synchronization packet transmission with the slave clock device.

Because the master-slave clock offset value is offset=T1-T2-Delay, where T1 is the time at which the master clock device sends a sync message, and T2 is the time at which the slave clock device receives the sync message, and the delay is the master clock device to the slave clock device. The delay, so the slave clock device can determine the master-slave clock offset value offset from each master clock device according to the sync synchronization message in the PTP synchronization message transmitted between each master clock device. The master-slave clock deviation between the master master clock device and the slave clock device is offset0, offset0=T1-T2-Delay0.

S302: Determine whether the master-slave clock offset value offset0 is within the set first threshold range. If the determination result is yes, proceed to step S303; otherwise, proceed to step S304.

The slave clock device stores a master-slave clock offset value for the master clock device for each master clock device. As shown in FIG. 2, in the slave clock device, the master-slave clock device has its own master-slave clock offset value, the first slave master clock device has its own master-slave clock offset value, and the second slave master clock device and itself. The master-slave clock bias value. Since the master-slave clock offset value is measured at the time when the master-slave clock device is connected to the GPS antenna, each of the master-slave clock offset values stored in the slave clock device is zero.

S303: Perform timing according to the master-slave clock offset value saved for the master master clock device.

When it is within the set first threshold range, it may be determined that the time channel between the primary master clock device and the slave clock device is normal, and the master master clock device and the slave clock device are also normal, and may also be used according to the master device. When the master clock device performs the pairing, in order to ensure the accuracy of the time alignment, in the embodiment of the present invention, when the master-slave clock offset value is saved for the master master clock device, the master-slave clock offset value is The offset between the primary master clock device and the slave clock device.

S304: Determine a master-slave clock offset value between the other standby master clock device and itself, and determine that the master-slave clock offset value is within a set first threshold range, according to the master slave clock saved for the standby master clock device The deviation value is timed.

In the embodiment of the present invention, the clock device establishes a time channel with the master clock device in at least three SDH paths at the same time. According to the BMC algorithm, the priorities of the three master clock devices are respectively used as the master clock device. An alternate primary clock device and a second alternate primary clock device. When the slave GPS device is connected to the clock device and each master clock device, the delay mask of each master clock device to itself is determined and saved.

During the time-to-time, each master clock device transmits a PTP synchronization message to and from the slave clock device. Therefore, the slave clock device can separately synchronize with the master master clock device according to the saved delay time of each master clock device to itself. Each standby master The clock device determines the master-slave clock offset value offset of the master clock device to itself. For example, as shown in FIG. 2, the master-slave clock device determined from the clock device has a master-slave clock offset value of offset0, and the master-slave clock offset value between the first slave master clock device and the slave clock device is offset1. The master-slave clock offset value between the second standby master clock device and the slave clock device is offset2.

First, determining from the clock device, determining whether the offset0 is within a set first threshold range, and when offset0 is within the set first threshold range, indicating between the primary master clock device and the slave clock device The time channel is normal, the master clock device and the slave clock device are both normal, and can be timed according to the master master clock device. In order to ensure the accuracy of the time according to the master master clock device, the time-dependent deviation between the master master clock device and the master-slave clock is saved.

When the offset 0 exceeds the set first threshold range, it indicates that the time channel between the primary master clock device and the slave clock device is faulty, or the master master clock device is faulty, or the slave clock device is faulty, and is implemented in the present invention. In order to ensure the accuracy of the time alignment, the slave clock device performs time alignment with other standby master clock devices.

Specifically, in the embodiment of the present invention, the priority of each primary clock device is determined according to the BMC algorithm, so the highest priority is selected in the standby primary clock device, as shown in FIG. 2, the first standby primary clock. If the priority of the device is higher than that of the second standby primary clock device, it is determined from the clock device whether it can be timed with the first standby primary clock device. When the slave clock device makes a judgment, according to the saved delay of the standby master clock device to itself, the master-slave clock deviation value between the slave master clock device and itself is determined, and it is determined whether the determined master-slave clock offset value is set. Within the first threshold range, when the master-slave clock offset value is within the set first threshold range, the time is determined according to the master-slave clock offset value saved for the standby master clock device; otherwise, the next step is selected. The standby primary clock device of the priority determines whether the standby primary clock device of the next priority is used for the time synchronization until the standby primary clock device that meets the condition is selected for the time synchronization.

In the above process, according to the priority of each standby master clock device, it is sequentially determined whether the value of the master-slave clock deviation of each of the standby master clock devices and the slave clock device is within a set first threshold range, when a certain standby master When the master/slave clock offset value corresponding to the clock device is within the set first threshold range, the standby master clock device is used for the time alignment. At this time, the time channel corresponding to the master master clock device is faulty, or the master device is used. The master clock device is faulty; when the master-slave clock deviation values of all the master clock devices and the slave clock device exceed the set first threshold range, it is likely that the slave clock has failed, and of course, each pair is not excluded. The time channel has failed, or every master clock device has failed.

Since in the embodiment of the present invention, the clock device establishes a time channel simultaneously with the master clock device in the plurality of different SDH paths, and the delay and the master-slave clock of the master clock device to itself are saved for each master clock device. Deviation value, so in the process of the time, it can be determined according to the current calculated master-slave clock deviation value to determine whether the current timing process is Accurate to determine whether the time channel and the master clock device are faulty, and when other problems occur, the other standby master clocks can be used in time to ensure the accuracy of the time.

In the embodiment of the present invention, in order to implement an accurate pairing of the slave clock device in the SDH network, the slave clock device simultaneously establishes a time channel with the master clock device in at least three SDH paths, and each host is determined by the BMC algorithm. The priority of the clock device. When both the master clock device and the slave clock device are connected to the GPS antenna, the slave clock device transmits a PTP synchronization message to each master clock device, and the slave clock device determines the delay delay of each master clock device and itself, and locally targets Each master clock device saves the delay, determines the master-slave clock offset value between each master clock device and itself according to the determined delay, and saves the master-slave clock offset value for each master clock device. Since the master and slave clock devices are connected to the GPS antenna, the master-slave clock offset value saved for each master clock device is zero. Moreover, each master clock device also determines the delay delay_sm of the slave clock device and itself, and the delay determined by each master clock device is stored locally.

After the master clock device is removed from the GPS connected to the slave clock device, each master clock device sends a sync message to the slave clock device. After receiving the sync message sent by each master clock device, the slave clock device The delay delay saved by the master clock device determines the master-slave clock offset value offset of itself and each master clock device. The PVR synchronization packet transmitted between the secondary clock device and the active primary clock device is synchronized with the primary master clock device. Used to monitor the timing process.

After the slave clock device determines the master-slave clock offset value of each master clock device to itself, it is determined whether the master master clock device to its own master-slave clock offset value offset0 is within the set first threshold range. When the offset0 is within the set first threshold range, it indicates that the time channel between the primary master clock device and the slave clock device is normal, and the master master clock device and the slave clock device are both normal, according to the master owner. The clock device is timed. In order to ensure the accuracy of the time according to the master master clock device, the time-dependent deviation between the master master clock device and the master-slave clock is saved.

When the offset 0 exceeds the set first threshold range, it indicates that the time channel between the primary master clock device and the slave clock device is faulty, or the master master clock device is faulty, or the slave clock device is faulty, and is implemented in the present invention. In order to ensure the accuracy of the time alignment, the slave clock device performs time alignment with other standby master clock devices. Downgrading the primary master clock device to the alternate primary clock device

Specifically, in the embodiment of the present invention, the priority of each primary clock device is determined according to the BMC algorithm, so the highest priority is selected in the standby primary clock device, as shown in FIG. 2, the first standby primary clock. If the priority of the device is higher than that of the second standby primary clock device, it is determined from the clock device whether it can be timed with the first standby primary clock device. When the slave clock device makes a judgment, it determines the backup according to the saved delay of the standby master clock device to itself. Determining the master-slave clock deviation value between the master clock device and itself, determining whether the master-slave clock bias value is within a set first threshold range, and when the master-slave clock bias value is within a set first threshold range, according to The master-slave clock offset value saved by the standby master clock device is matched. Otherwise, the standby master clock device of the next priority is selected to determine whether to use the next-priority standby master clock device for timing, until selection The time is up to the alternate primary clock device that meets the conditions. The standby master clock device is upgraded to the master clock device, and the subsequent slave clock device is timed with the upgraded standby master clock device.

After the primary master clock device is degraded to the standby master clock device, the slave clock device still performs the PTP synchronization packet transmission with the degraded primary master clock device. The method further includes:

That is, the degraded primary master clock device continues to transmit PTP synchronization messages with the slave clock device, and the slave clock device determines the delayed Delay Delay of the primary master clock device to the slave clock device. Delay Delay0' is saved when a constant value does not change, then Delay0' is saved instead of the original Delay0.

FIG. 4 is a detailed process of clock synchronization in an SDH network according to an embodiment of the present invention, where the process includes the following steps:

S401: The slave clock device determines a master-slave clock deviation between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved delay time from the primary master clock device to the slave clock device. The value is offset0.

S402: Determine whether the master-slave clock offset value offset0 is within the set first threshold range. When the determination result is yes, proceed to step S403; otherwise, proceed to step S404.

S403: Perform timing according to the master-slave clock offset value saved for the master master clock device. Then, step S405 is performed.

S404: Downgrade the primary master clock device to an alternate master clock device. Determining the master-slave clock offset value between the other standby master clock device and itself, and determining that the master-slave clock offset value is within the set first threshold range, according to the master-slave clock offset value saved for the standby master clock device Make the right time.

S405: The PTP synchronization packet is transmitted multiple times between the slave clock device and the degraded primary master clock device, and the delay of the primary master clock device and itself is determined according to the multiple PTP synchronization packets. .

S406: Determine whether the absolute value of the difference of the consecutive preset number of times delay is within the set delay threshold range. When the determination result is yes, proceed to step S407; otherwise, proceed to step S405.

S407: The slave clock device updates its corresponding delay for the downgraded primary master clock device.

In the embodiment of the present invention, the slave device continues to perform PTP synchronization packet transmission from the degraded primary master clock device. Transmitting, and after determining that the delay between the degraded main master clock device is kept at a constant value, updating the delay corresponding to the degraded main master clock device, thereby ensuring the main use after degrading When the master clock device is upgraded to the master clock device, the master master clock device can be used for timing.

In the embodiment of the present invention, when a standby primary clock device is upgraded to be the primary clock device, the link corresponding to the primary master clock device after the downgrade is restored during the time when the current primary master clock device is used for the timeout. The fault of the primary master clock device is restored, and the determined master-slave clock offset value of the current active master clock device is within a set first threshold range, and the slave clock device always uses the current When the primary master clock device performs the pairing, the slave clock device upgrades one of the standby master clock devices as the master master clock device and the current master clock device only when it exceeds the set first threshold range. Degraded to the standby primary clock device, which can effectively avoid the clock jitter caused by frequent switching between the primary and backup primary clock devices.

In the embodiment of the present invention, since the delay delay_sm between the slave clock device and itself is stored in each master clock device, in order to timely and effectively monitor the time channel between the slave clock device and the master clock device, the present invention The embodiment also includes:

Determining whether the difference between the delay and the saved slave clock device and its own delay is within a set second threshold range;

When the primary master clock device finds that the delay between the slave clock device and itself is greater than the delay delay_sm between the slave clock device and itself, in order to make the slave clock device know the link in time. Change, the primary master clock device sends a notification of the link change to the slave clock device.

Specifically, the active primary clock device carries the abnormal information in the TLV field in the Announce packet to notify the slave device of the link change. After receiving the Announce message from the clock device, the slave clock device no longer believes that the master master clock device is no longer in accordance with the master master clock device, and demotes the master master master clock device to standby. The master clock device upgrades one of the standby master clock devices to the master clock device according to the priority of the standby master clock device.

In the embodiment of the present invention, the method further includes:

The degraded primary master clock device continues to transmit PTP synchronization messages with the slave clock device to determine the slave clock. The delay between the device and itself delay_sm0, when the delay continues to stabilize at a value of delay_sm, although there is a certain gap with the initial delay_sm0, but its corresponding time channel, or its own has been stabilized, the main after the downgrade The master clock device no longer sends exception information to the slave clock device. Since the slave device no longer receives the abnormal information sent by the master clock device, the slave clock device no longer considers that the master clock device is untrusted, and determines the master clock according to the PTP synchronization message transmitted between the master clock device and the master clock device. The delay between the device and itself, if the delay value continues to stabilize near a value, the previously determined delay is replaced by the stabilized delay.

FIG. 5 is a schematic structural diagram of a clock synchronization system in an SDH network according to an embodiment of the present invention, where the system includes: a slave clock device 51 and a master clock device 52 that passes the different time channels and the slave clock pair ;

The slave clock device 51 is configured to determine a master-slave clock deviation between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved primary master clock device to its own delay Delay0. a value of offset0; determining whether the master-slave clock offset value offset0 is within a set first threshold range; and when it is within a set first threshold range, according to the master-slave clock offset held for the master master clock device The value is timed; otherwise, the master-slave clock offset value between the other standby master clock device and itself is determined, and when the master-slave clock offset value is within the set first threshold range, the save is performed according to the standby master clock device. The master slave clock bias value is timed;

Each master clock device 52 is configured to perform PTP synchronization message transmission with the slave clock device.

In order to ensure the accuracy of the clock pair, the entire time synchronization process can be detected as the standby master clock when the original master clock device is restored, and the slave clock device 51 is also used to be more than the master master clock device. Transmitting a PTP synchronization message; determining, according to the multiple PTP synchronization message, a delay each time the primary master clock device and itself; when the absolute value of the difference of the preset preset number of delays is at a set delay When the threshold is within the threshold, the corresponding primary clock device is updated for its corresponding delay.

The master clock device 52 is further configured to determine a delay of the slave clock device and itself according to the PTP packet transmitted between the slave clock device and the time slot for detecting the fault of the slave device. Determining whether the difference between the delay and the saved delay between the slave clock device and itself is within a set second threshold range; when the difference exceeds the set second threshold range, to the slave clock device Send notification information about link changes.

In order to ensure the accuracy of the clock pairing, the master clock device 52 is further configured to determine a delay between each slave clock device and itself according to a PTP message transmitted multiple times with the slave clock device; When the difference between the preset number of times delay is within the set third threshold range, the primary master clock device stops transmitting the notification information to the slave clock device, and updates the corresponding delay for the slave clock device. .

The slave clock device 51 is specifically configured to determine the priority of each master clock device according to the BMC algorithm according to the priority of each standby master clock device, and sequentially determine each standby master according to the priority of each standby master clock device. The master-slave clock offset value between the clock device and itself.

The embodiment of the invention provides a clock synchronization method and system in an SDH network, in which a clock channel is established from a clock device and a master clock device in at least three SDH paths, and the slave clock device is based on the current master. The PTP synchronization message is transmitted between the clock devices, and the saved main master clock device reaches its own delay Delay0, and the master-slave clock offset value offset0 between the master main clock device and itself is determined to determine the master-slave clock deviation. Whether the value offset0 is within the set first threshold range, when it is within the set first threshold range, according to the time saved for the primary master clock device, otherwise determining the other standby master clock device and itself The master-slave clock offset value between the master and slave clocks is determined according to the master-slave clock offset value saved for the standby master clock device when the master-slave clock offset value is within the set first threshold range. Since in the embodiment of the present invention, the clock device establishes a time channel simultaneously with the master clock device in the plurality of different SDH paths, and the delay and the master-slave clock of the master clock device to itself are saved for each master clock device. The deviation value, so in the process of the time, it can determine whether the current timing process is accurate according to the currently calculated master-slave clock deviation value, thereby determining whether the time channel and the master clock device are faulty, and when there is a problem in the time alignment It is also possible to use other alternate master clocks in time to ensure the accuracy of the time.

The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general purpose systems can also be used with the teaching based on the teachings herein. The structure required to construct such a system is apparent from the above description. Moreover, the invention is not directed to any particular programming language. It is to be understood that the invention may be embodied in a variety of programming language, and the description of the specific language has been described above in order to disclose the preferred embodiments of the invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that the embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of the description.

Similarly, the various features of the invention are sometimes grouped together into a single embodiment, in the above description of the exemplary embodiments of the invention, Figure, or a description of it. However, the method disclosed is not to be interpreted as reflecting the intention that the claimed invention requires more features than those recited in the claims. Rather, as the following claims reflect, inventive aspects reside in less than all features of the single embodiments disclosed herein. Therefore, the claims following the specific embodiments are hereby explicitly incorporated into the embodiments, and each of the claims as a separate embodiment of the invention.

Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of sub-modules or sub-units or sub-components. In addition to such features and/or at least some of the processes or units being mutually exclusive, any combination may be employed All of the features disclosed in this specification, including the accompanying claims, abstract and drawings, and all processes or elements of any method or apparatus so disclosed are combined. Each feature disclosed in this specification (including the accompanying claims, the abstract and the drawings) may be replaced by alternative features that provide the same, equivalent or similar purpose.

In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features that are included in other embodiments and not in other features, combinations of features of different embodiments are intended to be within the scope of the present invention. Different embodiments are formed and formed. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

The various component embodiments of the present invention may be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functionality of some or all of the components of the clock synchronization system in an SDH network in accordance with embodiments of the present invention may be implemented in practice using a microprocessor or digital signal processor (DSP). . The invention can also be implemented as a device or device program (e.g., a computer program and a computer program product) for performing some or all of the methods described herein. Such a program implementing the invention may be stored on a computer readable medium or may be in the form of one or more signals. Such signals may be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

It is to be noted that the above-described embodiments are illustrative of the invention and are not intended to be limiting, and that the invention may be devised without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as a limitation. The word "comprising" does not exclude the presence of the elements or steps that are not recited in the claims. The word "a" or "an" The invention can be implemented by means of hardware comprising several distinct elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by the same hardware item. The use of the words first, second, and third does not indicate any order. These words can be interpreted as names.

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A method for synchronizing a clock in an SDH network, wherein the slave clock device establishes a time channel with the master clock device in the at least three SDH paths, and the method includes:

The slave clock device determines the master-slave clock offset value offset0 between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved primary master clock device to its own delay Delay0;

Determining whether the master-slave clock offset value offset0 is within a set first threshold range;

When it is within the set first threshold range, the timing is performed according to the master-slave clock offset value saved for the master master clock device;

Otherwise, determining the master-slave clock offset value between the other standby master clock device and itself, and determining that the master-slave clock offset value is within the set first threshold range, according to the master-slave clock saved for the standby master clock device The deviation value is timed.
The method of claim 1 wherein the method further comprises:

Transmitting a PTP synchronization message by the slave clock device and the primary master clock device multiple times;

Determining, according to the multiple PTP synchronization messages, a delay of the primary master clock device and itself;

When the absolute value of the difference of the consecutive preset number of delays is within the set delay threshold range, the corresponding master clock device is updated for its corresponding delay.
The method of claim 1 wherein the method further comprises:

The active primary clock device determines the delay of the slave clock device and itself according to the PTP packet transmitted between the slave clock device and the slave clock device;

Determining whether the difference between the delay and the saved slave clock device and its own delay is within a set second threshold range;

When the difference exceeds the set second threshold range, the notification information of the link change is sent to the slave clock device.
The method of claim 3, wherein the method further comprises:

The active primary clock device determines the delay between each slave clock device and itself according to the PTP message transmitted multiple times with the slave clock device;

When the difference between consecutive preset number of times delays is within a set third threshold range, the primary master clock device stops transmitting notification information to the slave clock device and updates its corresponding for the slave clock device Delay.
The method of claim 1 wherein said determining a master-slave clock offset value between the other alternate master clock device and itself comprises:

The slave clock device sequentially determines the master-slave clock offset value between each slave master clock device and itself according to the priority of each master clock device according to the priority of each master clock device determined according to the BMC algorithm.
A clock synchronization system in an SDH network, characterized in that the system comprises: a slave clock device and a master clock device when the slave clock is paired through different time channels;

The slave clock device is configured to determine a master-slave clock offset value between the master master clock device and itself according to the PTP synchronization message transmitted between the primary clock device and the saved primary master clock device to its own delay Delay0. Offset0; determining whether the master-slave clock offset value offset0 is within a set first threshold range; when it is within the set first threshold range, according to the master-slave clock offset value saved for the master master clock device Performing the counterclockwise; otherwise, determining the master-slave clock offset value between the other standby master clock device and itself, and determining that the master-slave clock bias value is within the set first threshold range, according to the saved for the standby master clock device The master-slave clock bias value is timed;

Each master clock device is configured to perform PTP synchronization packet transmission with the slave clock device.
The system according to claim 6, wherein the slave clock device is further configured to transmit a PTP synchronization message to the primary master clock device multiple times; and determine, according to the multiple PTP synchronization message, each The time delay of the primary master clock device and itself; when the absolute value of the difference of the preset preset number of delays is within the set delay threshold range, updating the corresponding delay for the primary master clock device Time.
The system according to claim 6, wherein the master clock device is further configured to determine a delay of the slave clock device and itself according to a PTP message transmitted between the slave clock device; and determine the delay and Whether the difference of the delay between the saved slave clock device and itself is within a set second threshold range; when the difference exceeds the set second threshold range, sending a link change to the slave clock device Notification information.
The system according to claim 8, wherein the master clock device is further configured to determine a delay between each slave clock device and itself according to a PTP message transmitted multiple times with the slave clock device. When the difference between successive preset number of times delays is within a set third threshold range, the primary master clock device stops transmitting notification information to the slave clock device and updates its correspondence with the slave clock device Delay.
The system according to claim 6, wherein the slave clock device is specifically configured to sequentially determine the priority of each master clock device according to the priority of each standby master clock device according to the BMC algorithm. The master-slave clock offset value between each alternate master clock device and itself.