CN101110657B - Method for implementing clock source rearrangement and recovery under condition of single voltage controlled resistor - Google Patents
Method for implementing clock source rearrangement and recovery under condition of single voltage controlled resistor Download PDFInfo
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- CN101110657B CN101110657B CN2006101034015A CN200610103401A CN101110657B CN 101110657 B CN101110657 B CN 101110657B CN 2006101034015 A CN2006101034015 A CN 2006101034015A CN 200610103401 A CN200610103401 A CN 200610103401A CN 101110657 B CN101110657 B CN 101110657B
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Abstract
The present invention discloses a method to realize clock source inversion and restoration under condition of single voltage control crystal oscillator, which includes procedures below: A path of clock source is tracked and judge whether it conforms to conditions of inferior inversion. If eligible, operation continues. It is necessary to invert to a next clock source and then track the clock source to judge whether current clock source complies with conditions of inferior inversion. If eligible, it is proposed to judge a currently optimal clock source. If ineligible, it needs to judge which path of clock source should be restored and ensue a fake detention of a phase locking ring. Phase authentication values are collected for judgment. Once these values exceed a threshold, the clock source can not be restored to the current path of clock. Otherwise, restoration to a corresponding clock source is carried out to jump to a corresponding procedure for continuous operation. The method can effectively realize clock source inversion and restoration of current inferior clock and guarantee accuracy of communication clocks without increasing cost and development period and changing current structures.
Description
Technical field
The present invention relates to a kind of synchronous digital transmission technology (SDH) of the communications field; Particularly; Relate to a kind of under the condition of single VCXO (VCXO); If present clock source deterioration exceeds certain limit, system can auto switching arrive next available clock source, and can return to the method in a clock source under suitable condition.
Background technology
In synchronous digital communications network (SDH/SONET), accomplishing through clock unit synchronously between each network element node in the net.Therefore, network element is in locked in line clock or external clock, and its input will remain in certain scope, and output could keep within the specific limits in the time of locking like this, thereby clock signal could keep certain precision through after the multistage transmission.SDH could reduce the pointer adjustment, prevents the generation of UAS time.
Detection for clock source frequency deviation can have several different methods; Such as design two-way VCXO control system at hardware configuration; Wherein in one the tunnel, detect the lock condition on another road in locking simultaneously, system can switch to the clock signal better quality automatically that on the way.But this technology has increased the cost of existing structure, the transformation of existing structure has also been increased risk, thereby increased the cycle of product development.
Summary of the invention
In order to overcome the problem that exists in the prior art; The present invention is guaranteeing that minimum is changed by system; Minimum and the abundant maintenance of cost is closed under the condition of compatibility of existing system, propose a kind of can auto switching to another clock source, road and can return to the software approach in original clock source in due course.
In order to realize the foregoing invention purpose, the present invention specifically is achieved in that
Under the condition of single VCXO, realize the method that the clock source is switched and recovered, it is characterized in that, comprise the steps:
The first step is followed the tracks of first via clock source, judges whether this clock source, road is satisfied deterioration and switched condition, if, then proceed, if not, then jumped to for the 12 step;
Second step was switched to the second road clock source, and begins to follow the tracks of a set time, jumped to for the 11 step;
The 3rd step, judge whether tracking time arrives, if arrive, then jumped to for the 6th step, otherwise proceed;
In the 4th step, whether the clock source of judging current tracking satisfies deterioration is switched condition, if there is not deterioration, then jumps to for the 11 step, if deterioration, but current tracking is Third Road clock source, then jumps to for the tenth step;
The 5th step was switched to Third Road clock source, and begins to follow the tracks of a set time, jumped to for the 11 step;
In the 6th step, judge whether the present clock source is the optimal clock source, if then jumped to for the tenth step, otherwise proceed;
The 7th step, judge to return to which clock source, make phase-locked loop be in pseudo-hold mode;
The 8th step, gather the phase demodulation value, the phase demodulation value is judged, if surpass thresholding, then think to return to this road clock, jumped to for the tenth step;
The 9th step returned to the corresponding clock source, jumped to corresponding step and worked on;
In the tenth step, empty timer;
The 11 step, wait for the some time sheet, jumped to for the 3rd step;
The 12 step, wait for the some time sheet, jump to the first step.
Said deterioration condition can be:
Frequency deviation is bigger during locking present clock source, and voltage-controlled value surpasses 0xC000 perhaps less than 0x4000;
Surpass 5 minutes and can not lock the present clock source;
Detect the system phase sudden change and surpass ± 2～3ppm.
Said second step:
If the second road clock source does not exist, system never locks first via clock source before, then switches to maintenance pattern or free-run mode.
Said the 5th step:
If Third Road clock source does not exist, system never locks the second road clock source before:
Switch to maintenance pattern or free-run mode.
In said the 8th step, gather the phase demodulation value, the phase demodulation value judged, comprising:
(1) make phase-locked loop be in open loop situations;
(2) report locking present clock source;
(3) following the tracks of can the clock recovered source;
(4) read the phase demodulation value 16 times, the cycle is consistent with the cycle of single VCXO adjustment;
(5) difference of front and back 8 phase demodulation values sum of 16 times relatively judges whether the clock source can recover.
If current tracking is Third Road clock source, can not return to first via clock source through judging, need jump to for the 7th step, judge the possibility in the second road clock source that returns to.
Adopt the method for the invention; Compare with existing clock unit working method, can solve effectively when the method for utilizing software under single VCXO condition realizes when clock source deterioration, the clock source is switched and is recovered; Do not increasing cost; Do not change existing structure, do not increase under the situation of more construction cycle, guaranteed the accuracy of communication system clock.
Description of drawings
Fig. 1 is the schematic flow sheet that clock of the present invention source is switched and recovered.
Embodiment
Below in conjunction with accompanying drawing the method for the invention is implemented to do further to describe in detail.
Clock of the present invention output can remain on ± 4.6PPM in, when the clock source that deterioration takes place return to ± 2-3PPM the time, system can return to this clock source, road, has reached designing requirement.
The first step: follow the tracks of first via clock source, when detecting following arbitrary condition and take place:
1.: frequency deviation is bigger during locking present clock source, and voltage-controlled value surpasses 0xC000 perhaps less than 0x4000;
2.: surpass 5 minutes and can not lock the present clock source;
3.: detect the system phase sudden change and surpass ± 2～3ppm.
Then carried out for second step, otherwise, jumped to for the 12 step.
Second step: system all can be switched to the second road clock source.If the second road clock source does not exist, then switch to maintenance pattern or free-run mode (system never locks first via clock source before).If switch to the maintenance pattern, then system clock output guarantees less than ± 4.6ppm.Timing 10 minutes.Jumped to for the 11 step.
The 3rd step: judge that whether 10 fens clock times have arrived, if arrived, then jump to for the 6th step, otherwise proceed.
The 4th step: judge whether the present clock source deterioration takes place.If there is not deterioration, then jumped to for the 11 step.If deterioration, but current tracking Third Road clock source then jumped to for the tenth step.The deterioration condition is with the condition in the first step.
The 5th step: be switched to Third Road clock source.If Third Road clock source does not exist, then switch to maintenance pattern or free-run mode (system never locks the second road clock source before).If switch to the maintenance pattern, then system clock output guarantees less than ± 4.6ppm.Timing 10 minutes.Jumped to for the 11 step.
The 6th step: judge whether the present clock source is the optimal clock source, if then jumped to for the tenth step, otherwise proceed.
The 7th step: which clock source judgement should return to.Make phase-locked loop be in pseudo-hold mode, promptly voltage-controlled value is output as retention value, but tracking is that the clock source, road that will recover.
The 8th step: carry out following work:
A) phase-locked loop is in open loop situations;
B) report locking present clock source (also might keep or free oscillation);
C) follow the tracks of this clock source, road that to recover;
D) read the phase demodulation value 16 times, the cycle is 10ms (consistent with the cycle of VCXO adjustment);
E) difference of front and back 8 phase demodulation values sum of 16 times relatively.
If surpass certain scope, think that this clock source, road does not have to recover, then jumped to for the tenth step; If but current tracking Third Road clock source; Can not return to first via clock source through judging, need jump to for the 7th step, judge the possibility in the second road clock source that returns to.
The 9th step: return to the corresponding clock source, jump to the first step (if returning to first via clock source) or second step (if returning to the second road clock source).
The tenth step: recover 10 minutes timers.
The 11 step: wait for 100ms, jumped to for the 3rd step.
The 12 step: wait for 100ms, jump to the first step.
Claims (6)
1. under the condition of single VCXO, realize the method that the clock source is switched and recovered, it is characterized in that, comprise the steps:
The first step is followed the tracks of first via clock source, judges whether this clock source, road is satisfied deterioration and switched condition, if, then proceed, if not, then jumped to for the 12 step;
Second step was switched to the second road clock source, and begins to follow the tracks of a set time, jumped to for the 11 step;
The 3rd step, judge whether tracking time arrives, if arrive, then jumped to for the 6th step, otherwise proceed;
In the 4th step, whether the clock source of judging current tracking satisfies deterioration is switched condition, if there is not deterioration, then jumps to for the 11 step, if deterioration, but current tracking is Third Road clock source, then jumps to for the tenth step;
The 5th step was switched to Third Road clock source, and begins to follow the tracks of a set time, jumped to for the 11 step;
In the 6th step, judge whether the present clock source is the optimal clock source, if then jumped to for the tenth step, otherwise proceed;
The 7th step, judge to return to which clock source, make phase-locked loop be in pseudo-hold mode;
The 8th step, gather the phase demodulation value, the phase demodulation value is judged, if surpass thresholding, then think to return to this road clock, jumped to for the tenth step;
The 9th step returned to the corresponding clock source, if return to first via clock source, then jumped to the first step, if return to the second road clock source, then jumped to for second step;
In the tenth step, empty timer;
The 11 step, wait for the some time sheet, jumped to for the 3rd step;
The 12 step, wait for the some time sheet, jump to the first step.
2. the method that realization clock source is switched and recovered under the condition of single VCXO as claimed in claim 1 is characterized in that:
The said deterioration condition of switching can be:
Frequency deviation is bigger during locking present clock source, and voltage-controlled value surpasses 0xC000 perhaps less than 0x4000;
Surpass 5 minutes and can not lock the present clock source;
Detect the system phase sudden change and surpass ± 2～3ppm.
According to claim 1 or claim 2 under the condition of single VCXO, realize the method that the clock source is switched and recovered, it is characterized in that:
Said second step:
If the second road clock source does not exist, system never locks first via clock source before, then switches to maintenance pattern or free-run mode.
According to claim 1 or claim 2 under the condition of single VCXO, realize the method that the clock source is switched and recovered, it is characterized in that:
Said the 5th step:
If Third Road clock source does not exist, system never locks the second road clock source before:
Switch to maintenance pattern or free-run mode.
According to claim 1 or claim 2 under the condition of single VCXO, realize the method that the clock source is switched and recovered, it is characterized in that, in said the 8th step, gather the phase demodulation value, the phase demodulation value is judged, comprising:
(1) make phase-locked loop be in open loop situations;
(2) report locking present clock source;
(3) following the tracks of can the clock recovered source;
(4) read the phase demodulation value 16 times, the cycle is consistent with the cycle of single VCXO adjustment;
(5) difference of front and back 8 phase demodulation values sum of 16 times relatively judges whether the clock source can recover.
6. the method that realization clock source is switched and recovered under the condition of single VCXO as claimed in claim 5 is characterized in that:
If current tracking is Third Road clock source, can not return to first via clock source through judging, need jump to for the 7th step, judge the possibility in the second road clock source that returns to.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101034015A CN101110657B (en) | 2006-07-18 | 2006-07-18 | Method for implementing clock source rearrangement and recovery under condition of single voltage controlled resistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101034015A CN101110657B (en) | 2006-07-18 | 2006-07-18 | Method for implementing clock source rearrangement and recovery under condition of single voltage controlled resistor |
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| Publication Number | Publication Date |
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| CN101110657A CN101110657A (en) | 2008-01-23 |
| CN101110657B true CN101110657B (en) | 2012-07-04 |
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| CN2006101034015A Expired - Fee Related CN101110657B (en) | 2006-07-18 | 2006-07-18 | Method for implementing clock source rearrangement and recovery under condition of single voltage controlled resistor |
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| CN104660359B (en) * | 2013-11-21 | 2019-01-11 | 中兴通讯股份有限公司 | A kind of method, apparatus and equipment of clock frequency deviation detection |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540879A (en) * | 2003-04-26 | 2004-10-27 | 华为技术有限公司 | Fast clock rearranging method and device with no spike |
| CN1700623A (en) * | 2004-05-21 | 2005-11-23 | 华为技术有限公司 | Method for implementing clock management via Q3 interface in synchronous optical network |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540879A (en) * | 2003-04-26 | 2004-10-27 | 华为技术有限公司 | Fast clock rearranging method and device with no spike |
| CN1700623A (en) * | 2004-05-21 | 2005-11-23 | 华为技术有限公司 | Method for implementing clock management via Q3 interface in synchronous optical network |
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