WO2016045311A1

WO2016045311A1 - Device self-checking method, apparatus and storage medium

Info

Publication number: WO2016045311A1
Application number: PCT/CN2015/073247
Authority: WO
Inventors: 曹志刚
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-09-28
Filing date: 2015-02-25
Publication date: 2016-03-31
Also published as: CN105530139B; CN105530139A

Abstract

A device self-checking method is disclosed in the present invention including: obtaining a line delay between a reception port and a transmission port of a physical interface transceiver PHY in a 1588 device; when the absolute value of the difference between the line delay and a standard time is not in a pre-set difference range, determining that the time synchronization performance of the 1588 device is abnormal; when the absolute value of the difference between the line delay and the standard time is in the pre-set difference range, determining that the time synchronization performance of the 1588 device is normal. Meanwhile, a device self-checking apparatus and storage medium are disclosed in the present invention.

Description

Device self-testing method, device and storage medium

Technical field

The present invention relates to device detection technology, and in particular, to a device self-test method, device and storage medium.

Background technique

As the 1588 device is widely used in the time synchronization of the packet transmission network, it is particularly important to detect the 1588 function such as the transceiver channel and synchronization performance of the 1588 device during the generation and deployment of the 1588 device.

The detection of the 1588 function requires the device at both ends to be connected. After the time synchronization interface is configured on the devices at both ends, the device detects the time synchronization of the devices at both ends. The device is faulty or the devices at both ends are abnormal. In this case, you need to check and locate the faults of the devices at both ends. The detection method can only test whether one physical port is normal. All ports of the device are tested.

Summary of the invention

In view of the above, the embodiment of the present invention is to provide a device self-test method, device, and storage medium, which can independently detect 1588 packet sending and receiving performance and 1588 device time synchronization performance of all ports of the 1588 device.

The technical solution of the embodiment of the present invention is implemented as follows:

An embodiment of the present invention provides a device self-test method, which includes: acquiring a line delay between a receiving port and a sending port of a PHY in a 1588 device, where an absolute value of a difference between the line delay and the standard time is not preset. When the difference is within the range, it is determined that the time synchronization performance of the 1588 device is abnormal. When the absolute value of the difference between the line delay and the standard time is within a preset difference range, it is determined that the time synchronization performance of the 1588 device is normal.

In the foregoing implementation, the acquiring the line delay between the receiving port and the sending port of the PHY in the 1588 device includes: recording the timestamp of the packet to be T1, and the time for the PHY to send the packet is T2, and the PHY receives the report. The time of the text is T3, the time when the message is returned is T4, the line delay is the difference between T3 and T2, and the difference between T3 and T2 is T4 minus T1 minus C3; wherein C3 is It also returns the updated time calibration value carried in the text.

In the above implementation, when the message is generated, the time calibration value in the message is cleared.

After the time synchronization performance of the 1588 device is determined, the method further includes: displaying the time synchronization performance of the 1588 device, the transceiver performance of the 1588 device port, and the return delay.

In the above implementation, the determining the time synchronization performance abnormality of the 1588 device includes: determining that the first time synchronization counter and the second time synchronization counter in the 1588 device are out of synchronization, and/or the PHY abnormality, and/or the PHY calculation calibration time. error.

The embodiment of the invention further provides a device self-checking device, the device comprising: an obtaining module, a comparing module and a determining module; wherein

The acquiring module is configured to acquire a line delay between a receiving port and a sending port of the PHY in the 1588 device;

The comparing module is configured to compare the line delay and a preset difference range;

The determining module is configured to determine that the time synchronization performance of the 1588 device is abnormal when the absolute value of the difference between the line delay and the standard time is not within a preset difference range; in the line delay and the standard time When the absolute value of the difference is within the preset difference range, it is determined that the time synchronization performance of the 1588 device is normal.

In the above implementation, the acquiring module is configured to record the timestamp of the packet as T1, the time when the PHY sends the packet is T2, the time when the PHY receives the packet is T3, and the time when the packet is returned is T4. The line delay is the difference between T3 and T2, and the difference between the T3 and the T2 is T4. Subtract T1 and subtract C3; wherein C3 is the updated time calibration value carried in the return text.

In the above implementation, the device further includes: a clearing module configured to clear the time calibration value in the message when the message is generated.

In the above implementation, the device further includes: a display module configured to display time synchronization performance of the 1588 device, transceiver performance of the 1588 device port, and a return delay.

In the foregoing implementation, the determining module is specifically configured to determine that the first time synchronization counter and the second time synchronization counter are not synchronized, and/or the PHY abnormality, and/or the PHY calculation calibration time error in the 1588 device.

The embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the device self-test method of the embodiment of the invention.

The device self-test method, device and storage medium provided by the embodiments of the present invention acquire the line delay between the receiving port and the sending port of the PHY in the 1588 device; the absolute value of the difference between the line delay and the standard time is not When the preset difference range is within the range, it is determined that the time synchronization performance of the 1588 device is abnormal; when the absolute value of the difference between the line delay and the standard time is within a preset difference range, it is determined that the time synchronization performance of the 1588 device is normal. The time when the 1588 device message is generated is T1, the time when the PHY receives the message is T2, the time when the PHY sends the message is T3, the time when the packet is returned is T4, and the calibration time of the packet is correction. The line delay is T3-T2, T3-T2=T4-T1-C3, and the C3 is the updated time calibration value carried in the report. The embodiment of the present invention sends and receives the message through the PHY in the 1588 device. The PHY's transmit port Tx and the receive port Rx can work normally. The time synchronization performance of the 1588 device is determined by comparing the obtained switchback delay with the preset difference range. Thus, all ports of the 1588 device are independently implemented. At the same time, the 1588 packet sending and receiving performance and the time synchronization performance of the 1588 device are detected.

DRAWINGS

1 is a schematic diagram of a processing flow of a device self-test method according to an embodiment of the present invention;

2 is a schematic diagram of a packet processing process of a device 1558 according to an embodiment of the present invention;

3 is a schematic diagram of self-checking of a device according to an embodiment 1588 of the present invention;

4 is a diagram showing a self-test result display interface of the device 1588 according to the embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a device self-test device according to an embodiment of the present invention.

detailed description

In the embodiment of the present invention, the line delay between the receiving port and the sending port of the physical interface transceiver PHY in the device 1588 is obtained; the absolute value of the difference between the line delay and the standard time is not within the preset difference range. The time synchronization performance of the 1588 device is abnormal. When the absolute value of the difference between the line delay and the standard time is within a preset difference range, it is determined that the time synchronization performance of the 1588 device is normal.

In order to better understand the technical solutions of the embodiments of the present invention, the composition of the 1588 device and the functions of the components are described in detail below.

The 1588 device generally includes a centralized processing module and a line transceiver module. The centralized processing module is configured to generate a message, return a message, time stamp the message, select a time source of the 1588 device, calculate a time offset, and synchronize the time. The line transceiver module is configured to process 1588 message time stamps, perform physical layer coding, and send and receive functions; the centralized processing module is provided with a first time counter, and the line transceiver module is provided with a second time counter, the second time The counter needs to be synchronized with the first time counter to ensure that all time stamps of the line transceiver module and the centralized processing module are the same reference.

The processing flow of the device self-test method in the embodiment of the present invention, as shown in FIG. 1 , includes the following steps:

Step 101: Acquire a line delay between a receiving port and a sending port of the physical interface transceiver PHY in the 1588 device.

Specifically, in the embodiment of the present invention, the packet processing flow of the 1558 device is as shown in FIG. 2, The self-checking diagram of the 1588 device is as shown in Figure 3. The centralized processing module generates the packet. The time when the packet is generated is T1. The packet is sent to the line transceiver module through the internal communication channel of the 1588 device. The module internally enters the timestamp processing module to update the correction value in the message to C1=correction-T1; the time that the PHY sends the message through the sending port Tx is T2, and the PHY updates the correction value in the message to C2=correction. -T1+T2; the time at which the PHY receives the message through Rx is T3; the PHY then returns the message to the centralized processing module through the internal communication channel of the 1588 device, and the returned packet carries the T1 and the updated correction. The value is C3; the centralized processing module records the time T4 of the packet return, and updates the correction value in the packet to C3=correction-T1+T2+(T4-T3);

The packet may be a sync packet, and the correction is a calibration time inside the packet, and the delay of the calibration is required. When the centralized processing module generates the packet, the correction value in the packet is cleared. Then, the line delay between the receiving port and the sending port of the PHY is T3-T2=T4-T1-C3, and T3-T2 can also be the return time of the high-speed serial link of the PHY;

Here, the line delay may be a line delay acquired at one time, or may be an average value of multiple line delays.

Step 102: When the absolute value of the difference between the line delay and the standard time is not within the preset difference range, determine that the time synchronization performance of the 1588 device is abnormal;

Here, the standard time is a theoretical time for the message to be transmitted between the receiving port and the sending port of the PHY, and is determined by the PHY; the preset difference range is determined by the 1588 device, and the preset difference range may be Is [1ns, 20ns];

When the line delay is not in the preset difference range, it is determined that the time synchronization performance of the 1588 device is abnormal, and the time synchronization performance abnormality of the 1588 device includes: the first time synchronization counter and the second time synchronization counter in the 1588 device. Out of sync, and/or PHY anomaly, and/or PHY calculation calibration time error;

The first time synchronization counter and the second time synchronization counter in the 1588 device are different. Both step and PHY anomalies can cause inaccuracies in T2 and T3 values.

Step 103: When the line delay is within a preset difference range, determine that the time synchronization performance of the 1588 device is normal.

The embodiment of the present invention further includes: Step 104, displaying time synchronization performance, calibration time, and preset difference range of the 1588 device;

Specifically, the 1588 device self-test result display interface diagram, as shown in FIG. 4, the 1588 device self-test result display interface includes: 1588 device time synchronization performance, 1588 device port transceiver performance, and return delay.

In the packet processing process, the high-speed serial link back test can be performed on each receiving port and the sending port to detect the receiving and transmitting performance of the receiving port and the sending port, and all receiving ports of the 1588 device are detected. When the sending and receiving performance of the sending port is normal, the time synchronization performance of the 1588 device is further detected according to the line delay and the preset difference range.

Before the implementation of the embodiment of the present invention, the method further includes: setting a self-test option of the 1588 device in the network management system, including: performing parameters such as 1588 device self-test, and performing 1588 device self-test time.

In order to implement the above-mentioned device self-test method, the embodiment of the present invention further provides a device self-test device, and the component structure of the device, as shown in FIG. 5, includes: an obtaining module 11, a comparing module 12, and a determining module 13;

The obtaining module 11 is configured to acquire a line delay between a receiving port and a sending port of the PHY in the 1588 device;

The comparing module 12 is configured to compare the line delay and a preset difference range.

The determining module 13 is configured to determine that the time synchronization performance of the 1588 device is abnormal when the line delay is not within a preset difference range; when the line delay is within a preset difference range, determine The time synchronization performance of the 1588 device is normal.

In the above implementation, the acquiring module 11 is specifically configured to record a packet time stamp. The time is T1, the time for the PHY to send the message is T2, the time for the PHY to receive the message is T3, and the time for the packet to return is T4, the line delay is T3-T2, T3-T2=T4-T1-C3 Wherein, the C3 is an updated time calibration value carried in the return text;

The packet may be a sync packet, the correction is a time calibration value of the packet, and T3-T2 may also be a high-speed serial link return time of the PHY.

In the above implementation, the device further includes: a clearing module 14 configured to clear the time calibration value in the message when the message is generated.

In the above implementation, the device further includes: a display module 15 configured to display time synchronization performance, calibration time, and preset difference range of the 1588 device.

In the above implementation, the determining module 13 is specifically configured to determine that the first time synchronization counter and the second time synchronization counter are not synchronized, and/or the PHY abnormality, and/or the PHY calculation calibration time error in the 1588 device;

The first time synchronization counter and the second time synchronization counter in the 1588 device are not synchronized, and the PHY abnormality causes the inaccuracy of the T2 value and the T3 value.

In the above implementation, the line delay may be a line delay acquired at one time, or may be an average value of multiple line delays.

In the above implementation, the standard time is determined by the PHY for the theoretical time that the packet is transmitted between the receiving port and the sending port of the PHY; the preset difference range is determined by the 1588 device, and the preset difference is The range can be [1ns, 20ns].

The obtaining module 11, the comparing module 12, the determining module 13, the clearing module 14, and the display module 15 in the device self-checking device proposed in the embodiment of the present invention may be implemented by a processor, and may also be implemented by a specific logic circuit. The processor may be a mobile terminal or a processor on a server. In practical applications, the processor may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field. Programming gate arrays (FPGAs), etc.

In the embodiment of the present invention, if the device self-test method is implemented in the form of a software function module, And when sold or used as a stand-alone product, it can also be stored on a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the device self-test method of the embodiment of the present invention.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

A device self-test method, the method comprising: acquiring a line delay between a receiving port and a sending port of a physical interface transceiver PHY in a 1588 device;

When the absolute value of the difference between the line delay and the standard time is not within the preset difference range, determining that the time synchronization performance of the 1588 device is abnormal;

When the absolute value of the difference between the line delay and the standard time is within a preset difference range, it is determined that the time synchronization performance of the 1588 device is normal.
The device self-test method according to claim 1, wherein the acquiring the line delay between the receiving port and the sending port of the PHY in the 1588 device comprises:

The time when the packet timestamp is recorded is T1, the time when the PHY sends the message is T2, the time when the PHY receives the message is T3, and the time when the packet is returned is T4, and the line delay is the difference between T3 and T2. The difference between T3 and T2 is T4 minus T1 minus C3; wherein

The C3 is an updated time calibration value carried in the report.
The device self-test method according to claim 2, wherein the time calibration value in the message is cleared when the message is generated.
The device self-test method according to claim 1, wherein after determining the time synchronization performance of the 1588 device, the method further includes:

Displays the time synchronization performance of the 1588 device, the transceiver performance of the 1588 device port, and the return delay.
The device self-test method according to claim 1, wherein the determining the time synchronization performance abnormality of the 1588 device comprises:

It is determined that the first time synchronization counter and the second time synchronization counter within the 1588 device are out of sync, and/or the PHY is abnormal, and/or the PHY calculates a calibration time error.
A device self-checking device, the device comprising: an obtaining module, a comparing module and a determining module; wherein

The acquiring module is configured to acquire a line delay between a receiving port and a sending port of the PHY in the 1588 device;

The comparing module is configured to compare the line delay and a preset difference range;

The determining module is configured to determine that the time synchronization performance of the 1588 device is abnormal when the absolute value of the difference between the line delay and the standard time is not within a preset difference range; in the line delay and the standard time When the absolute value of the difference is within the preset difference range, it is determined that the time synchronization performance of the 1588 device is normal.
The device self-test device according to claim 6, wherein the obtaining module is configured to record a timestamp of the message as T1, a time when the PHY sends the message is T2, and a time when the PHY receives the message is T3, and the report The time returned is T4, the line delay is the difference between T3 and T2, and the difference between T3 and T2 is T4 minus T1 minus C3;

The C3 is an updated time calibration value carried in the report.
The device self-test device according to claim 7, wherein the device further comprises: a clearing module configured to clear the time calibration value in the message when the message is generated.
The device self-test device according to claim 6, wherein the device further comprises: a display module configured to display time synchronization performance of the 1588 device, transceiver performance of the 1588 device port, and return delay.
The device self-test device of claim 6, wherein the determining module is configured to determine that the first time synchronization counter and the second time synchronization counter are out of sync, and/or PHY abnormal, and/or PHY calculations within the 1588 device The calibration time is wrong.
A computer storage medium having stored therein computer executable instructions for performing the device self-test method of any one of claims 1 to 5.