CN107872360B - Method for calculating one-way path delay between clock modules - Google Patents
Method for calculating one-way path delay between clock modules Download PDFInfo
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- CN107872360B CN107872360B CN201610862883.6A CN201610862883A CN107872360B CN 107872360 B CN107872360 B CN 107872360B CN 201610862883 A CN201610862883 A CN 201610862883A CN 107872360 B CN107872360 B CN 107872360B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
- H04L43/0858—One way delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0041—Delay of data signal
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Abstract
The invention aims to provide a method for calculating the one-way path delay between a first clock module and a second clock module. Specifically, in the measurement clock cycle, measuring and recording a second delay value between the transmission of the rising edge time information of the clock pulse signal sent by the clock generator of the first clock module in the measurement clock cycle from the second measurement point to the fourth measurement point; measuring and recording a fourth delay value between the transmission of the rising edge time information from the first measuring point to the fifth measuring point; and calculating the one-way path delay according to the fourth delay value, the second delay value and the respective propagation delay values of the first transmitter, the first receiver, the second transmitter and the second receiver. Compared with the prior art, the invention realizes the measurement and calibration of the one-way path delay in an automatic mode without an additional reverse path in the reverse direction and a PTP mechanism.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a technique for calculating a one-way path delay between a first clock module and a second clock module.
Background
One-way path delay is difficult to measure accurately, two typical examples of which are:
ITU-T g.8013/y.1731 defines ethernet OAM (Operation Administration and Maintenance) tools to measure one-way path delay, but this method is only valid when phase and Time synchronization (by Precision Time Protocol PTP) is obtained between sending MEP (Maintenance Entity Group End Point) and receiving MEP;
ITU-T g.798 defines only a two-way delay measurement method applied to OTN (Optical Transport Network) networks.
One preferred method of measuring the delay of a unidirectional path is shown in figure 1. By using an additional reverse path in the reverse direction, the bi-directional path delay can be measured at the master clock module side. If the forward path and the reverse path have the same length, the one-way path delay is equal to half of the two-way delay. The disadvantages of this method are: 1) an additional reverse path in the reverse direction is required; 2) the asymmetry between the forward path and the reverse path causes the one-way path delay measurement to be inaccurate.
Another presently preferred method is shown in fig. 2. By using the PTP mechanism, the phases and times of the master and slave clock modules are synchronized. The time information is marked at the entry of the master clock module with a time stamp t1 and is communicated to the slave clock module. After the same time information arrives at the entry of the slave clock module, labeled as timestamp t2, the one-way path delay is equal to (t2-t 1). The disadvantage of this method is that a PTP mechanism is required between the master and slave clock modules to ensure phase and time synchronization.
Disclosure of Invention
It is an object of the present invention to provide a method for calculating a one-way path delay between a first clock module and a second clock module.
According to an aspect of the present invention, there is provided a method for calculating a one-way path delay between a first clock module and a second clock module, wherein the first clock module comprises a first transmitter and a first receiver, the second clock module comprises a second transmitter and a second receiver and a phase synchronization unit, wherein the method comprises:
a disabling a second receiver in the second clock module, measuring and recording a second delay value of time information of a clock pulse signal transmitted from a point between the second receiver and the phase synchronization unit to a programmable delay unit of the second clock module;
b, in response to a detected trigger condition, enabling a first receiver in the first clock module, measuring and recording a fourth delay value of a time information of the clock pulse signal transmitted from the first transmitter to the first receiver, wherein the transmission is via the phase synchronization unit and the programmable delay unit; and
and C, calculating the one-way path delay according to the fourth delay value, the second delay value and the respective propagation delay values of the first transmitter, the first receiver, the second transmitter and the second receiver.
Preferably, the present invention provides a method for calculating a one-way path delay between a first clock module and a second clock module, wherein the first clock module comprises a clock generator, a first transmitter connected to the clock generator, a first receiver having an input connected to an output of the first transmitter, a first delay measuring unit, and a first controller, the second clock module comprises a second receiver, a phase synchronization unit connected to the second receiver, a programmable delay unit connected to the phase synchronization unit, a second transmitter connected to the programmable delay unit, a second delay measuring unit, and a second controller, wherein an output of the second transmitter is connected to an input of the second receiver, a first measuring point is provided between the clock generator and the first transmitter, setting a second measurement point between the second receiver and the phase synchronization unit, a fourth measurement point between the programmable delay unit and the second transmitter, and a fifth measurement point at the output of the first receiver, the method comprising the steps of:
a disabling the first transmitter and enabling the second transmitter after the second receiver is disabled during a measurement clock cycle;
b, the second delay measuring unit measures and records the rising edge time information of the clock pulse signal sent by the clock generator of the first clock module in the measuring clock period, and the second delay value is transmitted to the fourth measuring point from the second measuring point sequentially through the phase synchronization unit and the programmable delay unit;
c the first controller detecting whether a first trigger condition to enable the first receiver is satisfied;
d if the first trigger condition is met, the first controller enables the first receiver;
e the first delay measuring unit measures and records a fourth delay value of the rising edge time information transmitted from the first measuring point back to the fifth measuring point via the phase synchronization unit and the programmable delay unit;
f calculating the one-way path delay according to the fourth delay value, the second delay value and the respective propagation delay values of the first sender, the first receiver, the second sender and the second receiver.
Preferably, the present invention may also reestablish the forward path from the first clock module to the second clock module.
Compared with the prior art, one embodiment of the invention achieves the following beneficial effects: the one-way path delay is measured and calibrated in an automatic manner without requiring an additional reverse path in the reverse direction and without using a PTP mechanism, and meanwhile, the measurement is completed within one clock pulse signal period without interrupting the normal transmission of the clock pulse signal.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic diagram illustrating a measurement method for measuring a one-way path delay in the prior art;
FIG. 2 is a schematic diagram of another measurement method for measuring one-way path delay according to the prior art;
FIG. 3 is a schematic diagram of the first and second clock modules according to the present invention;
FIG. 4 is a timing diagram illustrating the calculation of the one-way path delay between the first clock module and the second clock module according to the present invention.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present invention is described in further detail below with reference to the attached drawing figures.
Fig. 3 shows a schematic structural diagram of the first clock module 1 and the second clock module 2 according to the present invention. As shown in fig. 3, the first clock module 1 includes a clock generator 11, a first transmitter 12 connected to the clock generator, a first receiver 13 having an input end connected to an output end of the first transmitter 12, a first delay measuring unit 14, and a first controller 15, the second clock module 2 includes a second receiver 21, a phase synchronizing unit 22 connected to the second receiver 21, a programmable delay unit 23 connected to the phase synchronizing unit 22, a second transmitter 24 connected to the programmable delay unit 23, a second delay measuring unit 25, and a second controller 26, wherein an output end of the second transmitter 24 is connected to an input end of the second receiver 21, a first measuring point (r) is provided between the clock generator 11 and the first transmitter 12, a second measuring point (r) is provided between the second receiver 21 and the phase synchronizing unit 22, a fourth measurement point is arranged between the programmable delay unit 23 and the second transmitter 24, and a fifth measurement point is arranged at the output of the first receiver 13. The first controller 15 and the second controller 26 are coupled via a communication channel (e.g., an in-band communication channel or an out-of-band communication channel).
Preferably, the present invention may further set a measurement point (c) at the output of the phase synchronization unit 22.
Preferably, as shown in fig. 3, the first clock module 1 may further include a pull-down resistor 16 connected to an output terminal of the first receiver 13, and the second clock module 2 may further include a pull-down resistor 27 connected to an output terminal of the second receiver 21.
Here, the first clock module 1 and the second clock module 2 may have the same circuit but present in different modes, for example, in an embodiment, the first clock module 1 may be a master clock module, and the second clock module 2 may be a slave clock module, or, if the first clock module 1 is a slave clock module, the second clock module 2 is a master clock module. The delay of the transmission medium between the first clock module 1 and the second clock module 2 (between a and B as shown in fig. 3) is called one-way path delay. In a specific embodiment, the transmission medium between a and B may be a backplane, a coaxial cable, or a UTP (Unshielded Twisted Pair)/STP (Shielded Twisted Pair) cable. Here, in the present invention, the first clock module 1 is a master clock module, and the second clock module 2 is a slave clock module.
It will be appreciated by those of ordinary skill in the art that the foregoing transmission media are merely exemplary and that other transmission media, existing or later, that may be used with the present invention are also included within the scope of the present invention and are hereby incorporated by reference.
To facilitate a better understanding of the invention, the following description is first made:
1) rising edge time information of the clock pulse signal: for example, in a measurement clock cycle, if the clock generator 11 sends out a clock signal (which is labeled as p1 for convenience of description), the rising edge of the clock signal at the first measurement point (r) is the time information 1 shown in fig. 4, and the time information 1 is sent from the first measurement point (r) to the second clock module 2 and then reaches the fourth measurement point (r) via the phase synchronization unit 22 and the programmable delay unit 23 to become the time information 2, as shown in fig. 4, that is, the rising edge of the clock signal p1 at the fourth measurement point (r) is the time information 2;
2) forward path and reverse path: as shown in fig. 3, time information 1 is transferred from the first clock module 1 to the second clock module 2 via the forward path, i.e.: clock generator 11- > first transmitter 12- > transmission medium from a to B- > second receiver 21- > phase synchronization unit 22. Subsequently, the second clock module 2 sends the time information 2 back to the first clock module 1 via the reverse path, i.e.: phase synchronization unit 22- > programmable delay unit 23- > second transmitter 24- > transmission medium from B to a- > first receiver 13; here, the meaning of point a and point B is explained by taking a forward path as an example, specifically, point a in fig. 3 is an output terminal of the first clock module 1, and point B in fig. 3 is an input terminal of the second clock module 2;
3) for convenience of description, the first transmitter 12, the first receiver 13, the second receiver 21, and the second transmitter 24 are hereinafter referred to as T1, R1, R2, and T2, respectively.
Preferably, the phase synchronization unit 22 may be implemented with a phase-locked loop circuit, which outputs the third measurement point (c) phase-locked to its input second measurement point (c) without delay. The fourth measurement point (r) is delayed by a fixed phase by the programmable delay unit 23 compared to the third measurement point (c). The second delay measurement unit 25 in the second clock module 2 is used to measure and calibrate the delay between the second measurement point (c) and the fourth measurement point (c).
The controllers in the first and second clock modules 1 and 2 are used to enable/disable the T1, R1, T2 and R2 (here, the control manner of the controllers includes, but is not limited to, at least any one of: 1) the device is enabled when the control signal is high, and the device is disabled when the control signal is low; 2) when the control signal is low level, the device is enabled, when the control signal is high level, the device is disabled), the state of the corresponding delay measurement unit is controlled, and the state of the peer controller is exchanged through the communication channel between the first clock module 1 and the second clock module 2. It will be understood by those skilled in the art that the above control schemes are merely exemplary, and other control schemes now known or later developed, such as those applicable to the present invention, are included within the scope of the present invention and are incorporated herein by reference. The control method adopted by the invention is as follows: when the control signal is high, the device is enabled, and when the control signal is low, the device is disabled.
FIG. 4 is a timing diagram illustrating the calculation of the one-way path delay between the first clock module and the second clock module according to the present invention. The following detailed measurement process in one clock signal cycle is illustrated with reference to fig. 3 and fig. 4, and it should be first explained that the overall process of measuring the one-way path delay is smaller than the following clock signal cycle, that is, one-way path delay measurement is performed in one clock signal cycle:
step a: after the R2 is disabled, the T1 is disabled and the T2 is enabled during a measurement clock cycle.
Specifically, in the measurement clock cycle, for the clock pulse signal p1, if the second controller 26 detects that the time information 1 is transmitted to the second measurement point two via the forward path, the second controller 26 disables the R2; after R2 is disabled, the second controller 26 enables T2 after the output of R2 is pulled down completely; the first controller 15 detects whether the second trigger condition for disabling T1 is satisfied.
Preferably, the second trigger condition comprises at least any one of:
the first controller 15 satisfies a second predetermined time threshold at a time after the first measurement point detects time information 1;
the first controller 15 receives the information that R2 sent by the second clock module 2 has been disabled.
For example, in the measurement clock cycle, for the clock pulse signal p1, time information 1 is transmitted to the second measurement point through the forward path, if the second measurement point is reached after the first delay value D1, since the second controller 26 can detect the time information 1 transmitted to the second measurement point, it disables R2 after the second measurement point detects the time information 1 (that is, the time point at which R2 is disabled is after the time information 1 reaches the second measurement point), after R2 is disabled, the output of R2 is pulled down completely, and then the second controller 26 enables T2. Wherein, the propagation delay values of T1 and R2 and the one-way path delay from A to B constitute D1.
If the second clock module 2 sends the information that R2 has been disabled to the first clock module 1, T1 may be disabled when the first controller 15 of the first clock module 1 receives the information; alternatively, the first clock module 1 may estimate the point in time at which R2 is disabled based on T1, the propagation delay value of R2, and the longest transmission medium between the AB, thereby determining the point in time at which T1 is disabled, e.g., the first controller 15 disables T1 if the time after the first controller 15 detects time information 1 (i.e., detects the rising edge) at the first measurement point (R) satisfies a second predetermined time threshold ≧ the propagation delay value of longest one-way path delay value between T1+ AB + R2.
It will be understood by those skilled in the art that the second trigger condition is only exemplary, and other existing or future second trigger conditions, such as those applicable to the present invention, are also included within the scope of the present invention and are hereby incorporated by reference.
Step b: the second delay measurement unit 25 measures and records the rising edge time information of the clock pulse signal sent by the clock generator 11 of the first clock module 1 in the measurement clock cycle, and the second delay value is transmitted from the second measurement point to the fourth measurement point through the phase synchronization unit 22 and the programmable delay unit 23 in sequence.
For example, for the clock pulse signal p1 whose rising edge at the first measurement point (r) is the time information 1 as shown in fig. 4, the second delay measurement unit 25 measures and records the second delay value D2 transmitted from the second measurement point (r) to the fourth measurement point (r) via the phase synchronization unit 22 and the programmable delay unit 23 in sequence after the time information 1 is transmitted to the second clock module 2. As shown in fig. 4, the rising edge of the clock pulse signal at the fourth measurement point (r) is time information 2, and the time information 2 is delayed in phase by D2 compared to the time information 1 and is sent back to the first clock module 1 via the shared reverse path between the first clock module 1 and the second clock module 2. It should be noted here that it is precisely because time information 2 is delayed in phase by D2 that it is injected into the shared reverse path only after it is established, i.e., D2 makes it possible for the establishment of the shared reverse path.
Step c: the first controller 15 detects whether a first trigger condition to enable R1 is satisfied.
Preferably, the first trigger condition comprises at least any one of:
the first controller 15 receives the information sent by the second clock module 2 that the T2 has been enabled;
the first controller 15 satisfies a first predetermined time threshold at a time after the first measurement point detects time information 1.
For example, if the second clock module 2 sends the information that T2 is enabled to the first clock module 1, R1 may be enabled when the first controller 15 of the first clock module 1 receives the information; alternatively, the first clock module 1 may determine the time point at which R1 is enabled based on the estimated time point at which R2 is disabled, the propagation delay value of T2, and the longest transmission medium between the AB, where the first clock module 1 may estimate the time point at which R2 is disabled, as described above, since the time point at which R2 is disabled is after time information 1 reaches the second measurement point (T) i.e., the first clock module 1 may determine the time point at which R2 is disabled based on the propagation delay value of T1 and the longest transmission medium between the AB and the propagation delay value of R2, and the time point at which R1 is enabled is after T2 is turned on and its output signal (logic low) is propagated from the second clock module 2 to the first clock module 1, so that the first controller 15 enables R1 if the first controller 15 satisfies the first predetermined time threshold value after time information 1 is detected at the first measurement point (T), the first predetermined time threshold ≧ (propagation delay value of T1+ longest one-way path delay value between AB + propagation delay value of R2) + propagation delay value of T2+ longest one-way path delay value between BA. And the longest one-way path delay value between the BAs is equal to the longest one-way path delay value between the AB.
It will be understood by those skilled in the art that the first trigger condition is merely exemplary, and other existing or future first trigger conditions may be suitable for the present invention, and are included within the scope of the present invention and are herein incorporated by reference.
Step d: if the first trigger condition is satisfied, the first controller 15 enables R1. To this end, after R1 is enabled, a shared reverse path is formed between the first clock module 1 and the second clock module 2.
Step e: the first delay measurement unit 14 measures and records a fourth delay value between the transmission of the rising edge time information from the first measurement point back to the fifth measurement point via the phase synchronization unit 22 and the programmable delay unit 23.
For example, with respect to the clock pulse signal p1, as shown in fig. 4, the time information 2 reaches the fifth measurement point (p) after the third delay value D3, and after reaching the fifth measurement point (p), the first delay measurement unit 14 measures and records the fourth delay value D4 between the time information 1 of the first measurement point (p) and the time information 2 of the fifth measurement point (p), wherein the propagation delay values of T2 and R1 and the one-way path delay from B to a constitute D3.
Step f: calculating the one-way path delay according to the fourth delay value, the second delay value, and the respective propagation delay values of T1, R1, T2, R2.
Specifically, both the first clock module 1 and the second clock module 2 can calculate the one-way path delay. If the second clock module 2 calculates the one-way path delay, the first clock module 1 first sends the fourth delay value D4 to the second clock module 2, and then the second clock module 2 calculates the one-way path delay to obtain a propagation delay value/2 of [ D4-D2- (T1+ R1+ T2+ R2) ]; if the first clock module 1 calculates the one-way path delay, the second clock module 2 first sends the second delay value D2 to the first clock module 1, and then the first clock module 1 calculates to obtain the one-way path delay as the propagation delay value/2 of [ D4-D2- (T1+ R1+ T2+ R2) ].
It should be noted that the electronic devices have their corresponding propagation delay values, so that the respective propagation delay values of T1, R1, T2 and R2 are determined after the respective devices are determined, and the respective propagation delay values of T1, R1, T2 and R2 can be measured and calibrated, but the specific measurement and calibration method is out of the scope of the present invention. Preferably, the first clock module 1 and the second clock module 2 may exchange values of propagation delays of the respective transmitters and receivers through a communication channel.
Preferably, after step e, the method further comprises step g: the first controller 15 disables R1.
Specifically, after the time information 2 reaches the fifth measurement point (c) after the delay value D3, D4 is measured, and then, R1 is disabled (that is, the time point at which R1 is disabled is after the time information 2 reaches the fifth measurement point (c)), the output thereof is pulled low.
More optionally, after step g, the method further comprises the step m: the first controller 15 enables the T1.
Specifically, after R1 is disabled, T1 is enabled if the first controller 15 is pulled down completely after detecting that R1 is disabled.
Preferably, after R1 is disabled, the method further comprises step n and step p.
Specifically, step n: the second controller 26 detects whether a third trigger condition for disabling the T2 is satisfied. Step p: if the third trigger condition is met, the second controller 26 disables the T2.
Preferably, the third trigger condition comprises at least any one of:
-the second controller 26 satisfies a third predetermined time threshold at a time after the second measurement point detects time information 1;
the second controller 26 receives the information sent by the first clock module 1 that the R1 has been disabled.
For example, after R1 is disabled, the first clock module 1 may send information that R1 has been disabled to the second clock module 2, and disable T2 if the information is received by the second controller 26 of the second clock module 2; alternatively, the second clock module 2 may determine a point in time to disable T2 based on the propagation delay values of D2, T2, the longest transmission medium between BAs, the propagation delay value of R1, and a point in time at the second measurement point of reception of time information 1, and the second controller 26 disables T2 if the second controller 26 satisfies a third predetermined time threshold at the second measurement point of time after detection of time information 1, wherein the third predetermined time threshold is ≧ the propagation delay value of D2+ T2+ the propagation delay value between BAs and the longest one-way path delay value + R1.
It will be understood by those skilled in the art that the third trigger condition is merely exemplary, and that other existing or future third trigger conditions may be suitable for the present invention, and are included within the scope of the present invention and are herein incorporated by reference.
After step m, the method further comprises step q and step r.
Specifically, in step q, the second controller 26 detects whether a fourth trigger condition for enabling the R2 is satisfied; in step R, if the fourth trigger condition is satisfied, the second controller 26 enables the R2 to establish the forward path from the first clock module 1 to the second clock module 2 again.
Preferably, the fourth trigger condition comprises at least any one of:
-the second controller 26 receives the information sent by the first clock module 1 that the T1 has been enabled;
-the second controller 26 satisfies a fourth predetermined time threshold at a time after the second measurement point detects time information 1.
For example, after T1 is enabled, the first clock module 1 sends information that T1 is enabled to the second clock module 2, and if the information is received by the second controller 26 of the second clock module 2, R2 is enabled; alternatively, the second clock module 2 may determine the point in time at which R2 is enabled based on D2, the propagation delay value of T2, the longest transmission medium between BAs, the propagation delay value of R1, the propagation delay value of T1, the longest transmission medium between AB, and the point in time at which time information 1 is received at the second measurement point (c). Here, the R2 is enabled at a time point after the output signal (logic low) of the T1 is enabled and transferred from the first clock module 1 to the second clock module 2. Since the output of R1 is completely pulled down after being disabled, T1 is enabled, and R1 is disabled after time information 2 reaches fifth measurement point (c), and the time point corresponding to time information 2 is time information 1 reaches fourth measurement point (c), and time information 1 reaches fourth measurement point (c) from second measurement point (c), and a delay D2 is required, when time information 1 reaches second measurement point (c), second controller 26 may detect time information 1 (i.e., detect the rising edge), and if second controller 26 detects that the time after time information 1 satisfies the fourth predetermined time threshold, second controller 26 enables R2, wherein the fourth predetermined time threshold ≧ (D2+ T2 propagation delay value + longest one-way path delay value between BA + R1 propagation delay value) + T1 propagation delay value + AB. And the longest one-way path delay value between the BAs is equal to the longest one-way path delay value between the AB.
Here, after R2 is enabled, the forward path is again established from the first clock module 1 to the second clock module 2. Here, it should be noted that the establishment of the forward path is completed before the next cycle starts, so that the normal transmission of the clock pulse signal between the first clock module 1 and the second clock module 2 is not interrupted. Here, the next period includes, but is not limited to: 1) the next measurement clock cycle; 2) the next clock cycle of the clock pulse signal from the clock generator.
It will be understood by those skilled in the art that the fourth trigger condition is merely exemplary, and other existing or future fourth trigger conditions may be applied to the present invention, and are included in the scope of the present invention and are herein incorporated by reference.
It should be noted that the present invention may be implemented in software and/or in a combination of software and hardware, for example, as an Application Specific Integrated Circuit (ASIC), a general purpose computer or any other similar hardware device. In one embodiment, the software program of the present invention may be executed by a processor to implement the steps or functions described above. Also, the software programs (including associated data structures) of the present invention can be stored in a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. Further, some of the steps or functions of the present invention may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.
In addition, some of the present invention can be applied as a computer program product, such as computer program instructions, which when executed by a computer, can invoke or provide the method and/or technical solution according to the present invention through the operation of the computer. Program instructions which invoke the methods of the present invention may be stored on a fixed or removable recording medium and/or transmitted via a data stream on a broadcast or other signal-bearing medium and/or stored within a working memory of a computer device operating in accordance with the program instructions. An embodiment according to the invention herein comprises an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the apparatus to perform a method and/or solution according to embodiments of the invention as described above.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (18)
1. A method for calculating a one-way path delay between a first clock module and a second clock module, wherein the first clock module comprises a first transmitter and a first receiver, and the second clock module comprises a second transmitter and a second receiver and a phase synchronization unit, wherein the method comprises:
a disabling a second receiver in the second clock module, measuring and recording a second delay value at which time information of a clock pulse signal is transmitted from a point between the second receiver and the phase synchronization unit to a point between a programmable delay unit and a second transmitter of the second clock module;
b, in response to a detected first trigger condition for enabling a first receiver, enabling the first receiver in the first clock module, measuring and recording a fourth delay value of a time information of the clock pulse signal transmitted from the first transmitter to the first receiver, wherein the transmission is via the phase synchronization unit and the programmable delay unit; and
c, calculating the one-way path delay according to the fourth delay value, the second delay value and the respective propagation delay values of the first sender, the first receiver, the second sender and the second receiver;
wherein the first clock module further comprises a clock generator, the first transmitter is connectable to the clock generator, and the input of the first receiver is connectable to the output of the first transmitter.
2. The method of claim 1, wherein the first clock module further comprises a clock generator, a first delay measurement unit and a first controller, wherein the first transmitter is coupled to the clock generator, an input of the first receiver is coupled to an output of the first transmitter, the second clock module further comprises a second delay measurement unit and a second controller, wherein the phase synchronization unit is coupled to the second receiver, the programmable delay unit is coupled to the phase synchronization unit, the second transmitter is coupled to the programmable delay unit, an output of the second transmitter is coupled to an input of the second receiver, a first measurement point is provided between the clock generator and the first transmitter, a second measurement point is provided between the second receiver and the phase synchronization unit, setting a fourth measurement point between the programmable delay unit and the second transmitter, and setting a fifth measurement point at an output of the first receiver, wherein the step a includes:
a disabling the first transmitter and enabling the second transmitter after the second receiver is disabled during a measurement clock cycle;
b, the second delay measuring unit measures and records the rising edge time information of the clock pulse signal sent by the clock generator of the first clock module in the measuring clock period, and the rising edge time information is transmitted to a second delay value between the fourth measuring points from the second measuring point through the phase synchronization unit and the programmable delay unit in sequence;
wherein the step B comprises:
c the first controller detecting whether a first trigger condition to enable the first receiver is satisfied;
d if the first trigger condition is met, the first controller enables the first receiver;
e the first delay measurement unit measures and records a fourth delay value between the transmission of the rising edge time information from the first measurement point back to the fifth measurement point via the phase synchronization unit and the programmable delay unit.
3. The method of claim 2, wherein the first trigger condition comprises at least any one of:
-the first controller receives information transmitted by the second clock module that the second transmitter has been enabled;
-the first controller satisfies a first predetermined time threshold at a time after the first measurement point detects the rising edge.
4. A method according to claim 2 or 3, wherein said step a comprises:
-disabling the second receiver if the second controller detects that a rising edge of a clock pulse signal from the clock generator is transmitted to the second measurement point via a forward path between the first clock module and the second clock module during a measurement clock cycle;
-the second controller enables the second transmitter after disabling the second receiver;
-the first controller detecting whether a second trigger condition for disabling the first transmitter is fulfilled.
5. The method of claim 4, wherein the second trigger condition comprises at least any one of:
-the first controller satisfies a second predetermined time threshold at a time after the first measurement point detects the rising edge;
-the first controller receives information from the second clock module that the second receiver has been disabled.
6. The method of claim 1, wherein the phase synchronization unit comprises a phase locked loop circuit.
7. The method of claim 1, wherein the step C comprises:
-said second clock module receiving said fourth delay value sent by said first clock module;
-said second clock module calculating said one-way path delay based on said fourth delay value, said second delay value, and respective propagation delay values of said first transmitter, said first receiver, said second transmitter, and said second receiver.
8. The method of claim 1, wherein the step C comprises:
-the first clock module receives the second delay value sent by the second clock module;
-said first clock module calculating said one-way path delay based on said fourth delay value, said second delay value, and respective propagation delay values of said first transmitter, said first receiver, said second transmitter, and said second receiver.
9. The method of claim 2, wherein after step e, the method further comprises the steps of:
g the first controller disables the first receiver.
10. The method of claim 9, wherein after step g, the method further comprises the steps of:
m the first controller enables the first transmitter.
11. The method of claim 9 or 10, wherein after the first receiver is disabled, the method further comprises the steps of:
n the second controller detecting whether a third trigger condition to disable the second transmitter is satisfied;
p if the third trigger condition is met, the second controller disables the second transmitter.
12. The method of claim 11, wherein the third trigger condition comprises at least any one of:
-the second controller satisfies a third predetermined time threshold at a time after the second measurement point detects the rising edge;
-the second controller receives information sent by the first clock module that the first receiver has been disabled.
13. The method of claim 10, wherein after step m, the method further comprises:
q the second controller detecting whether a fourth trigger condition to enable the second receiver is satisfied;
r if the fourth trigger condition is satisfied, the second controller enables the second receiver to re-establish a forward path from the first clock module to the second clock module.
14. The method of claim 13, wherein the fourth trigger condition comprises at least any one of:
-the second controller receives information sent by the first clock module that the first transmitter has been enabled;
-the second controller satisfies a fourth predetermined time threshold at a time after the second measurement point detects the rising edge.
15. A method according to claim 13 or 14, wherein the re-establishment of the forward path from the first clock module to the second clock module is completed before the start of the next cycle.
16. A first clock module for calculating a one-way path delay between the first clock module and a second clock module, wherein the first clock module is operative to perform the method of any one of claims 8-10.
17. A second clock module for calculating a one-way path delay between a first clock module and the second clock module, wherein the second clock module is operative to perform the method of any one of claims 7 and 11-14.
18. A system for calculating a one-way path delay between a first clock module and a second clock module, wherein the system comprises a first clock module according to claim 16 and a second clock module according to claim 17.
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| CN115022084B (en) * | 2022-07-18 | 2022-11-25 | 深圳市城市交通规划设计研究中心股份有限公司 | Network isolation gatekeeper data exchange method and application thereof |
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