CN114389735A - Clock synchronization method based on IEEE802.1AS redundant master clock - Google Patents
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Abstract
The invention relates to the technical field of industrial time-sensitive network communication, in particular to a clock synchronization method based on an IEEE802.1AS redundant master clock, which comprises the steps that a synchronous centralized control node receives clock source parameter information reported by each time-sensitive in a clock synchronization domain to obtain a redundant clock sequence table and a current optimal master clock; the synchronous centralized control node issues the redundant clock sequence list and the current optimal master clock to other nodes, and the nodes determine the master-slave state of the local clock according to the issued master clock sequence list information; the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to compensate the timestamp; each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and the asymmetry to model and solve a time delay error for time delay measurement, and clock synchronization is completed; the invention reduces the synchronization error accumulated in the time consumed by reselection, improves the reliability of clock synchronization, and reduces the synchronization error caused by factors such as adjacent frequency ratio, asymmetry and the like.
Description
Technical Field
The invention relates to the technical field of industrial time-sensitive network communication, in particular to a clock synchronization method based on an IEEE802.1AS redundant master clock.
Background
The industrial internet is the core of intelligent manufacturing and intelligent factories, connects each link of industrial manufacturing, and aims to improve manufacturing efficiency, optimize production management and promote transformation and upgrade in the field of industrial manufacturing and continuous high-speed development of national economy. The requirement of emerging time sensitive services for deterministic latency for data transmission poses a few challenges to existing ethernet networks. The IEEE802.1 working group provides a time-sensitive network (TSN) protocol, and the TSN is based on a wired ethernet based on IEEE 802.3, and adds and extends a series of functions and protocol standards, thereby improving the capability of the ethernet to support real-time application, and providing a high-rate but best-effort transmission service for non-time-sensitive services while providing a time-delay-bounded and highly reliable data transmission service for the time-sensitive services.
IEEE802.1AS is the premise of TSN technology realization, works in the data link layer of full duplex Ethernet, realizes the clock synchronization of high accuracy through the mode of timestamp transmission. Compared with the traditional NTP and SNTP synchronization protocols, the IEEE802.1AS protocol unifies the clock types, and simultaneously adopts a peer-to-peer delay mechanism, so that the sub-microsecond synchronization precision can be provided.
The precision of the time stamp determines the precision of synchronization, and the high-precision time stamp plays an important role in improving the precision of synchronization in the IEEE802.1AS protocol which takes the time stamp as information transmission and calculation. For example, when a software implementation manner is adopted to call function extraction time count, since the function extraction requires a certain time and the extracted time count has a large deviation from the actual time, the clock synchronization accuracy achieved by software is mostly inferior to that achieved by hardware. Meanwhile, the asymmetry of the link is also one of the main factors influencing the synchronization precision of the IEEE802.1AS protocol. Because the protocol adopts a peer-to-peer delay mechanism, and the actual link is different in data processing delay due to different configurations among nodes, the round-trip link delay among the nodes is often asymmetric, so that a certain delay error is caused and the error is increased along with the deepening of the asymmetry. In addition, ideally, the real-time clock does not change with the time and the influence of the external environment, but actually, the crystal oscillator has the problems of temperature drift, inherent jitter and the like, and the clock source may be unstable, so that errors are generated. For example, a clock oscillator source with a stability of 100ppm could theoretically generate a maximum cumulative error of 12.5 μ s every 125ms of synchronization. Therefore, when the master clock node fails, synchronization errors of the master node and the slave node in a longer time required by the BMCA to select the optimal master clock are accumulated, and the master node and the slave node can even exceed 1us of synchronization errors before the optimal master clock is selected, so that deterministic delay transmission of time-sensitive services is influenced.
In summary, the existing clock synchronization technology lacks a specific reliability scheme for reducing the clock error in the time consumed by re-selecting the failed master clock node, and meanwhile, the protocol lacks practicability on the premise of measuring the path delay on the basis of the symmetric link. Therefore, it is important to improve the synchronization reliability and reduce the error caused by the link asymmetry to improve the synchronization accuracy.
Disclosure of Invention
Based on the problems existing in the existing protocol, the invention provides a clock synchronization method based on an IEEE802.1AS redundant master clock, which specifically comprises the following steps:
a synchronous centralized control node receives clock source parameter information reported by each time sensitivity in a clock synchronization domain to acquire a redundant clock sequence table and a current optimal master clock;
the synchronous centralized control node issues the redundant clock sequence list and the current optimal master clock to other nodes, and the nodes determine the master-slave state of the local clock according to the issued master clock sequence list information;
the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to compensate the timestamp;
and each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and the asymmetry degree to model and solve the delay error for the delay measurement, thereby completing the clock synchronization.
Further, the process of generating the redundant clock sequence list and selecting the current best master clock comprises the following steps:
the synchronous centralized control node receives clock source parameter information reported by each time sensitive node in a clock synchronous domain, wherein the clock source parameter information at least comprises a clock source class, a clock error estimation value and a clock identification number;
and sequentially comparing the clock source data set parameters reported by each node by adopting a data set comparison algorithm, taking the clock of the optimal node as the optimal clock, and generating a redundant clock sequence list by using the clocks of the two suboptimal nodes.
Furthermore, each time-sensitive node in the clock synchronization domain receives the redundant clock list and the optimal master clock information to confirm the clock tree structure, namely when a new node is added, the priority sequence of the node is calculated according to the clock source parameter information reported by the node, the node is added into the clock priority arrangement table of the node according to the sequence, and the table is packaged into the redundant clock sequence list message to be issued and covers the message issued before.
Further, the process of compensating the timestamp by using the timestamp precision compensation mechanism comprises the following steps:
when data passes through the input processing module, respectively recording a receiver timestamp t2 when a request message is received, a receiver timestamp t4 when a response message is received and a receiver timestamp ts when a synchronous message is received according to different message types, and extracting local time in the synchronous module for comparison to obtain an entry delay value; (ii) a
After the data is sent from the synchronization module, when the data processing module is output, according to different message types, a sender timestamp t1 when the request message is sent is extracted, a sender timestamp t3 when the response message is sent and a sender timestamp tm when the synchronization message is sent are compared with local time to obtain an outlet delay value;
the message key information extraction module carries out timestamp compensation according to the calculated entrance delay value and the extracted exit delay value;
and sending the corrected time stamp to a time delay measurement module or a synchronous correction module.
Further, the correcting the transmission time stamp and the reception time stamp includes:
egressTimestamp＝egressMeasuredTimestamp+egressLatency
igressTimestamp＝igressMeasuredTimestamp-igressLatency
wherein, egressTimestamp is the transmission timestamp, igressTimestamp is the receipt timestamp, egressMeasuredTimestamp is the transmission timestamp of synchronization module record, egressLatency is the export delay value, igresMeasuredTimestamp is the receipt timestamp of synchronization module record, igressLatency is the entry delay value.
Further, the modeling and solving of the delay error of the delay measurement by considering the adjacent frequency ratio and the asymmetry degree by each time-sensitive node in the clock synchronization domain comprises:
wherein Delay _ reply is time Delay obtained by solving; f. ofratioIs the frequency ratio of the adjacent nodes; t1 is the timestamp of the sender when sending the transmission delay request message; t2 is the timestamp of the receiver clock when receiving the transmission delay request message; t3 is the timestamp of the sender when sending the response message, and t4 is the timestamp of the receiver clock when receiving the response message; SDR is the degree of symmetry.
Further, in order to obtain more accurate time delay, multiple times of time delay measurement calculation are performed, and an average time delay measurement value obtained through multiple times of calculation is taken as time delay, and then an average time delay measurement value obtained through the kth calculation is expressed as:
Davg,k＝αDavg,k-1+(1-α)Dk-1；
wherein D isk-1Is the k-1 th time delay measurement, Davg,kIs the average delay measurement value obtained by the k-th calculation; alpha is an exponential weighting factor, expressed as
And M is the number of measurements.
Further, the frequency ratio f of the adjacent nodesratioExpressed as:
wherein, t3(k) Time stamp, t, of the sender indicating when the response packet was sent at time k3(k-1) indicating a timestamp of the sender when the response message is sent at the k-1 moment; t is t4(k) Time stamp, t, of receiver clock indicating when response message is received at time k4And (k-1) represents the timestamp of the receiver clock when the response message is received at the time of k-1.
Further, the symmetry SDR is expressed as:
wherein, the Trans _ request represents the time required for transmitting the delay request message, and represents that the Trans _ reply is t4-t3(ii) a Trans _ reply represents the time required for transmitting the delayed response message, and is represented as Trans _ request ═ t2-t1。
According to the invention, by adopting the redundant master clock sequence, each node of the global network can rapidly reselect the optimal master clock according to the redundant master clock sequence when the master clock node fails, so that the synchronization error accumulated in the time consumed by reselection is reduced, and the reliability of clock synchronization is improved; modeling and calculating the path delay measurement value by considering factors such as adjacent frequency ratio, asymmetry and the like so as to reduce the synchronization error caused by the factors; and the clock counting is based on a hardware circuit and a timestamp precision compensation mechanism is adopted to reduce the deviation of the recorded timestamp from the actual time so as to improve the synchronization precision.
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FIG. 1 is an industrial TSN network model in an embodiment of the present invention;
FIG. 2 is a flow chart of the method for synchronizing industrial time-sensitive network clocks based on redundant clocks according to the present invention;
FIG. 3 is a master clock sequence table format in an embodiment of the present invention;
FIG. 4 is a flow chart of the synchronization centralized control node updating the master clock sequence table in the present invention;
FIG. 5 is a schematic diagram of the continuous delayrep messages employed in the present invention;
FIG. 6 is a flow chart of node path delay measurement employed in the present invention;
FIG. 7 is a time stamp error schematic employed in the present invention;
fig. 8 is a schematic diagram of a link delay measurement employed by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is an industrial TSN network model employed by an embodiment of the present invention; the present case considers an industrial TSN network composed of a plurality of terminals and bridges and a synchronous centralized control node as shown in fig. 1. Each node reports clock source parameter information to the synchronous centralized control node to select an optimal main clock node, and the node is used as a root node to generate a clock spanning tree as shown in the figure.
FIG. 2 is a flow chart of a clock synchronization method for an industrial time-sensitive network based on redundant clocks in an embodiment of the present invention, wherein the clock synchronization method of the present invention improves synchronization reliability through a redundant clock sequence table, i.e., a master clock can be reselected according to the sequence of the sequence table if a problem occurs in the master clock; the synchronization error is reduced through a timestamp compensation mechanism and path delay measurement compensation, so that the synchronization precision is improved, the clock synchronization correction value of the IEEE802.1AS protocol is calculated through a timestamp and a path delay measurement value, and the delay measurement error can be reduced by considering the factors, so that the synchronization error is reduced; the method of the invention improves the synchronization precision while ensuring the reliability of clock synchronization, and comprises the following steps:
step 1: and the synchronous centralized control node receives the clock source parameter information reported by each time sensitive node in the clock synchronization domain, and selects a redundant clock sequence and the current optimal master clock through a data set comparison algorithm. And the synchronous centralized control node issues redundant clock sequences and current optimal master clock information for all time-sensitive nodes in the clock synchronization domain by a centralized configuration method. Fig. 3 is a master clock sequence table format generated by the synchronous centralized control node, and as shown in the figure, the table entry is composed of the clock identification number of the node and the sequence of the master clock sequence corresponding to the clock identification number.
Step 2: the node determines the master-slave state of the local clock according to the issued master clock sequence table information, fig. 4 is a flow chart of updating the master clock sequence table by the synchronous centralized control node after the new node is added, as shown in the figure, the new node reports the clock source parameter information of itself to the synchronous centralized control node, the synchronous centralized control node compares the node information with the master clock sequence table entries in sequence, if the node information is better than a certain entry, the corresponding entry is generated by the node clock identification number, and the original entry sequence from the sequence is shifted backward by one bit in sequence in a set. And if all the options are compared and are not inferior to the new node, adding a new entry generated by the node at the tail of the original master clock sequence table entry.
And step 3: the node takes the adjacent frequency ratio and the asymmetry into consideration to model the link delay measurement, thereby reducing the synchronous error brought by the factors, and the specific process comprises the following steps:
when asymmetric traffic is used, the differences in propagation and transmission delays must be known, and since the synchronization process of time sensitive networks involves different node models, dynamic data rates and asymmetric characteristics, it is necessary to propose a model to handle these variables.
1) Degree of symmetry SDR
Wherein Trans _ request and Trans _ reply are respectively the time required for transmitting the delay request message and the response message, including transmission delay and data propagation delay
Trans_reply＝t4-t3
Trans_request＝t2-t1
Wherein, t1 and t2 are the time stamps of the clocks of the sender and the receiver when the transmission delay request message is sent and received, respectively. Similarly, t3 and t4 are time stamps of the sender and receiver clocks when sending and receiving the response message.
TranstimerequestFor requesting message transmission time, TranstimereplyDetermining a time difference delta in response to a message transmission timefixed_timeEqual to the absolute value of the subtraction of the two.
Δfixed_time＝|Transtimerequest-Transtimereply|
In a wired scenario, the propagation time of data is basically fixed, and the asymmetry of a data link is mainly reflected in the difference between the transmission times of messages in nodes.
t4-t3＝(t2-t1)+Δfixed_time
The available SDR ratio:
2) frequency ratio f of adjacent nodesratio:
In actual measurement, the timestamps t1 and t4 use the clock source of the sender node as the counting reference, and the timestamps t2 and t3 use the clock source of the responder as the counting reference, so if the frequencies of the crystal oscillator sources of the two clock sources are different, a certain error is brought to the delay measurement. Thus, it is possible to provideCalculating the frequency ratio f of adjacent time-aware devices in order to obtain accurate synchronized time on the slave clockratioFor compensating the drift time of the local clock.
FIG. 5 is a schematic diagram of a continuous delayrep message, as shown, fratioThe value of (d) may be calculated by the last two subsequent delayrep messages:
wherein, t3(k) And t3(k-1) are the previous timestamps of the receiving node clock and the delayrep message in the sending neighboring time-aware node, respectively. Similarly, t4(k) And t4(k-1) is the current timestamp value of the same delayrep message.
3) Calculate Delay _ reply value
The result of one measurement may have a larger deviation, and in order to calculate a more accurate delay measurement value, multiple calculations need to be performed:
Davg,k＝αDavg,k-1+(1-α)Dk-1
wherein D isk-1Is the k-1 time delay measurement, Davg,kIs the average delay measurement value obtained by the k-th calculation, alpha is an exponential weighting factor, and M is the measurement times.
Fig. 6 is a flow chart of node path delay measurement, and as shown in the figure, after receiving four timestamps, a node first calculates an adjacent frequency ratio and asymmetry, then substitutes the adjacent frequency ratio and asymmetry into an established delay measurement value model to calculate an accurate link delay value, and calculates according to an average calculation method to obtain a link delay measurement value finally adopted.
In this embodiment, t 1-t 4 performs calculation through a timestamp generated in a message interaction process of delay measurement, for example, as shown in fig. 8, a talker sends a path delay request message and records a timestamp t1, a listener receives the request message and records a timestamp t2, then the listener returns a response message containing the timestamp t2 and records a sending time t3, after the response message is sent, the listener packages t3 to a following message and sends the following message to the talker, the talker records a receiving timestamp t4 when receiving the response message containing t2, and a path delay value is calculated through the received or recorded timestamps t1\ t2, t3\ t 4.
And 4, step 4: the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to reduce the error between the recording time and the actual time. Fig. 7 is a schematic diagram of a timestamp error employed in the present invention, and as shown in the figure, there is an error of an output delay or an input delay between a timestamp recording time of data transmission and reception and an actual time, so that the accuracy of a timestamp is reduced and further the synchronization accuracy is reduced. The invention adopts a timestamp precision compensation mechanism as follows:
egressTimestamp＝egressMeasuredTimestamp+egressLatency
igressTimestamp＝igressMeasuredTimestamp-igressLatency
wherein, egressTimestamp is the transmission timestamp, igressTimestamp is the receipt timestamp, egressMeasuredTimestamp is the transmission timestamp of synchronization module record, egressLatency is the export delay value, igresMeasuredTimestamp is the receipt timestamp of synchronization module record, igressLatency is the entry delay value.
The method comprises the following concrete steps:
step 1: the data is recorded and received time stamp and packaged into the header when being input into the processing module, and the header time stamp and the local time are extracted from the synchronization module to calculate and obtain an entry delay value.
Step 2: after the data is sent from the synchronous message module, when the data processing module is output, the sending timestamp and the local timestamp carried by the message are extracted, the exit delay value is obtained through calculation and is encapsulated into the reserved data message.
And step 3: and the message key information extraction module corrects the obtained timestamp according to the formula according to the calculated entrance delay value and the extracted exit delay value, and sends the corrected timestamp to the delay measurement module or the synchronous correction module for calculating the delay measurement value and the clock offset.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. A clock synchronization method based on IEEE802.1AS redundant master clock is characterized by comprising the following steps:
the synchronous centralized control node receives clock source parameter information reported by each time sensitivity in a clock synchronization domain to obtain a redundant clock sequence table and a current optimal master clock;
the synchronous centralized control node issues the redundant clock sequence list and the current optimal master clock to other nodes, and the nodes determine the master-slave state of the local clock according to the issued master clock sequence list information;
the node adopts a hardware timestamp as clock counting, and simultaneously adopts a timestamp precision compensation mechanism to compensate the timestamp;
and each time-sensitive node in the clock synchronization domain considers the adjacent frequency ratio and the asymmetry degree to model and solve the delay error for the delay measurement, thereby completing the clock synchronization.
2. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the process of generating the redundant clock sequence list and selecting the current best master clock comprises:
the synchronous centralized control node receives clock source parameter information reported by each time sensitive node in a clock synchronous domain, wherein the clock source parameter information at least comprises a clock source class, a clock error estimation value and a clock identification number;
and sequentially comparing the clock source data set parameters reported by each node by adopting a data set comparison algorithm, taking the clock of the optimal node as the optimal clock, and generating a redundant clock sequence list by using the clocks of the two suboptimal nodes.
3. The clock synchronization method according to claim 2, wherein each time-sensitive node in the clock synchronization domain receives the redundant clock list and the best master clock information to confirm the clock tree structure, that is, when a new node is added, the priority ranking of the node is calculated according to the clock source parameter information reported by the node, and the node is added to the clock priority ranking list of the node according to the ranking, and the list is encapsulated into the redundant clock sequence list message to be issued and covers the previously issued message.
4. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the process of compensating the timestamp by using the timestamp accuracy compensation mechanism comprises the following steps:
when data passes through the input processing module, respectively recording a receiver timestamp t2 when a request message is received, a receiver timestamp t4 when a response message is received and a receiver timestamp ts when a synchronous message is received according to different message types, and extracting local time in the synchronous module for comparison to obtain an entry delay value; (ii) a
After the data is sent from the synchronization module, when the data processing module is output, according to different message types, a sender timestamp t1 when the request message is sent is extracted, a sender timestamp t3 when the response message is sent and a sender timestamp tm when the synchronization message is sent are compared with local time to obtain an outlet delay value;
the message key information extraction module carries out timestamp compensation according to the calculated entry delay value and the extracted exit delay value;
and sending the corrected time stamp to a time delay measurement module or a synchronous correction module.
5. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the correcting the transmission time stamp and the reception time stamp comprises:
egressTimestamp＝egressMeasuredTimestamp+egressLatency
igressTimestamp＝igressMeasuredTimestamp-igressLatency
wherein, egressTimestamp is the transmission timestamp, igressTimestamp is the receipt timestamp, egressMeasuredTimestamp is the transmission timestamp of synchronization module record, egressLatency is the exit delay value, igresMeasuredTimestamp is the receipt timestamp of synchronization module record, igressLatency is the entry delay value.
6. The clock synchronization method based on the IEEE802.1AS redundant master clock as claimed in claim 1, wherein the step of solving the delay error for the delay measurement modeling by each time-sensitive node in the clock synchronization domain considering the adjacent frequency ratio and the asymmetry degree comprises:
wherein Delay _ reply is time Delay obtained by solving; f. ofratioIs the frequency ratio of the adjacent nodes; t1 is the timestamp of the sender when sending the transmission delay request message; t2 is the timestamp of the receiver clock when receiving the transmission delay request message; t3 is the timestamp of the sender when sending the response message, and t4 is the timestamp of the receiver clock when receiving the response message; SDR is the degree of symmetry.
7. The clock synchronization method according to claim 1, wherein to obtain more accurate delay, a plurality of delay measurement calculations are performed, and the average delay measurement value calculated a plurality of times is taken as the delay, and then the average delay measurement value calculated at the kth time is expressed as:
Davg,k＝αDavg,k-1+(1-α)Dk-1；
wherein D isk-1Is the k-1 th time delay measurement, Davg,kIs the average delay measurement value obtained by the k-th calculation; alpha is an exponential weighting factor, expressed as
M is the number of measurements.
8. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the frequency ratio f of neighboring nodes isratioExpressed as:
wherein, t3(k) Time stamp, t, of the sender indicating when the response packet was sent at time k3(k-1) indicating the timestamp of the sender when the response message is sent at the k-1 moment; t is t4(k) Time stamp, t, of the receiver clock indicating when the response message was received at time k4And (k-1) represents the timestamp of the receiver clock when the response message is received at the time of k-1.
9. The clock synchronization method based on IEEE802.1AS redundant master clock as claimed in claim 1, wherein the symmetry SDR is expressed as:
wherein, the Trans _ request represents the time required for transmitting the delay request message, and represents that the Trans _ reply is t4-t3(ii) a Trans _ reply represents the time required for transmitting the delayed response message, and is represented as Trans _ request ═ t2-t1。
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