CN107528654B - 1588-based time synchronization method and device - Google Patents
1588-based time synchronization method and device Download PDFInfo
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- CN107528654B CN107528654B CN201610448854.5A CN201610448854A CN107528654B CN 107528654 B CN107528654 B CN 107528654B CN 201610448854 A CN201610448854 A CN 201610448854A CN 107528654 B CN107528654 B CN 107528654B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/067—Details of the timestamp structure
Abstract
The invention discloses a 1588-based time synchronization method and a system, which relate to the field of communication, and the method comprises the following steps: detecting and processing the phase difference between a system clock and a line clock to obtain the phase difference between the system clock and the line clock; under a line clock, determining the time difference between a rising edge corresponding to a message header mark of a 1588 message and a rising edge of the current period of the line clock; generating a timestamp related to the 1588 message under a system clock; and compensating the generated time stamp by using the phase difference and the time difference to make the time stamp consistent with a line clock. By compensating the timestamp related to the 1588 message, the compensated timestamp is consistent with the line clock, and the purpose of high-precision time synchronization is achieved.
Description
Technical Field
The invention relates to the field of communication, in particular to a 1588-based time synchronization method and device.
Background
With the continuous development of communication technology, higher requirements are put forward on time synchronization performance, for example, recently, people put forward a requirement for providing a positioning service by using a base station, the time precision requirement is about ± 200ns, and the relative time precision between adjacent base stations is required to be about ± 500ns in the Coordinated Multipoint Joint Processing (CoMP-JP) of the key technology of the Long Term Evolution-Advanced (Long Term Evolution-Advanced, LTE-Advanced) upgrade version; future fifth Generation mobile communication Technology (5G) systems may require ultra-high precision time synchronization requirements on The order of hundreds of ns; for another example, a quantum communication technology in a longer period needs a time measurement technology with extremely high precision to reduce the bit error rate of a quantum communication system and improve the bit rate of the quantum communication system, and may need time synchronization precision within hundred ns.
At present, high-precision time synchronization realized based on a 1588v2 technology can only meet us-magnitude time synchronization requirements, but cannot meet the hundreds of ns or even higher-precision time synchronization requirements.
Disclosure of Invention
The technical problem solved by the technical scheme provided by the embodiment of the invention is to overcome the problems and defects of low synchronization precision in the prior synchronization technology.
The time synchronization method based on 1588 provided by the embodiment of the invention comprises the following steps:
obtaining a phase difference between a system clock and a line clock according to the system clock and the line clock;
under a line clock, determining the time difference between a rising edge corresponding to a message header mark of a 1588 message and a rising edge of the current period of the line clock;
generating a timestamp related to the 1588 message under a system clock;
and compensating the generated time stamp by using the phase difference and the time difference to make the time stamp consistent with a line clock.
Preferably, before the step of determining, under the line clock, a time difference between a rising edge corresponding to a message header flag of the 1588 message and a rising edge of a current cycle of the line clock, the method further includes:
and generating a message header mark of the 1588 message under a line clock, and sending the generated message header mark to a system clock domain.
Preferably, the step of determining, under the line clock, a time difference between a rising edge corresponding to a packet header flag of the 1588 packet and a rising edge of the current cycle of the line clock includes:
detecting a rising edge corresponding to the message header mark and a rising edge of the current period of the line clock under the line clock;
and determining the time difference between the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock according to the detected rising edge corresponding to the message header mark and the rising edge of the current period of the line clock.
Preferably, the step of generating, under a system clock, a timestamp associated with the 1588 message includes:
and under a system clock, receiving the message header marker, and performing timestamp sampling on the received message header marker to obtain a timestamp related to the 1588 message.
Preferably, the step of compensating the generated time stamp to be consistent with the line clock by using the phase difference and the time difference comprises:
comparing the phase difference to the time difference;
if the phase difference is larger than the time difference, subtracting the phase difference from the timestamp to obtain a compensated timestamp;
otherwise, subtracting the phase difference and the system clock period from the timestamp to obtain a compensated timestamp.
According to an embodiment of the present invention, there is provided a storage medium storing a program for implementing the 1588-based time synchronization method described above.
According to an embodiment of the present invention, a 1588-based time synchronization apparatus includes:
and the phase difference detection module is used for obtaining the phase difference between the system clock and the line clock according to the system clock and the line clock.
The rising edge detection module is used for determining the time difference between the rising edge corresponding to the message head mark of the 1588 message and the rising edge of the current period of the line clock under the line clock;
the timestamp sampling module is used for generating a timestamp related to the 1588 message under a system clock;
and the time stamp compensation module is used for compensating the generated time stamp by using the phase difference and the time difference so as to enable the time stamp to be consistent with the line clock.
Preferably, the method further comprises the following steps:
and the PMA/PCS module is used for generating a message head mark of the 1588 message under a line clock and sending the generated message head mark to a system clock domain.
Preferably, the rising edge detecting module detects a rising edge corresponding to the packet header flag and a rising edge of the current cycle of the line clock under the line clock, and determines a time difference between the rising edge corresponding to the packet header flag and the rising edge of the current cycle of the line clock according to the detected rising edge corresponding to the packet header flag and the rising edge of the current cycle of the line clock.
Preferably, the timestamp sampling module is configured to receive the packet header flag in a system clock, and perform timestamp sampling on the received packet header flag to obtain a timestamp associated with the 1588 packet.
Preferably, the timestamp compensation module compares the phase difference with the time difference, and subtracts the timestamp from the phase difference to obtain a compensated timestamp if the phase difference is greater than the time difference, or subtracts the timestamp from the phase difference and a system clock cycle to obtain the compensated timestamp if the phase difference is not greater than the time difference.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the time stamp related to the 1588 message is compensated by utilizing the phase difference between the system clock and the line clock, so that the compensated time stamp is consistent with the line clock, and the aim of high-precision time synchronization is fulfilled.
Drawings
Fig. 1 is a block diagram of a 1588-based time synchronization method according to a first embodiment of the present invention;
fig. 2 is a block diagram of a 1588-based time synchronizer provided in a second embodiment of the present invention;
fig. 3 is a block diagram of a 1588-based time synchronizer according to a third embodiment of the present invention;
fig. 4 is a timing diagram of sof provided by the fourth embodiment of the present invention between the line clock and the system clock;
FIG. 5 is a timing diagram of the sof provided by the fourth embodiment of the invention after the system clock;
fig. 6 is a block diagram of an apparatus applied to a GE electrical port according to a fourth embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be understood that the preferred embodiments described below are only for the purpose of illustrating and explaining the present invention, and are not to be construed as limiting the present invention.
Fig. 1 is a block diagram of a 1588-based time synchronization method according to a first embodiment of the present invention, and as shown in fig. 1, the steps include:
step S101: and obtaining the phase difference between the system clock and the line clock according to the system clock and the line clock.
Specifically, the phase difference between the system clock and the line clock is obtained by detecting the phase difference between the system clock and the line clock.
Step S102: and under the line clock, determining the time difference between the rising edge corresponding to the message head mark of the 1588 message and the rising edge of the current period of the line clock.
And before the time difference is determined, generating a message header mark of the 1588 message under a line clock, and sending the generated message header mark to a system clock domain. Then, under a line clock, detecting a rising edge corresponding to the message header mark and a rising edge of a current period of the line clock, and determining a time difference between the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock according to the detected rising edge corresponding to the message header mark and the rising edge of the current period of the line clock. That is, under the line clock, a header flag is generated, and the time difference between the rising edge of the header flag and the rising edge of the current period of the line clock is detected or measured, so that the compensation value is determined using the obtained time difference.
Step S103: and generating a timestamp related to the 1588 message under a system clock.
Under the system clock domain, receiving the message header mark, and performing timestamp sampling on the received message header mark to obtain a timestamp related to the 1588 message, namely under the system clock domain, after receiving the message header mark, the time corresponding to the first rising edge of the system clock.
Step S104: the generated time stamp is compensated to be consistent with the line clock by using the phase difference and the time difference.
Specifically, comparing the phase difference with the time difference, and if the phase difference is greater than the time difference, subtracting the phase difference from the time stamp to obtain a compensated time stamp; otherwise, subtracting the phase difference and the system clock period from the timestamp to obtain the compensated timestamp.
And for the message sending direction, adding the obtained compensated timestamp into the 1588 message to serve as the sending time of the 1588 message.
And for the message receiving direction, storing the obtained compensated timestamp as the receiving time of the received 1588 message.
It will be understood by those skilled in the art that all or part of the steps in the method according to the above embodiments may be implemented by a program, which may be stored in a computer-readable storage medium, and includes steps S101 to S104 when the program is executed. The storage medium may be ROM/RAM, magnetic disk, optical disk, etc.
Fig. 2 is a block diagram of a 1588-based time synchronizer according to a second embodiment of the present invention, as shown in fig. 2, including:
and the phase difference detection module is used for obtaining the phase difference between the system clock and the line clock according to the system clock and the line clock.
And the rising edge detection module determines the time difference between the rising edge corresponding to the message head mark of the 1588 message and the rising edge of the current period of the line clock under the line clock.
And the timestamp sampling module is used for generating a timestamp related to the 1588 message under a system clock.
And the time stamp compensation module is used for compensating the generated time stamp by using the phase difference and the time difference so as to enable the time stamp to be consistent with the line clock.
Further comprising:
and the PMA/PCS module is used for generating a message head mark of the 1588 message under the line clock and sending the generated message head mark to a system clock domain.
The working principle of the device is as follows:
the message receiving direction is as follows: the PMA/PCS module receives signals from a line interface and carries out corresponding processing to obtain a received message, generates a message header mark of the received message and sends the message header mark to the timestamp sampling module and the rising edge detection module. The rising edge detection module determines the time difference between the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock by detecting the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock under the line clock, and sends the time difference to the timestamp compensation module. The timestamp sampling module receives the message header marker, performs timestamp sampling on the received message header marker at the system time to obtain a timestamp related to the 1588 message, and sends the timestamp to the timestamp compensation module, wherein the timestamp is the rising edge time corresponding to the next cycle rising edge of the system clock after the message header marker is received. And the timestamp compensation module compares the phase difference with the time difference, if the phase difference is greater than the time difference, the timestamp and the phase difference are subtracted to obtain a compensated timestamp, otherwise, the timestamp, the phase difference and the system clock period are subtracted to obtain the compensated timestamp. And finally, saving the compensated time stamp as the receiving time of the received message. The received message is a received 1588 message.
In the message sending direction, when the PMA/PCS module receives a sent message, a message header mark of the sent message is generated and sent to the timestamp sampling module and the rising edge detection module. The rising edge detection module determines the time difference between the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock by detecting the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock under the line clock, and sends the time difference to the timestamp compensation module. The timestamp sampling module receives the message header marker, performs timestamp sampling on the received message header marker at the system time to obtain a timestamp related to the 1588 message, and sends the timestamp to the timestamp compensation module, wherein the timestamp is the rising edge time corresponding to the next cycle rising edge of the system clock after the message header marker is received. And the timestamp compensation module compares the phase difference with the time difference, if the phase difference is greater than the time difference, the timestamp and the phase difference are subtracted to obtain a compensated timestamp, otherwise, the timestamp, the phase difference and the system clock period are subtracted to obtain the compensated timestamp. And finally, adding the compensated timestamp into the sending message as the sending time of the sending message. The sending message is a sent 1588 message.
The 1588-based time synchronization device provided by the invention is high in precision and can achieve synchronization of ns level and even ps level.
Fig. 3 is a block diagram of a 1588-based time synchronizer according to a third embodiment of the present invention, and as shown in fig. 3, the time synchronizer includes a 1588 packet transceiver module, a 1588 packet parsing and timestamp processing module, an interface conversion module, a PMA/PCS module, a timestamp sampling module, a clock circuit, a phase difference detection module of a line clock and a system clock, a rising edge detection module, a comparison module, and a timestamp compensation module. The present embodiment divides the timestamp compensation module of the embodiment of fig. 2 into two parts, one part is a comparison module for comparing a phase difference and a time difference, and the other part is a timestamp compensation module for compensating a timestamp.
The 1588 packet receiving and transmitting module is responsible for sending and receiving 1588 messages; after the 1588 message is analyzed by the 1588 message analyzing and timestamp processing module, a timestamp is added to the message sent by the 1588 packet receiving and sending module, and the timestamp of the message from the interface conversion module is stored and is acquired from the timestamp compensation module; the interface conversion module mainly performs interface conversion to convert messages of PMA/PCS into a system clock domain; the PMA/PCS module converts signals received from a line interface into 8-bit data, sends the 8-bit data to the interface conversion module, converts messages received from the interface conversion module into signals and sends the signals to the line interface, meanwhile, the PMA/PCS module generates message header marks of receive _ sof and send _ sof of the received messages and sends the message header marks to the timestamp sampling module for timestamp sampling, and the message header marks are sent to the rising edge detection module to determine the time difference between the rising edge corresponding to the receive _ sof or send _ sof and the rising edge of the current period of the line clock. The timestamp sampled by the timestamp sampling module is generated by a system clock; the phase difference detection module carries out phase difference detection on the system clock and the line clock to obtain the phase difference between the system clock and the line clock, and sends the phase difference to the comparison module; the comparison module compares the phase difference with the time difference, and the timestamp compensation module correspondingly compensates the timestamp of the timestamp sampling module according to the comparison result of the comparison module to obtain the high-precision timestamp. The clock circuit is used for synchronizing the source device clock and generating the system clock.
Both the receive _ sof and send _ sof (hereinafter collectively sof) are generated in the line clock domain, and their rising edges typically lag behind the line clock. The sof of the actual message should be aligned with the rising edge of the line clock, so the phase difference between the line clock and the system clock is compensated instead of the difference between the generated sof and the rising edge of the system clock.
The specific compensation mode is as follows: the time that the sof lags the line clock is denoted as Δ t2, and the phase difference between the line clock and the system clock is denoted as Δ t 1. FIG. 4 is a timing diagram of sof between the line clock and the system clock provided by the fourth embodiment of the invention, and as shown in FIG. 4, when 0 ≦ Δ t2< Δ t1, the timestamps are t2- Δ t 1; fig. 5 is a timing diagram of the sof provided by the fourth embodiment of the invention after the system clock, and as shown in fig. 5, when Δ t2> - Δ t1, the timestamps are t3-Tclk _ sys- Δ t1, and Tclk _ sys is the clock cycle of clk _ sys.
For the message receiving direction: the PMA/PCS module processes signals received from a line interface and sends the obtained received messages to the interface conversion module; and generating a message header mark receive _ sof of the message, and sending the receive _ sof to the rising edge detection module and the timestamp sampling module. The rising edge detection module measures the time difference between the rising edge corresponding to the receive _ sof and the rising edge of the current period of the line clock under the line clock and sends the time difference to the comparison module. The timestamp sampling module carries out timestamp sampling on the received receive _ sof under the system clock to obtain a timestamp related to the 1588 message, and sends the timestamp to the timestamp compensation module, wherein the timestamp is the rising edge time corresponding to the rising edge of the next period of the system clock after the receive _ sof is received. The timestamp compensation module compensates the timestamp from the timestamp sampling module by using the comparison result of the phase difference and the time difference of the comparison module to obtain a high-precision timestamp, namely, if the phase difference is greater than the time difference, the timestamp and the phase difference are subtracted to obtain a compensated timestamp, otherwise, the timestamp, the phase difference and the system clock period are subtracted to obtain a compensated timestamp, and the compensated timestamp is sent to the 1588 message analysis and timestamp processing module. And finally, the 1588 message analyzing and timestamp processing module receives a received message converted from the line clock domain to the system clock domain by the interface conversion module, and if the message is analyzed to be the 1588 message, the compensated timestamp obtained from the timestamp compensation module is saved and used as the receiving time of the 1588 message.
For the message sending direction: the 1588 message analyzing and timestamp processing module receives a sending message from the 1588 packet receiving and sending module and sends the message to the interface conversion module. The interface conversion module converts the message from the system clock domain to the line clock domain and then sends the message to the PMA/PCS module. When the PMA/PCS module receives a sending message from the interface conversion module, a message header mark send _ sof of the sending message is generated and sent to the rising edge detection module and the timestamp sampling module. The rising edge detection module measures the time difference between the rising edge corresponding to the send _ sof and the rising edge of the current period of the line clock under the line clock and sends the time difference to the comparison module. And the timestamp sampling module carries out timestamp sampling on the received send _ sof under the system clock to obtain a timestamp related to the 1588 message, and sends the timestamp to the timestamp compensation module, wherein the timestamp is the rising edge time corresponding to the rising edge of the next period of the system clock after the send _ sof is received. The timestamp compensation module performs timestamp compensation on a comparison result of the phase difference and the time difference by using the comparison module, specifically, if the phase difference is greater than the time difference, the timestamp and the phase difference are subtracted to obtain a compensated timestamp, otherwise, the timestamp, the phase difference and the system clock cycle are subtracted to obtain a compensated timestamp, and the timestamp compensation module sends the compensated timestamp to the 1588 message analysis and timestamp processing module. Since the message has a certain length, after the 1588 message analyzing and timestamp processing module determines that the sent message is the 1588 message, the compensated timestamp obtained from the timestamp compensation module is added to the 1588 message to serve as the sending time of the 1588 message.
The higher the phase difference detection precision is, the higher the timestamp precision is, and the higher the precision of 1588 time synchronization is. The phase difference detection can be realized by adopting a high-frequency clock or TDC technology, and the 1588 synchronization precision can reach ns level and even ps level.
Fig. 6 is a block diagram of a fourth embodiment of the present invention for applying the apparatus to a GE electrical port, and as shown in fig. 6, the apparatus of the embodiment of the present invention is applied to the GE electrical port, and the hardware module portion thereof includes:
PMA/PCS Module: receiving direction, receiving signal from GE electric port, AD converting, digital equalizing, decoding to obtain 8bit parallel data, and generating receiving message header mark receive _ sof; in the sending direction, 8-bit parallel data are coded and shaped, then DA is converted into an analog signal, the analog signal is sent out through a GE electric port, and a sending message header flag send _ sof is generated; to ensure send _ sof/receive _ sof, there is no fifo between the production site and the GE electrical port.
An interface conversion module: clock domain and bus conversion, i.e. signal conversion between the system clock domain and the line clock domain, is performed.
1588 message parsing and timestamp processing module: and the server is responsible for message analysis, and performs corresponding timestamp processing after identifying the 1588 message.
1588 transceiver module: the method comprises the steps of sending, responding and terminating the 1588 message.
A timestamp sampling module: first, there is a timestamp counter under 125M clock of the system, when the receive _ sof or send _ sof arrives, the rising edge timestamp is recorded, and the recorded timestamp is sent to the timestamp compensation module for compensation.
A phase difference detection module: the phase difference between the system 125M clock and the line 125M clock is detected, which is a fixed value when the clocks are locked, which requires high accuracy for detection, and which can be implemented with high frequency clocks or TDC techniques.
Rising edge detection module: determining a time difference between a rising edge corresponding to send _ sof and a rising edge of the current period of the line clock under the line clock.
A comparison module: and comparing the phase difference determined by the phase difference detection module with the time difference determined by the rising edge detection module.
A timestamp compensation module: the different low-frequency clocks are used for generating the sof and sampling the timestamp, the accuracy is low, the phase difference of the two clocks needs to be compensated, the phase difference accuracy is higher, and the compensated timestamp is more accurate. And during specific compensation, different compensation modes are adopted according to the comparison result of the comparison module.
In this embodiment, the precision of the timestamp sampling is 8ns, and when the phase difference detection precision reaches 100ps, the precision of the compensated timestamp can be improved to 100 ps.
Phase locked loop and clock chip (equivalent to clock circuit): the source device clock is synchronized and a system clock is generated. The clock synchronization accuracy and the stability of the generated system clock directly affect the phase difference detection accuracy, and further affect the timestamp accuracy and the time synchronization accuracy, so that a high-performance phase-locked loop and a clock chip are required.
Although the present invention has been described in detail hereinabove, the present invention is not limited thereto, and various modifications can be made by those skilled in the art in light of the principle of the present invention. Thus, modifications made in accordance with the principles of the present invention should be understood to fall within the scope of the present invention.
Claims (6)
1. A1588-based time synchronization method comprises the following steps:
obtaining a phase difference between a system clock and a line clock according to the system clock and the line clock;
under a line clock, generating a message header marker of a 1588 message, and sending the generated message header marker to a system clock domain;
under a line clock, determining the time difference between a rising edge corresponding to a message header mark of the 1588 message and a rising edge of the current period of the line clock;
generating a timestamp related to the 1588 message under a system clock;
comparing the phase difference to the time difference;
if the phase difference is larger than the time difference, subtracting the phase difference from the timestamp to obtain a compensated timestamp, otherwise, subtracting the system clock cycle from the timestamp to obtain a compensated timestamp, and enabling the compensated timestamp to be consistent with a line clock.
2. The method according to claim 1, wherein the step of determining, under the line clock, a time difference between a rising edge corresponding to a packet header flag of the 1588 packet and a rising edge of a current cycle of the line clock comprises:
detecting a rising edge corresponding to the message header mark and a rising edge of the current period of the line clock under the line clock;
and determining the time difference between the rising edge corresponding to the message header mark and the rising edge of the current period of the line clock according to the detected rising edge corresponding to the message header mark and the rising edge of the current period of the line clock.
3. The method according to claim 1 or 2, wherein the step of generating a timestamp associated with the 1588 message under a system clock comprises:
and under a system clock, receiving the message header marker, and performing timestamp sampling on the received message header marker to obtain a timestamp related to the 1588 message.
4. A1588-based time synchronization apparatus, comprising:
the phase difference detection module is used for obtaining the phase difference between the system clock and the line clock according to the system clock and the line clock;
the PMA/PCS module is used for generating a message header mark of the 1588 message under a line clock and sending the generated message header mark to a system clock domain;
a rising edge detection module, configured to determine, under a line clock, a time difference between a rising edge corresponding to a message header flag of the 1588 message and a rising edge of a current period of the line clock;
the timestamp sampling module is used for generating a timestamp related to the 1588 message under a system clock;
and the timestamp compensation module is used for comparing the phase difference with the time difference, if the phase difference is greater than the time difference, subtracting the phase difference from the timestamp to obtain a compensated timestamp, otherwise, subtracting the phase difference from the system clock cycle from the timestamp to obtain the compensated timestamp, and enabling the compensated timestamp to be consistent with the line clock.
5. The apparatus according to claim 4, wherein the rising edge detecting module detects, under a line clock, a rising edge corresponding to the packet header flag and a rising edge of the current cycle of the line clock, and determines a time difference between the rising edge corresponding to the packet header flag and the rising edge of the current cycle of the line clock according to the detected rising edge corresponding to the packet header flag and the rising edge of the current cycle of the line clock.
6. The apparatus according to claim 4 or 5, wherein the timestamp sampling module is configured to receive the message header flag at a system clock, and obtain a timestamp associated with the 1588 message by performing timestamp sampling on the received message header flag.
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| CN201610448854.5A CN107528654B (en) | 2016-06-21 | 2016-06-21 | 1588-based time synchronization method and device |
| PCT/CN2017/087861 WO2017219881A1 (en) | 2016-06-21 | 2017-06-12 | Method and device for time synchronization based on 1588 standard |
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Families Citing this family (9)
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| CN110224775B (en) | 2018-03-01 | 2021-10-29 | 中兴通讯股份有限公司 | Method, device and equipment for determining time information |
| CN111245542B (en) * | 2018-11-28 | 2022-01-28 | 中兴通讯股份有限公司 | Method for acquiring time stamp and time synchronization system |
| CN110290580B (en) * | 2019-06-05 | 2021-08-20 | 深圳市英特瑞半导体科技有限公司 | Method and system for transmitting time based on 1588 protocol |
| CN112953669B (en) * | 2019-12-11 | 2022-04-29 | 烽火通信科技股份有限公司 | Method and system for improving timestamp precision |
| CN111800212B (en) * | 2020-06-12 | 2022-04-15 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and device |
| CN112235067B (en) * | 2020-09-24 | 2022-03-25 | 烽火通信科技股份有限公司 | Centralized 1588 time synchronization method and time synchronization system |
| CN113206665A (en) * | 2021-03-15 | 2021-08-03 | 新华三技术有限公司 | Signal sampling method and device |
| CN113904748A (en) * | 2021-09-24 | 2022-01-07 | 济南浪潮数据技术有限公司 | Clock synchronization method, system, device and medium |
| CN114422063B (en) * | 2021-12-13 | 2023-08-29 | 深圳市紫光同创电子有限公司 | Time stamp pulse synchronization method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769504A (en) * | 2012-07-11 | 2012-11-07 | 中兴通讯股份有限公司 | 1588 system and method thereof for achieving synchronization |
| CN102868515A (en) * | 2012-09-27 | 2013-01-09 | 烽火通信科技股份有限公司 | System time synchronization device and method in packet transport network |
| CN103546273A (en) * | 2013-10-31 | 2014-01-29 | 烽火通信科技股份有限公司 | Frequency synchronism device and method based on PTP frames |
| CN105577307A (en) * | 2014-10-14 | 2016-05-11 | 中兴通讯股份有限公司 | Method and apparatus for realizing time and clock synchronization |
Family Cites Families (4)
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