CN102957489B - Clock synchronization method and master-slave clock entity - Google Patents

Abstract

The embodiment of the invention discloses a clock synchronization method, which comprises the following steps that a slave clock marks a timestamp on a frame header of a frame received after a first message to be used as t2; the slave clock receives a second message including t1 sent by a master clock, wherein t1 is a timestamp on the frame header of one frame after the first message sent by the master clock, and the sequence of frames time stamped by the master clock after sending the first message is the same as that of frames time stamped by the master clock after sending the first message; the slave clock sends a third message to the master clock, and time stamps a frame header of one frame after the third message to be used as t3; the slave clock receives a fourth message including t4 from the master clock, wherein t4 is a timestamp on a frame header of one frame received by the master clock after the third message; the slave clock uses t1, t2, t3 and t4 to calculate to obtain Offset; and the self clock is adjusted in accordance with Offset.

Description

Clock synchronizing method, master-slave clock entity

The application is divisional application, and its female case is application number is 200810057606.3, and the applying date is on February 3rd, 2008, the application for a patent for invention that name is called " SDH network element time delay detecting method, clock synchronizing method, master-slave clock entity and SDH network element ".

Technical field

The present invention relates to Transport Network Technique field, particularly a kind of clock synchronizing method, master-slave clock entity.

Background technology

Synchronous object is that two or more clock is consistent in time.The mode of clock synchronous comprises master-slave synchronisation mode.Which be timing signal from master clock be sent to subordinate from clock, from the clock of clock according to the timing signal adjustment obtained self, synchronous with what keep with master clock.

In prior art a kind of master-slave synchronisation mode clock synchronizing method in message transmitting process as shown in Figure 1.As in figure, Tm is master clock, and Ts is from clock, master clock and be nonsynchronous from clock, there is clock correction (offset), need to make correctly to learn this offset from clock by the transmission of information between master-salve clock and reception, and then adjust self clock according to this offset.Specific as follows:

Step 101: master clock sends Sync message to from clock, and master clock record sends the time t1 of this Sync message; From the Sync message that clock reception master clock is sent, and from this message of the clock log t2 time of advent.

Step 102: master clock sends Follow up message to from clock, and this message comprises t1;

Like this, obtain from clock the time t1 that master clock sends Sync message.

Step 103: send Delay_Req message to master clock from clock, and from clock log transmitting time t3.

Step 104: master clock receives the Delay_Req message sent from clock, and this Delay_Req t4 time of advent of master clock record.

Step 105: master clock sends Delay_Resp message to from clock, comprises t4 in this message.

Like this, obtain from clock the time t4 that Delay_Req message arrives master clock.

So far, t1, t2, t3, t4 tetra-time values are obtained from clock.

As shown in fig. 1, also there is master clock to the propagation delay time Master_Slave_Delay from clock, and the propagation delay time Slave_Master_Delay from clock to master clock, then can utilize following formulae discovery Offset:

Offset=[(t2-t1)-(t4-t3)]/2-(Master_Slave_Delay-Slave_Master_Delay)/2

(1)

(Master_Slave_Delay-Slave_Master_Delay) in formula is that master clock arrives from clockwise with from clock to the two-way delay inequality in master clock direction.

Existing communication system, as 3G, telephone exchange, router etc., is carried in time division multiplexing (Time Division Multiplexing, TDM) transmission network mostly.TDM transmission network comprises synchronous digital hierarchy (Synchronous Digital Hierarchy, SDH) net and/or PDH (Pseudo-synchronous Digital Hierarchy) (Plesiochronous Digital Hierarchy, PDH) net.

With the 2 network configuration exemplary plot showing master-salve clock and transmission network in figure below.As in Fig. 2, SDH net can comprise some SDH network elements.

And in both direction, because fiber lengths is identical, and the difference of transmission direction on optical fiber can't cause the circuit delay that causes different, the circuit delay in both direction all can be set to W, then:

$\mathrm{Master}\_\mathrm{Slave}\_\mathrm{Delay}=W+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Master}-\mathrm{Slave}}$

$\mathrm{Slave}\_\mathrm{Master}\_\mathrm{Delay}=W+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Slave}-\mathrm{Master}}$

Then can obtain:

$\mathrm{Master}\_\mathrm{Slave}\_\mathrm{Delay}-\mathrm{Slave}\_\mathrm{Master}\_\mathrm{Delay}$

$=(W+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Master}-\mathrm{Slave}})-(W+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Slave}-\mathrm{Master}})$

$=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Master}-\mathrm{Slave}}-\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{Delay}{\left(i\right)}_{\mathrm{Slave}-\mathrm{Master}})$

$=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}(\mathrm{Delay}{\left(i\right)}_{\mathrm{Master}-\mathrm{Slave}}-\mathrm{Delay}{\left(i\right)}_{\mathrm{Slave}-\mathrm{Master}})---\left(2\right)$

This shows, circuit time delay W can disappear, and try to achieve master on each network element to from time delay and from the two-way delay inequality can trying to achieve this network element to main time delay, and then can in the hope of the transmission time delay difference of network elements all in both direction.

Above-mentioned Sync, Follow up, Delay_Req, Delay_Resp message all passes through SDH network element, is carried on SDH and nets in the E1 frame of the virtual container VC-12 of STM-N frame (namely SDH frame) below.Above-mentioned master clock is to from clockwise with from clock to the delay inequality in master clock direction, be actually the main time delay to each the SDH network element from process on direction, with the time delay from each the SDH network element to process in principal direction, the difference of these two time delays is exactly above-mentioned two-way delay inequality.

Both sides are all SDH interfaces (SDH mouth) or are all the SDH network element devices of PDH interface (PDH mouth), and for SDH interface, both sides are all directly transmit SDH frame, and for PDH interface, both sides are all directly transmit PDH frame (as E1 frame).Both sides are directly transmitted to the SDH interface of SDH frame, E1 frame is carried in the virtual container VC-12 in SDH frame, if and PDH(is as E1) speed and the speed of SDH network be homology, then the position of E1 frame in VC-12 is fixing, like this, can by detecting the position of SDH frame frame head and obtaining reception and the delivery time of this E1 frame to the pointer (pointer gauge understands time offset) of VC-12 frame, thus the time delay obtained on a direction, further, the time delay of both direction is done the two-way delay inequality that difference is this network element.Both sides are all directly transmitted to the PDH interface of E1 frame, can be received and delivery time by the position detecting E1 frame frame head, thus obtain the time delay on a direction, further, the time delay of both direction is done the two-way delay inequality that difference is this network element.

But be SDH interface for side, opposite side is the SDH network element device of PDH interface, and E1 frame is carried in SDH frame, the interface circuit of SDH network element device needs to map, and is loaded by E1 frame in the virtual container VC-12 of SDH frame and flows out.That commonly uses at present comprises a kind of asynchronous mapping mode, this mapping mode, is regard E1 signal as bit stream to map, and does not distinguish the frame head of E1 in VC-12.That is, the position of the frame head of E1 frame in VC-12 is arbitrary.When E1 is mapped to the frame structure that VC-12 is then multiplexed into STM-N, from line interface, the frame head of SDH and the pointer of wherein VC-12 frame can only be obtained, and the moment of the frame head of SDH adds that pointer can only determine the moment of VC-12 frame head, and the frame head of VC-12 can not be learnt to the frame head of wherein carried E1.That is, cannot accurately learn from PDH interface to the time delay on this direction of SDH interface.Correspondingly, after the SDH frame receiving the inflow of SDH interface, could at PDH interface transmission E1 frame after needing to carry out mapping, similarly, the frame head of the E1 carried to it due to the frame head of VC-12 in STH frame can not be learnt, therefore, the time delay on this direction also cannot be learnt.Like this, be SDH interface for side, opposite side is the SDH network element device of PDH interface, and the mode of prior art cannot obtain the time delay on this equipment, also just cannot obtain the two-way delay inequality on this equipment.

On the other hand, above-mentioned Sync, Follow up, Delay_Req, Delay_Resp message needs when transmission and reception just can be sent to circuit through master clock entity with from the inner corresponding interface chip process of clock entity.These inside chips need Sync, Follow u p, Delay_Req, Delay_Resp message encapsulation of transmission to send afterwards in a data frame, or extract from Frame and could receive.In general, master clock, from clockwork, t1, t2, t3 and t4 of record are the moment that respective chip starts message to encapsulate, or message are carried out from frame moment of extracting.To be packaged or after having extracted, just can really send and receive.That is, t1, t2, t3 and t4 of above-mentioned record are not the moment that above-mentioned message really sends or receives.Significantly, t1, t2, t3 and t4 of recording in prior art and transmission and receive the above-mentioned message actual moment occurred and there is certain deviation, this deviation is generally owing to there is jitter elimination circuit in interface chip and elastic buffers causes.This deviation equals encapsulation or the time delay required for leaching process.And this time delay is at master clock be different after powering up startup from clock at every turn.Like this, this time delay has no idea to eliminate in Clock Synchronization Procedure.Thus above-mentioned t1, t2, t3 and t4 are substituted into after in formula (1), the Offset value obtained has error, utilizes this Offset value can not realize synchronous with master clock from clock.

Summary of the invention

The object of the embodiment of the present invention is to provide a kind of clock synchronizing method and master-slave clock entity, to make master clock and to realize synchronous from clock.

For solving the problems of the technologies described above, the clock synchronizing method that the embodiment of the present invention provides, master-slave clock entity are achieved in that

A kind of clock synchronizing method, comprising:

From the first message that clock reception master clock is sent, the frame head of the frame received after this first message beats timestamp as t2;

From the second message comprising t1 that clock reception master clock is sent; On the frame head of the frame that t1 is master clock after described first message sent the timestamp beaten, and the order of frame after transmission first message that timestamp beaten by master clock is identical with the order of frame after the first message received beating timestamp from clock;

Send the 3rd message to master clock from clock, and the frame head of a frame after the 3rd message beats timestamp as t3;

From the 4th message comprising t4 that clock reception master clock is sent; On the frame head of the frame that t4 is master clock after described 3rd message received the timestamp beaten, and the order of frame after reception the 3rd message that timestamp beaten by master clock is identical with the order of frame after transmission the 3rd message beating timestamp from clock;

T1, t2, t3 and t4 is utilized to calculate Offset from clock;

Adjust the clock of self according to Offset from clock.

The described order of frame after the first message beating timestamp is predefined, or is indicated to from clock in the first message sent by master clock.

The described order of frame after the 3rd message beating timestamp is predefined, or is indicated to master clock by the 3rd message sent from clock.

Described first message and the 3rd message have passed in one or more frame.

When described first message and the 3rd message have passed in a frame, this first message and the 3rd message-length are set as 8, and this coding of 8 comprises more than 7 or 7 continuous print " 1 ".

In described second message and the 4th message, for the information that frame transmits, then inserting one " 0 " thereafter if there is 5 continuous print " 1 "; Correspondingly, if find that there is 5 continuous print " 1 " at receiving terminal, following closely " 0 " is removed.

A kind of master clock entity, comprises the first message sending unit, the first timing unit, the second message sending unit, the 3rd message reception units, the 4th timing unit, the 4th message sending unit, wherein,

First message sending unit, for sending the first message;

First timing unit, on the frame head of the frame after described first message beat timestamp as t1;

Second message sending unit, for sending the second message comprising t1;

3rd message reception units, for receiving the 3rd message;

4th timing unit, beats timestamp as t4 on the frame head of the frame after the 3rd message;

4th message sending unit, for sending the 4th message comprising t4.

The order of frame after the first message that timestamp is beaten in instruction is comprised in described first message.

Comprise the order of frame after the 3rd message that timestamp is beaten in instruction in described 3rd message, correspondingly, the 4th timing unit beats timestamp as t4 according on the frame head of the frame of corresponding order after the 3rd message of the instruction in the 3rd message.

One, from clock entity, comprises the first message reception units, the second timing unit, the second message reception units, the 3rd message sending unit, the 3rd timing unit, the 4th message reception units, Offset computing unit, clock adjustment unit, wherein,

First message reception units, for receiving the first message sent;

Second timing unit, beats timestamp as t2 on the frame head of the frame received after the first message;

Second message reception units, for receiving the second message comprising t1 sent;

3rd message sending unit, for sending the 3rd message;

3rd timing unit, on the frame head of the frame after described 3rd message beat timestamp as t3;

4th message reception units, for receiving the 4th message comprising t4 sent;

Offset computing unit, utilizes the calculation of parameter comprising t1, t2, t3 and t4 to obtain Offset;

Clock adjustment unit, according to the clock of Offset adjustment from clock.

The order of frame after the 3rd message that timestamp is beaten in instruction is comprised in described 3rd message.

Comprise the order of frame after the first message that timestamp is beaten in instruction in described first message, correspondingly, the second timing unit beats timestamp as t2 according on the frame head of the frame of corresponding order after the first message of the instruction in the first message.

The technical scheme provided from the above embodiment of the present invention, master clock and be all that timestamp is beaten to frame head from clock, namely send the moment to frame head to detect, this moment can accurately obtain, thus moment of accurately obtaining can be utilized to calculate offset from clock, thus it is synchronous to realize with master clock.

Accompanying drawing explanation

Fig. 1 is message transmitting process in the clock synchronizing method of a kind of master-slave synchronisation mode in prior art;

Fig. 2 is the network configuration exemplary plot of master-salve clock and transmission network in prior art;

Fig. 3 is the flow chart of SDH network element time delay detecting method embodiment of the present invention;

Fig. 4 is the block diagram of SDH network element device embodiment of the present invention;

Fig. 5 is the flow chart of clock synchronizing method embodiment of the present invention;

Fig. 6 is the frame structure schematic diagram of HDLC of the present invention;

Fig. 7 is master clock physical embodiment block diagram of the present invention;

Fig. 8 is that the present invention is from clock entity embodiment.

Embodiment

Below introduce a kind of SDH network element time delay detecting method and SDH network element that the embodiment of the present invention provides.

Fig. 3 shows the flow process of SDH network element time delay detecting method embodiment, as figure:

Step 301: the moment that on the moment that the frame head detecting E1 frame on SDH network element PDH interface flows out and SDH interface, the frame head of SDH frame flows into; Or the moment that on the frame head detecting SDH frame on SDH network element SDH interface moment of flowing out and PDH interface, the frame head of E1 frame flows into.

While be SDH interface, another side is the SDH network element device of PDH interface, for flowing into as PDH interface, outflow are the direction of SDH interface, then can detect the moment of the frame head obtaining the E1 frame that PDH interface flows into, and the moment of the frame head obtaining the SDH frame that SDH interface flows out can be detected.Wherein, as previously mentioned, in the VC-12 in the SDH frame that SDH interface flows out, E1 frame is comprised.

For flowing into as SDH interface, outflow are the direction of PDH interface, then can detect the moment of the frame head obtaining the SDH frame that SDH interface flows into, and the moment of the frame head obtaining the E1 frame that PDH interface flows out can be detected.Wherein, as previously mentioned, in the VC-12 in the SDH frame that SDH interface flows into, E1 frame is comprised.

Step 302: using the difference in moment of SDH frame frame head that the moment of E1 frame frame head SDH network element PDH interface flowed into or flow out and SDH interface flows out or flow into as the time delay on this SDH network element direction.

One end for outflow network element is SDH interface, and the one end flowing into network element is the situation of E1 interface, and can be considered as at the Time Transmission relay baton of SDH interface is some SDH frame heads, is some E1 frame heads at the Time Transmission relay baton of E1 interface.Like this, the time of this network element of outflow of SDH interface is the entry time of Time Transmission relay baton, and the time of this network element of inflow of E1 interface is the Outlet time of Time Transmission relay baton.The Outlet time of the time relay baton of this network element deducts entry time and is described inflow, flows out the propagation delay time of time relay baton on direction, namely the propagation delay time of the party's upwards this network element device.

One end for outflow network element is E1 interface, and the one end flowing into network element is the situation of SDH interface, and in like manner, can be considered as at the Time Transmission relay baton of SDH interface is some SDH frame heads, is some E1 frame heads at the Time Transmission relay baton of E1 interface.Like this, the Outlet time of the time relay baton of this network element deducts entry time and is described inflow, flows out the propagation delay time of time relay baton on direction, namely the propagation delay time of the party's upwards this network element device.

The method also comprises step 303 further: using the two-way delay inequality of the difference of the time delay in SDH network element both direction as this SDH network element.

Obtain the time delay of both direction, the time delay of this both direction is done difference, just obtain the two-way delay inequality of this SDH network element.

It should be noted that, completing the equipment calculating two-way delay inequality can be SDH network element device, such as by one end be SDH interface, the other end is that the SDH network element device of PDH interface calculates its two-way delay inequality, also can be other SDH network element device, that is after a SDH network element device detects the time delay on two direction, these two time delays are sent to another SDH network element device, calculate two-way delay inequality by another network element device.And may be also to unifiedly calculate the two-way delay inequality that SDH nets each SDH network element device interior by webmaster.Here do not limit.

Two-way delay inequality can also be sent to from clock after step 303.Thus calculate the two-way delay inequality of SDH net from clock according to the two-way delay inequality of other network element device the two-way delay inequality of this SDH network element device and SDH net.

Send the main body that two-way delay inequality step performs, according to calculating the difference of two-way delay inequality main body, the SDH network element device of can be SDH interface be PDH interface, also can be other SDH network element device, can also be sent by webmaster.Here also do not limit.

From clock, to obtain this be PDH interface while be the two-way delay inequality of the SDH network element device of SDH interface, and the two-way delay inequality of other SDH network element device can be obtained, then from aforementioned, the two-way delay inequality of SDH net can be obtained by formula (2) from clock, the time that four message passing through again to send are relevant, namely the t1 that Sync, Follow up, Delay_Req, Delay_Resp message is relevant, t2, t3, t4, then can calculate offset according to formula (1), thus the clock of self can be adjusted according to the offset obtained from clock.

Especially, one end is SDH interface, and the other end is the SDH network element device of PDH interface, and what send or receive at SDH interface is SDH frame, and what send or receive at PDH interface is E1 frame, and inner at network element device, E1 frame and SDH frame need through mapping and going to map process.Described mapping and go mapping to take the regular hour, namely produces certain time delay.If this time delay is more than the duration of a frame, in order to obtain the time delay of this network element more accurately, according to described processing delay, the network element time delay recorded can be added specific frame period, each frame period is existing is 125 μ s.It should be noted that, the scope of the propagation delay time of the equipment of oneself is known by SDH manufacturer.By propagation delay time divided by 125us, can then get the integer of business, and remaining decimal, can be obtained by actual measurement.

It should be noted that, it is SDH interface that said method not only can detect one end, and the other end is the propagation delay time on a direction of the SDH network element device of PDH interface, is all SDH interface for two ends, or two ends are all the situations of PDH interface, still can be suitable for.That is, above-described embodiment can be suitable for for the situation that two ends are distinct interface or same-interface.At this moment, corresponding method is:

Detect the SDH network element two ends moment of frame head outflow and the moment of frame head inflow in one direction;

The difference in the moment that the moment of flow out frame head on direction described in SDH network element and frame head flow into is as the time delay on direction described in this SDH network element.

And be only illustrated embodiment for E1 frame in above-described embodiment, in fact, be also suitable for for frames such as E2, E3, the situation of SDH frame is also similar, is not restricted in the present invention.

From above-described embodiment, in the one end flowing into network element, Time Transmission relay baton is considered as on the SDH frame head flowing into this network element or E1 frame head, in the one end of flowing out network element, Time Transmission relay baton is considered as on the E1 frame flowing out this webpage or SDH frame head, like this, the Outlet time of the time relay baton of this network element deducts the propagation delay time that entry time is the party's upwards time relay baton, namely the propagation delay time of the party's upwards this network element device.

Below introduce SDH network element device, Fig. 4 shows the block diagram of this SDH network element device, as figure:

A kind of SDH network element device, comprises and flows into frame head moment detecting unit 401, flows out frame head moment detecting unit 402, time delay determining unit 403, wherein,

Flow into frame head moment detecting unit and flow out the two ends that frame head moment detecting unit lays respectively at SDH network element device;

Flow into frame head moment detecting unit 401, for detecting the moment that frame head flows into;

Flow out frame head moment detecting unit 402, for detecting the moment that frame head flows out;

Time delay determining unit 403, the difference in the moment that the moment of flow out frame head and frame head flow into is as SDH network element device the party time delay upwards.

This SDH network element device, is characterized in that, also comprises compensating unit 404, and the time delay for time delay determining unit being determined increases the frame period of the corresponding number of SDH network element handling duration.

This SDH network element device can also comprise two-way delay inequality determining unit 405, and the difference of the time delay in the both direction described time delay determining unit determined is defined as two-way delay inequality.

The frame head of described inflow is the frame head that frame head or SDH interface that PDH interface flows into flow into; The frame head of described outflow is the frame head that frame head or PDH interface that SDH interface flows out flow out.

Below introduce clock synchronizing method embodiment of the present invention.Fig. 5 shows the flow process of this embodiment, as figure, comprising:

Step 501: the first message sent from clock reception master clock, the frame head of the frame received after this first message beats timestamp as t2.

Above-mentioned first message can be aforesaid Sync message.

The frame head of the frame received after the first message beats timestamp, the frame head time of the frame received after being acquisition first message.The meaning of below beating timestamp is similar.

Step 502: the second message comprising t1 sent from clock reception master clock.

Above-mentioned second message can be aforesaid Follow up message.T1 is comprised in this message.

On the frame head of the frame that t1 is master clock after described first message sent the timestamp beaten.

Here, the master clock frame (beating the frame at the frame head place of timestamp) of beating timestamp after transmission first message with receive the first message from clock after beat timestamp frame be the frame of same order after the first message.

The described order of frame after the first message beating timestamp can be predefined, timestamp beaten by such as master clock and the frame head of the frame of closelying follow after the first message all fixed from clock, then timestamp beaten by such as master clock and the frame head of the 3rd frame after the first message all fixed from clock.

The described order of frame after the first message beating timestamp also can be informed from clock by master clock.Such as, master clock sends the first message, and the frame head of a frame of closelying follow in this first message beats timestamp, and indicates the frame head of a frame of closelying follow after this first message from clock to beat timestamp in described first message.Afterwards, receive the first message from clock, according to the instruction of the first message, the frame head of a frame of closelying follow after the first message can beat timestamp.Again such as, after master clock sends the first message, the frame head of the 3rd frame after this first message beats timestamp, described first message instruction beats timestamp from the frame head of the 3rd frame of clock after this first message, like this, from clock after receiving the first message, according to the instruction of the first message, the frame head of the 3rd frame after the first message beats timestamp.

The frame head of the frame of closelying follow after the first message above beats timestamp, and the frame head of the 3rd frame after the first message beats the situation of timestamp, just citing is illustrated, so that understand, is not limit.

Step 503: send the 3rd message to master clock from clock, and the frame head of a frame after the 3rd message beats timestamp as t3.

Above-mentioned 3rd message can be aforesaid Delay_Req message.

Step 504: the 4th message comprising t4 sent from clock reception master clock.

Above-mentioned 4th message can be aforesaid Delay_Resp message.

On the frame head of the frame that t4 is master clock after described 3rd message received the timestamp beaten.

Here, the master clock frame (beating the frame at the frame head place of timestamp) of beating timestamp after reception the 3rd message with send the 3rd message from clock after beat timestamp frame be the 3rd message after the frame of same order.

The described order of frame after the 3rd message beating timestamp can be predefined, timestamp beaten by such as master clock and the frame head of the frame of closelying follow after the 3rd message all fixed from clock, then timestamp beaten by such as master clock and the frame head of the 3rd frame after the 3rd message all fixed from clock.

The described order of frame after the 3rd message beating timestamp also can be inform master clock by from clock.Such as, after clock sends the 3rd message, the frame head of one frame of closelying follow in the 3rd message beats timestamp, the frame head of the frame that described 3rd message instruction master clock is closelyed follow after the 3rd message beats timestamp, like this, master clock, after receiving the 3rd message, according to the instruction of the 3rd message, the frame head of a frame of closelying follow after the 3rd message beats timestamp.Again such as, after clock sends the 3rd message, the frame head of the 3rd frame after the 3rd message beats timestamp, the frame head of three frame of described 3rd message instruction master clock after the 3rd message beats timestamp, like this, master clock, after receiving the 3rd message, according to the instruction of the first message, the frame head of the 3rd frame after the 3rd message beats timestamp.

The frame head of the frame of closelying follow after the 3rd message above beats timestamp, and the frame head of the 3rd frame after the 3rd message beats the situation of timestamp, just citing is illustrated, so that understand, is not limit.

So far, t1, t2, t3, t4 tetra-time values are obtained from clock.

Step 505: utilize aforementioned formula (1) to calculate Offset from clock.

Master in this formula to from time delay with from the difference to main time delay, i.e. (Master_Slave_Delay-Slave_Master_Delay), for the SDH network element of to be all SDH interface or two ends be all at two ends PDH interface, several method can be had in prior art to record, do not repeat them here.Net for SDH the SDH network element that the one end comprised is SDH interface, the other end is PDH interface, the SDH network element time delay detecting method embodiment that can propose according to the present invention above realizes.Like this, the two-way delay inequality of SDH net can obtain, thus can calculate Offset according to formula (1) from clock.

Step 506: the clock adjusting self from clock according to Offset.

Mention above, the transmission of message and reception need through master clock and corresponding chip carries out from clockwork encapsulation and extraction process.In the process of transmitting of message, need the message encapsulation that sends in frame after, add that frame originating point information will send, beat timestamp in the embodiment of the present invention to frame head, namely send the moment to frame head and detect, this moment can accurately obtain.And what detect in prior art is the moment starting to encapsulate, and is encapsulated into send and there is certain time delay, it is inaccurate that the timestamp that can cause like this is beaten.In the receiving course of message, first the message received just extract the message in Frame further through reading frame originating point information, beat timestamp to the frame head received in the embodiment of the present invention, namely detect the moment that frame head receives, this moment can accurately obtain.And what detect in prior art is the moment extracting message from frame, and there is certain time delay to extracting message in the frame received, and it is inaccurate that the timestamp that so also can cause is beaten.

In the prior art, because Sync and Delay_Req message is the message of beating timestamp, very sensitive to time delay, be therefore delay sensitive message.In the embodiment of the present invention, the frame head of a Frame after Sync and Delay_Req message needs to beat timestamp by transmit leg and recipient, recipient is after obtaining Sync and Delay_Req message in time, just can know and beat timestamp on the frame of below, in order to keep transmit leg to beat timestamp on the frame head of same Frame, transmit leg needs accurately to know the Sync message sent.Like this, Sync and Delay_Req message is delay sensitive message equally.

Above-mentioned delay sensitive message can pass in more than one frame, at this moment, still can be beat timestamp to the frame head of the frame of closelying follow after delay sensitive message, or beat timestamp to the frame head of the particular frame of after delay sensitive message.But delay sensitive message completes in a frame and sends and receive, it is the simplest on realizing and the method that precision is the highest.But if the message of definition unified 8bit length, can not carry enough amount of information again, be balance timing accuracy and the problem of carrying enough information, the present invention is following special frame structure openly:

To the message of delay sensitive, comprise the first message or the 3rd message, such as Sync, Delay_Req, setting its length is 8 hytes, has transmitted in a frame, and its coding comprises more than 7 or 7 continuous print " 1 ".As: " 11111110 ", " 01111111 ", " 11111111 ".

In addition, to the insensitive message of timing, comprise the second message or the 4th message, such as Follow_Up, Delay_Resp, similar HDLC(High level Data Link Control protocol can be used, High level data link control) frame structure, set being encoded to of its frame head and postamble: " 01111110 ".The frame structure of HDLC as shown in Figure 6, can comprise frame head, information field, cyclic redundancy check (CRC) code (CRC) and postamble, being wherein encoded to of frame head and postamble: " 01111110 ".In order to accomplish transparent transmission, namely allow frame, the information that namely information field transmits can be arbitrary bit sequence, adopts " 0 " bit insertion.If there is the place of 5 continuous print " 1 " will insert one " 0 ", if find that there is 5 continuous print " 1 " at receiving terminal, " 0 " following closely will be removed.

On the other hand, not beat timestamp on the frame head of Sync, Follow up, Delay_Req, Delay_Resp message place Frame in the embodiment of the present invention, this is because frame head is foremost at Frame, and the data division of above-mentioned message in the frame structure after frame head transmits, after receiving terminal receives the frame comprising above-mentioned message, the process of frame head completes, and cannot beat timestamp again on current frame head.Therefore, the frame head of a particular frame after delay sensitive message beats timestamp, transmit leg and recipient can detect delivery time and the time of reception with the transmitting procedure of the frame of same order after delay sensitive message, and the moment recorded like this is moment accurately.

Below introduce master clock physical embodiment of the present invention, Fig. 7 shows the block diagram of this embodiment, as figure:

A kind of master clock entity, comprises the first message sending unit 701, first timing unit 702, second message sending unit the 703, three message reception units the 704, four timing unit the 705, four message sending unit 706, wherein,

First message sending unit 701, for sending the first message;

First timing unit 702, on the frame head of the frame after described first message beat timestamp as t1;

Second message sending unit 703, for sending the second message comprising t1;

3rd message reception units 704, for receiving the 3rd message;

4th timing unit 705, beats timestamp as t4 on the frame head of the frame after the 3rd message;

4th message sending unit 706, for sending the 4th message comprising t4.

The order of frame after the first message that timestamp is beaten in instruction is comprised in described first message.

Comprise the order of frame after the 3rd message that timestamp is beaten in instruction in described 3rd message, correspondingly, the 4th timing unit 705 beats timestamp as t4 according on the frame head of the frame of corresponding order after the 3rd message of the instruction in the 3rd message.

Below introduce master clock physical embodiment of the present invention, Fig. 8 shows the block diagram of this embodiment, as figure:

A kind of from clock entity, comprise the first message reception units 801, second timing unit 802, second message reception units 803,3rd message sending unit the 804, three timing unit the 805, four message reception units 806, Offset computing unit 807, clock adjustment unit 808, wherein

First message reception units 801, for receiving the first message sent;

Second timing unit 802, beats timestamp as t2 on the frame head of the frame received after the first message;

Second message reception units 803, for receiving the second message comprising t1 sent;

3rd message sending unit 804, for sending the 3rd message;

3rd timing unit 805, on the frame head of the frame after described 3rd message beat timestamp as t3;

4th message reception units 806, for receiving the 4th message comprising t4 sent;

Offset computing unit 807, utilizes the calculation of parameter comprising t1, t2, t3 and t4 to obtain Offset;

Clock adjustment unit 808, according to the clock of Offset adjustment from clock.

The order of frame after the 3rd message that timestamp is beaten in instruction is comprised in described 3rd message.

Comprise the order of frame after the first message that timestamp is beaten in instruction in described first message, correspondingly, the second timing unit beats timestamp as t2 according on the frame head of the frame of corresponding order after the first message of the instruction in the first message.

Below reintroduce a kind of clock synchronizing method, particularly comprise for master clock with from the SDH transmission network between clock the SDH network element that one end is SDH interface, the other end is PDH interface, the method comprises:

From the first message that clock reception master clock is sent, the frame head of the frame data received after this first message beats timestamp as t2;

From the second message comprising t1 that clock reception master clock is sent; On the frame head of the frame data that t1 is master clock after described first message sent the timestamp beaten, and the order of frame after transmission first message that timestamp beaten by master clock is identical with the order of frame after the first message received beating timestamp from clock;

Send the 3rd message to master clock from clock, and the frame head of frame data after the 3rd message beats timestamp as t3;

From the 4th message comprising t4 that clock reception master clock is sent; On the frame head of the frame data that t4 is master clock after described 3rd message received the timestamp beaten, and the order of frame after reception the 3rd message that timestamp beaten by master clock is identical with the order of frame after transmission the 3rd message beating timestamp from clock;

Detect the SDH network element two ends moment of frame head outflow and the moment of frame head inflow in one direction;

The difference in the moment that the moment of flow out frame head on a direction described in SDH network element and frame head flow into is as the time delay on direction described in this SDH network element;

Utilize t1, t2, t3, t4 from clock, and utilize the two-way delay inequality of the described SDH network element received to calculate Offset; The two-way delay inequality of described SDH network element is the difference of the time delay in both direction described in SDH network element;

Adjust the clock of self according to Offset from clock.

From above embodiment, master clock and be all that timestamp is beaten to frame head from clock, namely send the moment to frame head and detect, this moment can accurately obtain, thus moment of accurately obtaining can be utilized to calculate offset from clock, thus it is synchronous to realize with master clock.

Although depict the embodiment of the present invention by embodiment, those of ordinary skill in the art know, the present invention has many distortion and change and do not depart from spirit of the present invention, and the claim appended by wishing comprises these distortion and change and do not depart from spirit of the present invention.

Claims (8)

1. a clock synchronizing method, is characterized in that, comprising:

From the first message that clock reception master clock is sent, the frame head of the frame received after this first message beats timestamp as t2;

From the second message comprising t1 that clock reception master clock is sent; On the frame head of the frame that t1 is master clock after described first message sent the timestamp beaten, and the order of frame after transmission first message that timestamp beaten by master clock is identical with the order of frame after the first message received beating timestamp from clock;

Send the 3rd message to master clock from clock, and the frame head of a frame after the 3rd message beats timestamp as t3;

From the 4th message comprising t4 that clock reception master clock is sent; On the frame head of the frame that t4 is master clock after described 3rd message received the timestamp beaten, and the order of frame after reception the 3rd message that timestamp beaten by master clock is identical with the order of frame after transmission the 3rd message beating timestamp from clock;

T1, t2, t3 and t4 is utilized to calculate Offset from clock;

Adjust the clock of self according to Offset from clock.

2. the method for claim 1, is characterized in that, the described order of frame after the first message beating timestamp is predefined, or is indicated to from clock in the first message sent by master clock.

3. the method for claim 1, is characterized in that, the described order of frame after the 3rd message beating timestamp is predefined, or is indicated to master clock by the 3rd message sent from clock.

4. the method for claim 1, is characterized in that, described first message and the 3rd message have passed in one or more frame.

5. method as claimed in claim 4, it is characterized in that, when described first message and the 3rd message have passed in a frame, this first message and the 3rd message-length are set as 8, and this coding of 8 comprises more than 7 or 7 continuous print " 1 ".

6. method as claimed in claim 4, is characterized in that, in described second message and the 4th message, for the information that frame transmits, is then inserting one " 0 " thereafter if there is 5 continuous print " 1 "; Correspondingly, if find that there is 5 continuous print " 1 " at receiving terminal, following closely " 0 " is removed.

7. a master clock entity, is characterized in that, comprises the first message sending unit, the first timing unit, the second message sending unit, the 3rd message reception units, the 4th timing unit, the 4th message sending unit, wherein,

First message sending unit, for sending the first message;

First timing unit, on the frame head of the frame after described first message beat timestamp as t1;

Second message sending unit, for sending the second message comprising t1;

3rd message reception units, for receiving the 3rd message;

4th timing unit, beats timestamp as t4 on the frame head of the frame after the 3rd message;

4th message sending unit, for sending the 4th message comprising t4;

The order of frame after the first message that timestamp is beaten in instruction is comprised in described first message;

Comprise the order of frame after the 3rd message that timestamp is beaten in instruction in described 3rd message, correspondingly, the 4th timing unit beats timestamp as t4 according on the frame head of the frame of corresponding order after the 3rd message of the instruction in the 3rd message.

8. from a clock entity, it is characterized in that, comprise the first message reception units, the second timing unit, the second message reception units, the 3rd message sending unit, the 3rd timing unit, the 4th message reception units, Offset computing unit, clock adjustment unit, wherein,

First message reception units, for receiving the first message sent;

Second timing unit, beats timestamp as t2 on the frame head of the frame received after the first message;

Second message reception units, for receiving the second message comprising t1 sent;

3rd message sending unit, for sending the 3rd message;

3rd timing unit, on the frame head of the frame after described 3rd message beat timestamp as t3;

4th message reception units, for receiving the 4th message comprising t4 sent;

Offset computing unit, utilizes the calculation of parameter comprising t1, t2, t3 and t4 to obtain Offset;

Clock adjustment unit, according to the clock of Offset adjustment from clock;

The order of frame after the 3rd message that timestamp is beaten in instruction is comprised in described 3rd message;

Comprise the order of frame after the first message that timestamp is beaten in instruction in described first message, correspondingly, the second timing unit beats timestamp as t2 according on the frame head of the frame of corresponding order after the first message of the instruction in the first message.