CN103546270A - Clock synchronization method and system of power distribution terminal - Google Patents
Clock synchronization method and system of power distribution terminal Download PDFInfo
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- CN103546270A CN103546270A CN201310499418.7A CN201310499418A CN103546270A CN 103546270 A CN103546270 A CN 103546270A CN 201310499418 A CN201310499418 A CN 201310499418A CN 103546270 A CN103546270 A CN 103546270A
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Abstract
The invention belongs to the field of electric power, and provides a clock synchronization method and system of a power distribution terminal. The clock synchronization method of the power distribution terminal comprises the steps that when main clock equipment sends a first message to the power distribution terminal, the power distribution terminal receives a first hardware timestamp and obtains a second hardware timestamp while receiving the first message, and when sending a third message to the main clock equipment, the power distribution terminal obtains a third hardware timestamp while sending the third message and receives a fourth hardware timestamp; the power distribution terminal determines synchronous clock difference between the clock of the power distribution terminal and the clock of the main clock equipment, and the clock of the power distribution terminal is corrected according to the synchronous clock difference; correct receiving of interactive data between the main clock equipment and the power distribution terminal or among the power distribution terminals is guaranteed.
Description
Technical field
The invention belongs to power domain, relate in particular to a kind of clock synchronizing method and system of distribution terminal.
Background technology
Electric power system is time-dependent system, and the electric parameters such as voltage, electric current, phase angle are all time-based variations and changing.Power network safety operation has proposed new requirement to distribution terminal; particularly to time synchronized; require the time reference operation of the distribution terminals such as protective relaying device, automation equipment, measurement supervising device, EMS and Style Product Information Management System based on unified, to meet synchronized sampling, system stability distinguishing, line fault location, failure wave-recording, accident analysis and the requirement of accident inversion time consistency.
At present, in order to realize the clock synchronous of each distribution terminal, the clock that clock equipment employing time synchronized time protocol Network Based (NTP/SNTP) is controlled each distribution terminal, to realize clock synchronous, is generally that the precision of clock synchronous can reach 50ms, and precision is not high.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of clock synchronizing method of distribution terminal, by carrying out message interaction to obtain hardware timestamping between clock equipment and controller switching equipment, further realize the clock of controller switching equipment and the clock synchronous of clock equipment, improve the precision of clock synchronous.
On the one hand, a kind of clock synchronizing method of distribution terminal, the clock synchronizing method of described distribution terminal comprises:
S11, when clock equipment sends the first message to distribution terminal, described distribution terminal receives the first hardware timestamping and obtains the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment is obtained the hardware timestamping while sending described the first message, when described distribution terminal sends described the 3rd message to described clock equipment, described distribution terminal obtains the 3rd hardware timestamping while sending described the 3rd message and receives the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment is obtained the hardware timestamping while receiving described the 3rd message,
S12, described distribution terminal, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, determines that the synchronised clock of the clock of described distribution terminal and the clock of described clock equipment is poor;
S13, described distribution terminal according to the clock of the described distribution terminal of the poor correction of described synchronised clock with the clock synchronous with described clock equipment.
On the other hand, another object of the present invention is to provide a kind of clock system of distribution terminal, and the clock system of described distribution terminal comprises:
Clock equipment, and one or more distribution terminal;
Described distribution terminal, when described clock equipment sends the first message to described distribution terminal, receive the first hardware timestamping and obtain the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment is obtained the hardware timestamping while sending described the first message, when described distribution terminal sends described the 3rd message to described clock equipment, obtain the 3rd hardware timestamping while sending described the 3rd message and receive the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment is obtained the hardware timestamping while receiving described the 3rd message, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, the synchronised clock of determining the clock of described distribution terminal and the clock of described clock equipment is poor, according to the clock of the described distribution terminal of the poor correction of described synchronised clock with the clock synchronous with described clock equipment.
The invention has the beneficial effects as follows: clock equipment and distribution terminal carry out message interaction, it is poor that distribution terminal calculates synchronised clock according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, and according to the clock of the poor adjustment distribution terminal of described synchronised clock with the clock synchronous with described clock equipment; Thereby, guarantee between clock equipment and distribution terminal or the correct reception of each distribution terminal interaction data each other; Realize the time reference operation of the distribution terminals such as protective relaying device, automation equipment, measurement supervising device, EMS and Style Product Information Management System based on unified.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the realization flow figure of the clock synchronizing method of the distribution terminal that provides of the embodiment of the present invention one;
Fig. 2 is the system architecture diagram of the clock system of the kind distribution terminal that provides of the embodiment of the present invention two.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
For technical solutions according to the invention are described, below by specific embodiment, describe.
It should be noted that, " first " in embodiments of the present invention, " second ", " the 3rd " and " the 4th " are acute pyogenic infection of finger tip, only for distinguishing.
embodiment mono-:
Fig. 1 shows the realization flow of the clock synchronizing method of the distribution terminal that the present embodiment provides, and for convenience of description, only shows the part relevant to the embodiment of the present invention, and details are as follows for its realization flow:
S11, when clock equipment sends the first message to distribution terminal, described distribution terminal receives the first hardware timestamping and obtains the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment is obtained the hardware timestamping while sending described the first message, when described distribution terminal sends described the 3rd message to described clock equipment, described distribution terminal obtains the 3rd hardware timestamping while sending described the 3rd message and receives the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment is obtained the hardware timestamping while receiving described the 3rd message,
In the present embodiment, described hardware timestamping comprises the first hardware timestamping, the second hardware timestamping, the 3rd hardware timestamping and the 4th hardware timestamping.
It should be noted that, message comprises described the first message and described the 3rd message.
In the present embodiment, when obtaining respectively the first hardware timestamping, the second hardware timestamping, the 3rd hardware timestamping and the 4th hardware timestamping, clock equipment can repeatedly be carried out message interaction with distribution terminal, particularly, clock equipment can repeatedly send described the first message to distribution terminal; Or distribution terminal can repeatedly send described the 3rd message to clock equipment, clock equipment is fed back the 3rd message to distribution terminal.Preferably, clock equipment and controller switching equipment to described message carry out at least 2 times above mutual, and then obtain respectively the first hardware timestamping, the second hardware timestamping, the 3rd hardware timestamping and the 4th hardware timestamping, to realize the clock of distribution terminal and the clock synchronous of clock equipment.
It should be noted that, clock equipment or distribution terminal, when sending message, can record the software timestamp and the hardware timestamping that send described message.Wherein, software timestamp is the software of clock equipment or the distribution terminal timestamp when sending described message; Wherein, hardware timestamping is the timestamp of described message while leaving clock equipment or distribution terminal; Therefore the time that, sends the hardware timestamping of described message is later than the software timestamp that sends described message.
In like manner, clock equipment or distribution terminal, when receiving message, can record the software timestamp and the hardware timestamping that receive described message.Wherein, hardware timestamping is the timestamp of described message while leaving clock equipment or distribution terminal; Wherein, software timestamp is the software of clock equipment or the distribution terminal timestamp when receiving described message; Therefore the software timestamp that, receives described message is later than the time of the hardware timestamping that receives described message.
As one embodiment of the invention, described step S11 also comprises:
Described clock equipment sends the first hardware timestamping of described the first message described the first message of record transmission to described distribution terminal, described distribution terminal record receives the second hardware timestamping of described the first message;
Described clock equipment sends the second message that carries described the first hardware timestamping to described distribution terminal, described message comprises described the second message.
In the present embodiment, described the first message and described the second message are described message.
Like this, described clock equipment is when sending to the first message, and the timestamp unit of described clock equipment can obtain the first hardware timestamping while sending described the first message.In addition, described distribution terminal is when receiving the first message, and the timestamp unit of described distribution terminal can obtain the second hardware timestamping while receiving described the first message.In addition, described distribution terminal is when receiving the second message, and described distribution terminal can extract described the first hardware timestamping from described the second message receiving.Thereby, according to described the first hardware timestamping and described the second hardware timestamping, generating the main model in path delay of joining, described master joins path delay model and comprises:
td＝(t2+ts)-t1 （1），
Wherein, described td is described communication delay, and described t2 is described the second hardware timestamping, and described ts is that described synchronised clock is poor, and described t1 is described the first hardware timestamping.
In like manner, as one embodiment of the invention, described step S11 also comprises:
Described distribution terminal sends the 3rd hardware timestamping of described the 3rd message described the 3rd message of record transmission to described clock equipment, described clock equipment record receives the 4th hardware timestamping of described the 3rd message;
Described clock equipment sends the 4th message that carries described the 4th hardware timestamping to described distribution terminal, described message comprises described the 4th message.
In the present embodiment, described the 3rd message and described the 4th message are described message.
Like this, described distribution terminal is when sending to the 3rd message, and the timestamp unit of described distribution terminal can obtain the 3rd hardware timestamping while sending described the 3rd message.In addition, described clock equipment is when receiving the 3rd message, and the timestamp unit of described clock equipment can obtain the 4th hardware timestamping while receiving described the 3rd message.Then, described distribution terminal is when receiving the 4th message of described clock equipment feedback, and described distribution terminal can extract described the 4th hardware timestamping from described the 4th message receiving.Thereby, according to described the 4th hardware timestamping and described the 3rd hardware timestamping, generate and to join main path delay model, described in join main path delay model and comprise:
td＝t4-(t3+ts) （2），
Wherein, described t4 is described the 4th hardware timestamping, and described t3 is described the 3rd hardware timestamping.
Step S12, described distribution terminal, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, determines that the synchronised clock of the clock of described distribution terminal and the clock of described clock equipment is poor.
In the present embodiment, distinct interaction flow process for message between described clock equipment and described distribution terminal, determine described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and the 4th order of hardware timestamping and the time point of representative, poor (for the clock of adjusting described distribution terminal to follow the clock of described clock equipment further to calculate the synchronised clock of the clock of described distribution terminal and the clock of described clock equipment, realize the clock of described distribution terminal and the clock synchronous of described clock equipment).
Preferably, described step S12 is:
Described distribution terminal is processed described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping according to communication delay model, determines communication delay, and described communication delay model is:
Wherein, described t1 is described the first hardware timestamping, and described t2 is described the second hardware timestamping, and described t3 is described the 3rd hardware timestamping, and described t4 is described the 4th hardware timestamping, and described td is described communication delay;
Described distribution terminal generates the first synchronised clock differential mode type according to described the first hardware timestamping, described the second hardware timestamping and described communication delay, according to described the 3rd hardware timestamping, described the 4th hardware timestamping and described communication delay, generate the second synchronised clock differential mode type, according to described the first synchronised clock differential mode type or described the second synchronised clock differential mode type, calculate described synchronised clock poor
Described the first synchronised clock differential mode type is: ts=td-(t2-t1) (4),
Described the second synchronised clock differential mode type is: ts=(t4-t3)-td(5),
Wherein, described ts is that described synchronised clock is poor.
Like this, (1) and (2) be added and carry out corresponding mathematic(al) manipulation, obtaining (3).Then, (1) or (2) is carried out to mathematic(al) manipulation, obtain (4) or (5), then by value substitution (4) or (5) of the td obtaining in (3), obtain the poor ts of described synchronised clock.
Step S13, described distribution terminal according to the clock of the described distribution terminal of the poor correction of described synchronised clock with the clock synchronous with described clock equipment.
Like this, the circuit that comprises clock synchronous control loop of described distribution terminal is according to the clock of the described distribution terminal of the poor adjustment of described synchronised clock, realizes the clock of clock equipment described in the time clock tracking of described distribution terminal to realize clock synchronous.By that analogy, realize the clock of clock equipment described in the time clock tracking of each distribution terminal to realize clock synchronous, be convenient between clock equipment and each distribution terminal or each distribution terminal carries out data each other synchronizes reception (to guarantee the correct reception of the data after clock synchronous).
embodiment bis-:
Fig. 2 shows the system architecture of the clock system of the first distribution terminal that second embodiment of the invention provides, and for convenience of description, only shows the part relevant to the embodiment of the present invention.It should be noted that, the clock synchronizing method of the distribution terminal that the clock system of the distribution terminal that embodiment bis-provides and embodiment mono-provide is mutually applicable.
A clock system for distribution terminal, the clock system of described distribution terminal comprises:
Described distribution terminal 2, when described clock equipment 1 sends the first message to described distribution terminal 2, receive the first hardware timestamping and obtain the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment 1 is obtained the hardware timestamping while sending described the first message, when described distribution terminal 2 sends described the 3rd message to described clock equipment 1, obtain the 3rd hardware timestamping while sending described the 3rd message and receive the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment 1 is obtained the hardware timestamping while receiving described the 3rd message, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, the synchronised clock of determining the clock of described distribution terminal 2 and the clock of described clock equipment 1 is poor, according to the clock of the described distribution terminal 2 of the poor correction of described synchronised clock with the clock synchronous with described clock equipment 1.
As one embodiment of the invention, described clock equipment 1, also for send the first hardware timestamping that described the first message record send described the first message to described distribution terminal 2, to described distribution terminal 2, send the second message that carries described the first hardware timestamping, described message comprises described the first message and described the second message.
Described distribution terminal 2, also, for receiving the second hardware timestamping of described the first message described the first message of record reception, receives described the second message to extract described the first hardware timestamping.
As one embodiment of the invention, described distribution terminal 2, also for send the 3rd hardware timestamping that described the 3rd message record send described the 3rd message to described clock equipment 1, receive the 4th message to extract described the 4th hardware timestamping, described message comprises described the 3rd message and described the 4th message;
Described clock equipment 1, also, for receiving the 4th hardware timestamping of described the 3rd message described the 3rd message of record reception, sends to described distribution terminal 2 described the 4th message that carries described the 4th hardware timestamping.
Preferably, described distribution terminal 2, also, for process described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping according to communication delay model, determine communication delay, described communication delay model is:
Wherein, described t1 is described the first hardware timestamping, and described t2 is described the second hardware timestamping, and described t3 is described the 3rd hardware timestamping, and described t4 is described the 4th hardware timestamping, and described td is described communication delay;
Described distribution terminal 2, also for generating the first synchronised clock differential mode type according to described the first hardware timestamping, described the second hardware timestamping and described communication delay, according to described the 3rd hardware timestamping, described the 4th hardware timestamping and described communication delay, generate the second synchronised clock differential mode type, according to described the first synchronised clock differential mode type or described the second synchronised clock differential mode type, calculate described synchronised clock poor
Described the first synchronised clock differential mode type is: ts=td-(t2-t1),
Described the second synchronised clock differential mode type is: ts=(t4-t3)-td,
Wherein, described ts is that described synchronised clock is poor.
In embodiments of the present invention, clock equipment and distribution terminal carry out message interaction, simultaneously, described clock equipment is obtained the first hardware timestamping and the 4th hardware timestamping, described distribution terminal obtains the second hardware timestamping and the 3rd hardware timestamping, then according to communication delay model, to calculate communication delay poor further to calculate synchronised clock according to the first synchronised clock differential mode type or the second synchronised clock differential mode type for distribution terminal, and according to the clock of the poor adjustment distribution terminal of described synchronised clock with the clock synchronous with described clock equipment; Thereby, guarantee between clock equipment and distribution terminal or the correct reception of each distribution terminal interaction data each other.
It will be appreciated by those skilled in the art that the unit that comprises for above-described embodiment two is just divided according to function logic, but be not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit also, just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
Those of ordinary skills it is also understood that, the all or part of step realizing in above-described embodiment method is to come the hardware that instruction is relevant to complete by program, described program can be in being stored in a computer read/write memory medium, described storage medium, comprises ROM/RAM, disk, CD etc.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention; make without departing from the inventive concept of the premise some alternative or obvious modification that are equal to; and performance or purposes identical, all should be considered as belonging to the present invention by the definite scope of patent protection of submitted to claims.
Claims (8)
1. a clock synchronizing method for distribution terminal, is characterized in that, the clock synchronizing method of described distribution terminal comprises:
S11, when clock equipment sends the first message to distribution terminal, described distribution terminal receives the first hardware timestamping and obtains the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment is obtained the hardware timestamping while sending described the first message, when described distribution terminal sends described the 3rd message to described clock equipment, described distribution terminal obtains the 3rd hardware timestamping while sending described the 3rd message and receives the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment is obtained the hardware timestamping while receiving described the 3rd message,
S12, described distribution terminal, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, determines that the synchronised clock of the clock of described distribution terminal and the clock of described clock equipment is poor;
S13, described distribution terminal according to the clock of the described distribution terminal of the poor correction of described synchronised clock with the clock synchronous with described clock equipment.
2. the clock synchronizing method of distribution terminal as claimed in claim 1, is characterized in that, described step S11 also comprises:
Described clock equipment sends the first hardware timestamping of described the first message described the first message of record transmission to described distribution terminal, described distribution terminal record receives the second hardware timestamping of described the first message;
Described clock equipment sends the second message that carries described the first hardware timestamping to described distribution terminal.
3. the clock synchronizing method of distribution terminal as claimed in claim 2, is characterized in that, described step S11 also comprises:
Described distribution terminal sends the 3rd hardware timestamping of described the 3rd message described the 3rd message of record transmission to described clock equipment, described clock equipment record receives the 4th hardware timestamping of described the 3rd message;
Described clock equipment sends the 4th message that carries described the 4th hardware timestamping to described distribution terminal.
4. the clock synchronizing method of the distribution terminal as described in as arbitrary in claims 1 to 3, described step S12, is specially:
Described distribution terminal is processed described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping according to communication delay model, determines communication delay, and described communication delay model is:
Wherein, described t1 is described the first hardware timestamping, and described t2 is described the second hardware timestamping, and described t3 is described the 3rd hardware timestamping, and described t4 is described the 4th hardware timestamping, and described td is described communication delay;
Described distribution terminal generates the first synchronised clock differential mode type according to described the first hardware timestamping, described the second hardware timestamping and described communication delay, according to described the 3rd hardware timestamping, described the 4th hardware timestamping and described communication delay, generate the second synchronised clock differential mode type, according to described the first synchronised clock differential mode type or described the second synchronised clock differential mode type, calculate described synchronised clock poor
Described the first synchronised clock differential mode type is: ts=td-(t2-t1),
Described the second synchronised clock differential mode type is: ts=(t4-t3)-td,
Wherein, described ts is that described synchronised clock is poor.
5. a clock system for distribution terminal, is characterized in that, the clock system of described distribution terminal comprises:
Clock equipment, and one or more distribution terminal;
Described distribution terminal, when described clock equipment sends the first message to described distribution terminal, receive the first hardware timestamping and obtain the second hardware timestamping while receiving described the first message, described the first hardware timestamping is that described clock equipment is obtained the hardware timestamping while sending described the first message, when described distribution terminal sends described the 3rd message to described clock equipment, obtain the 3rd hardware timestamping while sending described the 3rd message and receive the 4th hardware timestamping, described the 4th hardware timestamping is that described clock equipment is obtained the hardware timestamping while receiving described the 3rd message, according to described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping, the synchronised clock of determining the clock of described distribution terminal and the clock of described clock equipment is poor, according to the clock of the described distribution terminal of the poor correction of described synchronised clock with the clock synchronous with described clock equipment.
6. the clock system of distribution terminal as claimed in claim 5, is characterized in that,
Described clock equipment, also, for send the first hardware timestamping of described the first message described the first message of record transmission to described distribution terminal, sends the second message that carries described the first hardware timestamping to described distribution terminal.
Described distribution terminal, also, for receiving the second hardware timestamping of described the first message described the first message of record reception, receives described the second message to extract described the first hardware timestamping.
7. the clock system of distribution terminal as claimed in claim 6, is characterized in that,
Described distribution terminal, also, for send the 3rd hardware timestamping of described the 3rd message described the 3rd message of record transmission to described clock equipment, receives the 4th message to extract described the 4th hardware timestamping;
Described clock equipment, also, for receiving the 4th hardware timestamping of described the 3rd message described the 3rd message of record reception, sends described the 4th message that carries described the 4th hardware timestamping to described distribution terminal.
8. the clock system of the distribution terminal as described in as arbitrary in claim 5 to 7, is characterized in that,
Described distribution terminal, also, for process described the first hardware timestamping, described the second hardware timestamping, described the 3rd hardware timestamping and described the 4th hardware timestamping according to communication delay model, determines communication delay, and described communication delay model is:
Wherein, described t1 is described the first hardware timestamping, and described t2 is described the second hardware timestamping, and described t3 is described the 3rd hardware timestamping, and described t4 is described the 4th hardware timestamping, and described td is described communication delay;
Described distribution terminal, also for according to described the first hardware timestamping, described the second hardware timestamping and described communication delay generate the first synchronised clock differential mode type, according to described the 3rd hardware timestamping, described the 4th hardware timestamping and described communication delay generate the second synchronised clock differential mode type, according to described the first synchronised clock differential mode type or described the second synchronised clock differential mode type, calculate described synchronised clock poor, described the first synchronised clock differential mode type is: ts=td-(t2-t1), described the second synchronised clock differential mode type is: ts=(t4-t3)-td, wherein, described ts is that described synchronised clock is poor.
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