CN115865079B - High-precision phase difference measuring device and method for main clock link and standby clock link - Google Patents
High-precision phase difference measuring device and method for main clock link and standby clock link Download PDFInfo
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Abstract
The invention discloses a device and a method for measuring high-precision phase difference of a main clock link and a standby clock link, which are applied to the technical field of communication and comprise the following steps: reference signal common oscillator: a phase difference measurement module for providing a common reference frequency signal, the same primary clock signal and the same standby clock signal for a hybrid phase detector, comprising: mixing phase detector: the phase-comparison circuit is used for carrying out frequency mixing phase-demodulation on the clock signal to obtain a phase-comparison signal; an analog-to-digital converter: for converting the phase ratio signal into a digital signal; digital phase measurement analysis module: the high-frequency sampling is used for the digital signal, and phase difference value calculation is carried out; the main and standby signal phase difference output module: and the phase difference value measuring module is used for outputting the phase difference of the main and standby signals according to the phase difference values output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module. The invention improves the measurement resolution, enhances the anti-noise interference capability of measurement and ensures the measurement accuracy of the phase difference.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a device and a method for measuring a high-precision phase difference of a main clock link and a standby clock link.
Background
The redundancy backup of the satellite clock reference signals is mainly realized by a method that two paths of mutually independent reference frequency signals are mutually hot backups. Under normal conditions, the system mainly depends on a working reference frequency source, is automatically switched to a hot backup reference frequency source when necessary, and performs a main-standby parallel operation mode for the two systems and performs signal crossing comparison. In order to ensure the continuity and integrity of the reference frequency signal, two sets of systems must be monitored in real time, and when detecting that the system changes beyond a preset threshold value, the source of the change is judged, the normal operation system is automatically switched, and an alarm signal is generated. The difficulty of the satellite hot standby reference clock stable switching technology is mainly that the high-precision synchronization method of the main and standby clock reference signals and how to achieve the consistency of the phase and frequency of the system output frequency signals before and after switching.
In order to ensure that the frequency and phase consistency index of the main and standby links of the clock can meet the system requirement, the frequency and phase deviation of the main and standby links needs to be measured with high resolution and low noise, so that the stability, reliability and continuity of the output clock frequency signal are ensured. The common phase comparison method is to condition the two compared signals first, and then obtain phase-discriminating pulse after passing through a phase discriminator, namely phase-difference pulse width. And then the switch door of the counter is controlled by the phase discrimination pulse, and the pulse width of the phase difference is filled by the high-frequency clock pulse to measure the phase difference value. The counter takes the rising edge or the falling edge of the phase discrimination pulse signal as a trigger signal, so that the counting error of +/-1 clock pulse exists in the measurement by the method, and the measurement resolution depends on the period of the clock pulse.
Therefore, how to provide a device and a method for measuring the phase difference of the master clock link and the slave clock link with high accuracy, which can measure the frequency and the phase deviation of the master clock and the slave clock with high resolution and low noise, so as to ensure the stability, the reliability and the continuity of the output clock frequency signal is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a device and a method for measuring a high-precision phase difference of a main clock link and a standby clock link.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a high-precision phase difference measuring device of a main clock link and a standby clock link comprises: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module are the same, and the main clock signal phase difference value measuring module comprises:
mixing phase detector: the phase-comparison circuit is used for carrying out frequency mixing phase-demodulation on the clock signal to obtain a phase-comparison signal;
an analog-to-digital converter: for converting the phase ratio signal into a digital signal;
digital phase measurement analysis module: the method comprises the steps of performing high-frequency sampling for digital signals, and performing phase difference value calculation;
reference signal common oscillator: for providing a common reference frequency signal for the mixed phase detector;
the main and standby signal phase difference output module: and the phase difference value measuring module is used for outputting the phase difference of the main and standby signals according to the phase difference values output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module.
Optionally, the digital direction finding analysis module includes: a digital phase-locked loop (PLL), a digital sampling clock generator and a phase measurement output module;
a digital phase locked loop, PLL, comprising: the multiplier, the integral zero clearing device, the phase discriminator, the low-pass filter and the digital frequency synthesizer DDS are connected in sequence;
multiplier: for multiplying down-conversion of digital sinusoidal signals;
an integrator clearer for outputting an output signal in proportion to a time integral value of an input signal;
phase detector: phase discrimination for two digital sine multiplied signals;
a low pass filter: loop low pass filtering for the integrated signal;
digital frequency synthesizer DDS: for converting the digital low-pass filtered output value to a reference frequency output;
digital sampling clock generator: the sampling clock is used for generating a sampling clock with non-integer frequency from an input sampling clock signal and acts on the working clock of the digital phase-locked loop PLL;
and the phase measurement output module is used for: and the phase difference value measuring unit is used for measuring and outputting the phase difference value of the second pulse signal PPS and the output signal of the digital phase-locked loop PLL.
Optionally, the phase difference of the primary and the secondary signals is the difference between the phase difference values output by the primary clock signal phase difference value measuring module and the secondary clock signal phase difference value measuring module.
Optionally, the digital phase measurement analysis module and the primary and secondary signal phase difference output module are both stored in a computer.
The invention also provides a method for applying the device for measuring the high-precision phase difference of the main clock link and the standby clock link, which comprises the following steps:
step (1): based on a common reference frequency signal provided by a reference signal common oscillator, respectively carrying out frequency mixing phase discrimination on a main clock signal and a standby clock signal through a frequency mixing phase discriminator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): converting the main phase comparison signal and the standby phase comparison signal into digital signals through an analog-to-digital converter respectively, and inputting the digital signals to a digital phase measurement analysis module respectively for calculating a phase difference value;
step (3): the main and standby signal phase difference output module outputs a main and standby signal phase difference according to the phase difference value of the main clock signal and the standby clock signal.
Optionally, the digital phase measurement analysis module performs phase difference value calculation, specifically:
and if the main link is A and the standby link is B, sampling signals of A and B are respectively:
d A (n)＝Asin(θ)，d A (n-1)＝Asin(θ-φ)；
d B (n)＝B sin(θ+Δθ)，d B (n-1)＝B sin(θ+Δθ-φ)；
the phase difference measurement results were:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2AB sin(φ)sin(θ)；
design timeApproaching 90 degrees, d (Δθ) ≡2ab·θ.
Optionally, the phase difference of the primary and secondary signals is the difference between the phase differences of the primary and secondary clock signals.
Optionally, the phase difference calculation and the primary and secondary signal phase difference calculation are all completed on a computer.
Compared with the prior art, the invention provides the device and the method for measuring the phase difference of the main clock link and the standby clock link with high precision. By designing a common oscillator to be used for phase discrimination with two signal sources needing to measure phase difference respectively, the obtained two phase differences can counteract the influence of the common oscillator through subtraction, so that the phase difference value of the two signal sources is obtained. Wherein, the measurement of the two phase differences and the subtraction process are completed in a computer after being converted into digital signals through an analog/digital device. The phase discrimination processing with the common oscillator can reduce the frequency of a signal source, which is equivalent to amplifying the phase difference of two signals, and improves the measurement resolution, and the phase noise introduced by the common oscillator can be counteracted by the double-balanced structural design. And the digital signal processing is used for replacing the phase difference measurement solution of the traditional counter, the signals output by the phase discriminator are sampled at a high sampling rate, the phase difference value is calculated, the functions of the traditional zero-crossing detection circuit and the counter are replaced, the anti-noise interference capability of measurement is enhanced, and the measurement accuracy of the phase difference is ensured.
Compared with the prior art, the invention has the following advantages:
the measurement bandwidth is greatly shrunk, and the measurement accuracy is greatly improved. After the phase measured by the narrowband tracking loop is used, the phase noise depends on the loop bandwidth,wherein P is 10M (f) Is the noise power spectral density; b (B) L For the loop bandwidth, the narrower the loop bandwidth is, the higher the phase measurement accuracy is, for example, the 10MHz reference clock signal is, and when the loop bandwidth is taken as 1KHz, the measurement accuracy can reach within 50 ps.
The stability is good, and the clock edge judgment problem is avoided. The ADC only performs hard-touch sampling action, the following phase locking algorithm is very simple, and no judging action statement such as if, else, then is adopted, so that the stability is higher than that of an analog phase comparison method by more than 1 order of magnitude.
The anti-interference is strong. Has very strong resistance to disturbances and glitches on the clock signal. When the clock signal is interfered, the burr occurs, other measuring methods can cause measuring errors or malfunction, and the invention does not have the problem, which is the advantage of the loop bandwidth of the narrow phase-locked loop. The requirements for waveforms are greatly reduced and can operate at very low signal to noise ratios.
The temperature drift is small. The analog-to-digital converter ADC directly samples, and the problem of a shaping circuit is avoided. There is no zero crossing problem and no amplitude variation causes duty cycle variation problem.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of the structure of the device of the present invention.
Fig. 2 is a schematic diagram of a digital phase measurement analysis module according to the present invention.
FIG. 3 is a schematic flow chart of the method of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1:
the embodiment 1 of the invention discloses a high-precision phase difference measuring device of a main clock link and a standby clock link, which is shown in fig. 1 and comprises the following components: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module are the same, and the main clock signal phase difference value measuring module comprises:
mixing phase detector: the phase-comparison circuit is used for carrying out frequency mixing phase-demodulation on the clock signal to obtain a phase-comparison signal;
an analog-to-digital converter: for converting the phase ratio signal into a digital signal;
the digital phase measurement analysis module is stored in a computer: for high frequency sampling of digital signals, phase difference calculation, as shown in fig. 2, includes: a digital phase-locked loop (PLL), a digital sampling clock generator and a phase measurement output module;
a digital phase locked loop, PLL, comprising: the multiplier, the integral zero clearing device, the phase discriminator, the low-pass filter and the digital frequency synthesizer DDS are connected in sequence;
multiplier: for multiplying down-conversion of digital sinusoidal signals;
an integrator clearer for outputting an output signal in proportion to a time integral value of an input signal;
phase detector: phase discrimination for two digital sine multiplied signals;
a low pass filter: loop low pass filtering for the integrated signal;
digital frequency synthesizer DDS: for converting the digital low-pass filtered output value to a reference frequency output;
digital sampling clock generator: the sampling clock is used for generating a sampling clock with non-integer frequency from an input sampling clock signal and acts on the working clock of the digital phase-locked loop PLL;
and the phase measurement output module is used for: the phase difference value measuring device is used for measuring and outputting a second pulse signal PPS and an output signal of the digital phase-locked loop PLL;
reference signal common oscillator: for providing a common reference frequency signal for the mixed phase detector;
the main and standby signal phase difference output module is stored in a computer: and the phase difference of the main and standby signals is output according to the difference of the phase differences output by the main clock signal phase difference measuring module and the standby clock signal phase difference measuring module.
Example 2:
the embodiment 2 of the invention discloses a method for measuring satellite communication distance by using the high-precision phase difference measuring device of the main clock link and the standby clock link of the embodiment 1, which comprises the following specific results:
an important function of satellite communication ranging is to measure the clock face time of the satellite and the clock face time difference of the communication transceiver. If the time difference is not measured, the measurement cannot be used directly for time difference and autonomous orbit determination. Although the communication transceiver is homologous to the satellite time system, the sine wave sent by the reference clock is used as a reference, for example, the 10MHz signal period corresponds to 100ns precision. For accurate time-synchronized measurements, the accuracy is still insufficient and further measurements according to the accuracy are required.
By applying the high-precision phase difference measuring device for the main and standby clock links of the embodiment 1 of the invention to measure the phase of the reference signal sent to the communication transceiver and the phase of the local clock signal of the communication transceiver, the precision reaches the order of 10 ps.
Example 3:
the embodiment 3 of the invention discloses a method for applying the high-precision phase difference measuring device of the main clock link and the standby clock link of the embodiment 1, which is shown in fig. 3 and comprises the following steps:
step (1): based on a common reference frequency signal provided by a reference signal common oscillator, respectively carrying out frequency mixing phase discrimination on a main clock signal and a standby clock signal through a frequency mixing phase discriminator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): the main phase comparison signal and the standby phase comparison signal are respectively converted into digital signals through an analog-to-digital converter, and are respectively input into a digital phase measurement analysis module on a computer to calculate a phase difference value, wherein the phase difference value is specifically as follows:
and if the main link is A and the standby link is B, sampling signals of A and B are respectively:
d A (n)＝Asin(θ)，d A (n-1)＝Asin(θ-φ)；
d B (n)＝B sin(θ+Δθ)，d B (n-1)＝B sin(θ+Δθ-φ)；
the phase difference measurement results were:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2AB sin(φ)sin(θ)；
design timeApproaching 90 degrees, d (Δθ) ≡2ab·θ.
Calculating a phase difference value by using a signal output by the phase discriminator with a high sampling rate, and ensuring the measurement accuracy of the phase difference;
when the sampling signal clock is 10MHz and the sampling bit number is 14, phase discrimination is carried outThe accuracy can reach d (delta theta) =1/(10×10) 6 )/(2^14)＝6.1ps。
Step (3): a main and standby signal phase difference output module on the computer outputs a main and standby signal phase difference according to the difference of the phase difference values of the main clock signal and the standby clock signal.
The embodiment of the invention discloses a device and a method for measuring a high-precision phase difference of a main clock link and a standby clock link. By designing a common oscillator to be used for phase discrimination with two signal sources needing to measure phase difference respectively, the obtained two phase differences can counteract the influence of the common oscillator through subtraction, so that the phase difference value of the two signal sources is obtained. Wherein, the measurement of the two phase differences and the subtraction process are completed in a computer after being converted into digital signals through an analog/digital device. The phase discrimination processing with the common oscillator can reduce the frequency of a signal source, which is equivalent to amplifying the phase difference of two signals, and improves the measurement resolution, and the phase noise introduced by the common oscillator can be counteracted by the double-balanced structural design. And the digital signal processing is used for replacing the phase difference measurement solution of the traditional counter, the signals output by the phase discriminator are sampled at a high sampling rate, the phase difference value is calculated, the functions of the traditional zero-crossing detection circuit and the counter are replaced, the anti-noise interference capability of measurement is enhanced, and the measurement accuracy of the phase difference is ensured.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. The utility model provides a master and slave clock link high accuracy phase difference measuring device which characterized in that includes: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the primary clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module are the same, and the primary clock signal phase difference value measuring module comprises:
mixing phase detector: the phase-comparison circuit is used for carrying out frequency mixing phase-demodulation on the clock signal to obtain a phase-comparison signal;
an analog-to-digital converter: for converting the phase ratio signal into a digital signal;
digital phase measurement analysis module: the high-frequency sampling is used for the digital signal, and phase difference value calculation is carried out;
the reference signal common oscillator: for providing a common reference frequency signal for said mixed phase detector;
the master-slave signal phase difference output module is: the phase difference measuring module is used for outputting a main and standby signal phase difference according to the phase difference value output by the main clock signal phase difference measuring module and the standby clock signal phase difference measuring module;
the digital phase measurement analysis module comprises: a digital phase-locked loop (PLL), a digital sampling clock generator and a phase measurement output module;
the digital phase locked loop PLL comprises: the multiplier, the integral zero clearing device, the phase discriminator, the low-pass filter and the digital frequency synthesizer DDS are connected in sequence;
the multiplier: for multiplying down-conversion of digital sinusoidal signals;
the integral clearer is used for outputting an output signal in proportion to a time integral value of an input signal;
the phase detector: phase discrimination for two digital sine multiplied signals;
the low pass filter: loop low pass filtering for the integrated signal;
the digital frequency synthesizer DDS: for converting the digital low-pass filtered output value to a reference frequency output;
the digital sampling clock generator: the sampling clock is used for generating a sampling clock with non-integer frequency from an input sampling clock signal and acts on the working clock of the digital phase-locked loop PLL;
the phase measurement output module: and the phase difference value measuring unit is used for measuring and outputting a second pulse signal PPS and an output signal of the digital phase-locked loop PLL.
2. The device for measuring the phase difference of the master clock link and the slave clock link with high precision according to claim 1, wherein the phase difference of the master clock signal and the slave clock signal is the difference between the phase differences output by the master clock signal and the slave clock signal.
3. The device for measuring the phase difference of the master clock link and the slave clock link with high precision according to claim 1, wherein the digital phase measurement analysis module and the master signal phase difference output module are both stored in a computer.
4. A method of using a master-slave clock link high accuracy phase difference measurement apparatus as claimed in any one of claims 1 to 3, comprising:
step (1): based on a common reference frequency signal provided by a reference signal common oscillator, respectively carrying out frequency mixing phase discrimination on a main clock signal and a standby clock signal through a frequency mixing phase discriminator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): the main phase comparison signal and the standby phase comparison signal are respectively converted into digital signals through an analog-to-digital converter, and are respectively input into a digital phase measurement analysis module to calculate a phase difference value;
step (3): and the main and standby signal phase difference output module outputs a main and standby signal phase difference according to the phase difference value of the main clock signal and the standby clock signal.
5. A method according to claim 4, wherein the digital phase measurement analysis module performs phase difference calculation, specifically:
and if the main link is A and the standby link is B, sampling signals of A and B are respectively:
d A (n)＝A sin(θ)，d A (n-1)＝A sin(θ-φ)；
d B (n)＝B sin(θ+Δθ)，d B (n-1)＝B sin(θ+Δθ-φ)；
the phase difference measurement results were:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2AB sin(φ)sin(θ)
design timeNear 90 degrees, d (Δθ) ≡2ab·θ.
6. A method according to claim 4, applied to a device for measuring the phase difference of a master clock link and a slave clock link with high accuracy according to any one of claims 1 to 3, wherein the phase difference of the master clock signal and the slave clock signal is the difference between the phase differences of the master clock signal and the slave clock signal.
7. A method according to claim 4, wherein the phase difference calculation and the phase difference calculation of the master and slave signals are performed on a computer.
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| CN101820340A (en) * | 2010-02-22 | 2010-09-01 | 中兴通讯股份有限公司 | Clock recovery device and method |
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| CN101162959B (en) * | 2007-10-19 | 2011-08-24 | 中兴通讯股份有限公司 | Clock master-slave phase difference automatic measurement and compensation process |
| EP2944975B1 (en) * | 2014-05-14 | 2018-04-04 | Elmos Semiconductor Aktiengesellschaft | Device for measuring a changing physical parameter, such as pressure |
| CN107247181B (en) * | 2017-04-24 | 2019-09-03 | 西安电子科技大学 | A kind of digitization frequencies stable measurement method of total reponse time |
| CN109211414B (en) * | 2018-07-13 | 2020-10-16 | 华东师范大学 | Ultrahigh-precision optical frequency tester and testing method thereof |
| CN112014640A (en) * | 2020-09-03 | 2020-12-01 | 中国计量科学研究院 | Multi-channel frequency standard comparison test system and working method thereof |
| CN214503748U (en) * | 2021-03-30 | 2021-10-26 | 北京跟踪与通信技术研究所 | Frequency scale comparison device |
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| CN101820340A (en) * | 2010-02-22 | 2010-09-01 | 中兴通讯股份有限公司 | Clock recovery device and method |
| CN107483050A (en) * | 2017-07-12 | 2017-12-15 | 西安空间无线电技术研究所 | A kind of steady switching system of atomic clock based on real time technique for tracking |
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