CN104980245A - Redundancy protection output apparatus and method of frequency timing output signal of synchronized clock equipment - Google Patents
Redundancy protection output apparatus and method of frequency timing output signal of synchronized clock equipment Download PDFInfo
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- CN104980245A CN104980245A CN201510377334.5A CN201510377334A CN104980245A CN 104980245 A CN104980245 A CN 104980245A CN 201510377334 A CN201510377334 A CN 201510377334A CN 104980245 A CN104980245 A CN 104980245A
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Abstract
The invention discloses a redundancy protection output apparatus and method of a frequency timing output signal of synchronized clock equipment. The apparatus comprises a common unit module, a primary timing output module, and a standby timing output module. The primary timing output module and the standby timing output module receive a reference frequency signal and a reference phase signal from the common unit module jointly; and after phase-locked loops lock the reference frequency signal, a clock signal is outputted to a logic chip. When phase-locked loops of the primary timing output module and the standby timing output module works stably, the primary timing output module and the standby timing output module enable initial phases of outputted timing signals to be aligned at that of the reference phase signal of the common unit module, so that the same-frequency same-phase phenomenon of the timing signals of the primary module and the standby module is realized. Therefore, primary-standby redundancy protection of timing output signals can be realized and the phase incontinuity requirement can be met.
Description
[technical field]
The invention belongs to the communications field, be specifically related to a kind of synchronous clock equipment frequency timing output signal redundancy protecting output device and method.
[background technology]
China's SNC synchronous network clock equipment is divided into one-level reference clock equipment, two-level node clockwork, three grades of nodal clock equipment.Synchronous clock equipment output signal has 1MHz, 5MHz, 10MHz signal and 2048kb/s signal and 2048kHz signal usually.According to People's Republic of China's communication industry standard " YD/T 1479-2006 one-level reference clock equipment and technology requires and method of testing " 6.4 joint and " YD/T 1011-1999 digital synchronous network self node requires and method of testing from clock equipment and technology " technical requirement that 4.3.1 saves, equipment timing output signal should be able to redundant configuration.The timing output signal of redundant configuration forms main-apparatus protection relation, primary timing output signal and standby timing output signal received by user's distributing frame together with form timing output signal.When primary timing output signal breaks down, timing exports will be switched to timing output signal for subsequent use, in handoff procedure, it is discontinuous that timing output signal there will be phase place, according to the technical requirement of " YD/T 1012-1999 digital synchronous network nodal clock series and Timing characteristics thereof " 4.1.3 joint, the phase discontinuity of 2048kb/s signal and 2048kHz signal can not more than 1/8UI, i.e. 61ns, otherwise rear end equipment may be caused to occur the situation of slip frame losing, and then affect the normal operation of whole communication system.
[summary of the invention]
The object of the invention is to overcome above-mentioned deficiency, a kind of synchronous clock equipment frequency timing output signal redundancy protecting output device and method are provided, the master-slave redundancy protection of timing output signal can be realized, also meet phase discontinuity requirement simultaneously.
In order to achieve the above object; synchronous clock equipment frequency timing output signal redundancy protecting output device; comprise common unit module, primary timing output module and timing output module for subsequent use; common unit module all provides reference frequency signal and reference phase signal can to primary timing output module and timing output module for subsequent use; common unit module provides primary ID signal and ID signal for subsequent use also to respectively primary timing output module and timing output module for subsequent use, and primary timing output module and timing output module for subsequent use can swap datas.
Described primary timing output module is identical with the principle of timing output module for subsequent use, can exchange in logic.
Described reference frequency signal and reference phase signal are from same frequency source.
Described timing output module output interface realizes opening/closing timing output function by MAX4652 or MAX4592 electronic switch.
Synchronous clock equipment frequency timing output signal redundancy protecting output intent, comprises the following steps:
Step one: reference frequency signal and reference phase signal are all supplied to primary timing output module and timing output module for subsequent use by common unit module, primary ID signal and ID signal for subsequent use are also supplied to primary timing output module and timing output module for subsequent use by common unit module at random;
Step 2: when primary timing output module or timing output module for subsequent use receive the primary ID signal of common unit module, the default conditions of timing output module power-up initializing are just master state, if receive ID signal for subsequent use, then the default conditions that power on are stand-by state;
Step 3: when primary timing output module or timing output module for subsequent use receive reference frequency signal or reference phase signal, after timing output module is started working, first phase-locked loop in timing output module locks reference frequency signal, after phase-locked loop operation is stable, export with the clock signal of reference frequency signal homology to logic chip, primary timing output module also needs the phase-locked loop operation state judging timing output module for subsequent use simultaneously, when after primary and backup module phase-locked loop all steady operation, a primary timing output module electricity consumption square formula notifies timing output module for subsequent use, the initial phase of the timing signal of output aligns with common unit module reference phase signal by primary timing output module and timing output module for subsequent use simultaneously, the timing signal of primary like this timing output module and timing output module for subsequent use just achieves with frequency homophase.
In described step 3, standby usage timing output module can according to the configuration information of common unit module, under being operated in the mode of operation of 1:1 or 1:0, when being operated under 1:0 pattern, primary timing output module and timing output module for subsequent use export timing signal simultaneously simultaneously.When being operated under 1:1 pattern, primary timing output module is opened and exports timing signal, and timing output module for subsequent use exports closes.
In described step 3, the phase-locked loop in timing output module selects 61.44MHz temperature compensating crystal oscillator.
In described step 3, adopt 61.44MHz clock signal with the clock signal of reference frequency signal homology.
In described step 3, primary timing output module and timing output module for subsequent use export 2048kb/s timing signal and 2048kHz timing signal respectively.
Compared with prior art, the present invention makes primary timing output module and timing output module for subsequent use jointly accept reference frequency signal and the reference phase signal of common unit module, after phase lock loop locks reference frequency signal, clock signal is to logic chip, when after primary timing output module and timing output module phase-locked loop for subsequent use all steady operation, the initial phase of the timing signal of output aligns with common unit module reference phase signal by primary timing output module and timing output module for subsequent use simultaneously, the timing signal of primary and backup like this module just achieves with frequency homophase, the master-slave redundancy protection of timing output signal can be realized like this, also meet phase discontinuity requirement simultaneously.
[accompanying drawing explanation]
Fig. 1 is the system block diagram of synchronous clock equipment frequency timing output signal redundancy protecting output device of the present invention.
[embodiment]
See Fig. 1; synchronous clock equipment frequency timing output signal redundancy protecting output device; comprise common unit module, primary timing output module and timing output module for subsequent use; common unit module all provides reference frequency signal and reference phase signal can to primary timing output module and timing output module for subsequent use; common unit module provides primary ID signal and ID signal for subsequent use also to respectively primary timing output module and timing output module for subsequent use, and primary timing output module and timing output module for subsequent use can swap datas.
Wherein, primary timing output module is identical with the principle of timing output module for subsequent use, can exchange in logic; Reference frequency signal and reference phase signal are from same frequency source; Timing output module output interface realizes opening/closing timing output function by MAX4652 or MAX4592 electronic switch.
Synchronous clock equipment frequency timing output signal redundancy protecting output intent, comprises the following steps:
Step one: reference frequency signal and reference phase signal are all supplied to primary timing output module and timing output module for subsequent use by common unit module, primary ID signal and ID signal for subsequent use are also supplied to primary timing output module and timing output module for subsequent use by common unit module at random;
Step 2: when primary timing output module or timing output module for subsequent use receive the primary ID signal of common unit module, the default conditions of timing output module power-up initializing are just master state, if receive ID signal for subsequent use, then the default conditions that power on are stand-by state;
Step 3: when primary timing output module or timing output module for subsequent use receive reference frequency signal or reference phase signal, timing output inside modules phase-locked loop selects 61.44MHz temperature compensating crystal oscillator, after timing output module is started working, first phase-locked loop in timing output module locks reference frequency signal, after phase-locked loop operation is stable, export with the 61.44MHz clock signal of reference frequency signal homology to logic chip, primary timing output module also needs the phase-locked loop operation state judging timing output module for subsequent use simultaneously, when after primary and backup module phase-locked loop all steady operation, a primary timing output module electricity consumption square formula notifies timing output module for subsequent use, the initial phase of the timing signal of output aligns with common unit module reference phase signal by primary timing output module and timing output module for subsequent use simultaneously, the timing signal of primary like this timing output module and timing output module for subsequent use just achieves with frequency homophase.Wherein, primary timing output module and timing output module for subsequent use export 2048kb/s timing signal and 2048kHz timing signal respectively.
In step 3, standby usage timing output module can according to the configuration information of common unit module, under being operated in the mode of operation of 1:1 or 1:0, when being operated under 1:0 pattern, primary timing output module and timing output module for subsequent use export timing signal simultaneously simultaneously.When being operated under 1:1 pattern, primary timing output module is opened and exports timing signal, and timing output module for subsequent use exports closes.
Claims (9)
1. synchronous clock equipment frequency timing output signal redundancy protecting output device; it is characterized in that; comprise common unit module, primary timing output module and timing output module for subsequent use; common unit module all provides reference frequency signal and reference phase signal can to primary timing output module and timing output module for subsequent use; common unit module provides primary ID signal and ID signal for subsequent use also to respectively primary timing output module and timing output module for subsequent use, and primary timing output module and timing output module for subsequent use can swap datas.
2. synchronous clock equipment frequency timing output signal redundancy protecting output device according to claim 1, it is characterized in that, described primary timing output module is identical with the principle of timing output module for subsequent use, can exchange in logic.
3. synchronous clock equipment frequency timing output signal redundancy protecting output device according to claim 1, it is characterized in that, described reference frequency signal and reference phase signal are from same frequency source.
4. synchronous clock equipment frequency timing output signal redundancy protecting output device according to claim 1; it is characterized in that, described timing output module output interface realizes opening/closing timing output function by MAX4652 or MAX4592 electronic switch.
5. synchronous clock equipment frequency timing output signal redundancy protecting output intent, is characterized in that, comprise the following steps:
Step one: reference frequency signal and reference phase signal are all supplied to primary timing output module and timing output module for subsequent use by common unit module, primary ID signal and ID signal for subsequent use are also supplied to primary timing output module and timing output module for subsequent use by common unit module at random;
Step 2: when primary timing output module or timing output module for subsequent use receive the primary ID signal of common unit module, the default conditions of timing output module power-up initializing are just master state, if receive ID signal for subsequent use, then the default conditions that power on are stand-by state;
Step 3: when primary timing output module or timing output module for subsequent use receive reference frequency signal or reference phase signal, after timing output module is started working, first phase-locked loop in timing output module locks reference frequency signal, after phase-locked loop operation is stable, export with the clock signal of reference frequency signal homology to logic chip, primary timing output module also needs the phase-locked loop operation state judging timing output module for subsequent use simultaneously, when after primary and backup module phase-locked loop all steady operation, a primary timing output module electricity consumption square formula notifies timing output module for subsequent use, the initial phase of the timing signal of output aligns with common unit module reference phase signal by primary timing output module and timing output module for subsequent use simultaneously, the timing signal of primary like this timing output module and timing output module for subsequent use just achieves with frequency homophase.
6. synchronous clock equipment frequency timing output signal redundancy protecting output intent according to claim 4; it is characterized in that; in described step 3; standby usage timing output module can according to the configuration information of common unit module; under being operated in the mode of operation of 1:1 or 1:0 simultaneously; when being operated under 1:0 pattern; primary timing output module and timing output module for subsequent use export timing signal simultaneously; when being operated under 1:1 pattern; primary timing output module is opened and exports timing signal, and timing output module for subsequent use exports closes.
7. synchronous clock equipment frequency timing output signal redundancy protecting output intent according to claim 4, it is characterized in that, in described step 3, the phase-locked loop in timing output module selects 61.44MHz temperature compensating crystal oscillator.
8. synchronous clock equipment frequency timing output signal redundancy protecting output intent according to claim 4, is characterized in that, in described step 3, adopt 61.44MHz clock signal with the clock signal of reference frequency signal homology.
9. synchronous clock equipment frequency timing output signal redundancy protecting output intent according to claim 4; it is characterized in that; in described step 3, primary timing output module and timing output module for subsequent use export 2048kb/s timing signal and 2048kHz timing signal respectively.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105185346A (en) * | 2015-10-23 | 2015-12-23 | 京东方科技集团股份有限公司 | Display device |
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| CN1674704A (en) * | 2005-05-19 | 2005-09-28 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| WO2006087264A1 (en) * | 2005-02-15 | 2006-08-24 | Alcatel Lucent | A synchronization system using redundant clock signals for equipment of a synchronous transport network |
| CN101162959A (en) * | 2007-10-19 | 2008-04-16 | 中兴通讯股份有限公司 | Clock master-slave phase difference automatic measurement and compensation process |
| CN101197650A (en) * | 2007-11-21 | 2008-06-11 | 上海华为技术有限公司 | Clock synchronization device and method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2006087264A1 (en) * | 2005-02-15 | 2006-08-24 | Alcatel Lucent | A synchronization system using redundant clock signals for equipment of a synchronous transport network |
| CN1674704A (en) * | 2005-05-19 | 2005-09-28 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| CN101162959A (en) * | 2007-10-19 | 2008-04-16 | 中兴通讯股份有限公司 | Clock master-slave phase difference automatic measurement and compensation process |
| CN101197650A (en) * | 2007-11-21 | 2008-06-11 | 上海华为技术有限公司 | Clock synchronization device and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185346A (en) * | 2015-10-23 | 2015-12-23 | 京东方科技集团股份有限公司 | Display device |
| US10115361B2 (en) | 2015-10-23 | 2018-10-30 | Boe Technology Group Co., Ltd. | Display device |
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Application publication date: 20151014 |