CN102684807A - Clock recovering method and device - Google Patents
Clock recovering method and device Download PDFInfo
- Publication number
- CN102684807A CN102684807A CN2012101589160A CN201210158916A CN102684807A CN 102684807 A CN102684807 A CN 102684807A CN 2012101589160 A CN2012101589160 A CN 2012101589160A CN 201210158916 A CN201210158916 A CN 201210158916A CN 102684807 A CN102684807 A CN 102684807A
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency
- clock information
- mentioned
- dds
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a clock recovering method and device. The method comprises the following steps of: when a DDS (Direct Digital Synthesizer) receives clock information of client data, calculating a storage address in the DDS of a wave shape signal corresponding to the clock information and reading the wave shape signal corresponding to the clock information according to the storage address; and performing phase discrimination processing on the successfully-read wave shape signal to generate a synchronous clock of the client data. The clock recovering method and device disclosed by the invention adjust phase through the DDS so as to restore the phase of the recovering clock, reduce the vibration during clock restore and improve the quality of the clock restore.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of clock recovery method and device.
Background technology
In OTN (Optical Transport Network, optical transfer network), clock is the soul of transmission, does not have correct clock, and transfer of data is not known where to begin.Therefore in the OTN transmission field, clock recovery is an important problem, and can from the transmission data, recover correct timing relationship correct transmission to data.
In the process of OTN transmission data, can run into low order ODUk (Optical Data Unit, light data cell) data map to high-order ODUj data, and then from high-order ODUj data, parse the process of low order ODUk data.When low order ODUk data map arrived high-order ODUj data, data can switch to the clock zone of a upper frequency from the clock zone of a lower frequency, and this will cause data discontinuous, increased the difficulty of clock recovery.
Fig. 1 is the clock recovery method flow chart of prior art.As shown in Figure 1, prior art is passed through FIFO (First In First Out, first in first out) the pending customer data of unit caches, and by cell fifo statistics data in buffer number datacount, inputs to decision unit then; Decision unit produces control signal UP and DOWN according to datacount, the synchronised clock of control VCO (Voltage-Controlled Oscillator, voltage controlled oscillator) output customer data.Method shown in Figure 1 can't keep the phase relation of recovered clock in the process of clock recovery, the clock jitter that recovery is come out is bigger, if a plurality of website cascade, the easy problem that error code after a plurality of website cascades, occurs.
Summary of the invention
The object of the present invention is to provide a kind of clock recovery method and device,, recover the technical problem that clock phase is discontinuous, shake is bigger that obtains to solve prior art in the clock recovery process.
The present invention solves the problems of the technologies described above through following technical scheme:
A kind of clock recovery method may further comprise the steps:
When Direct Digital Frequency Synthesizers DDS receives the clock information of customer data, calculate the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information, and read the corresponding waveform signal of above-mentioned clock information according to above-mentioned memory address;
After reading successfully, the waveform signal that reads is carried out phase discrimination processing, thereby generate the synchronised clock of above-mentioned customer data.
Above-mentioned clock information draws above-mentioned customer data separation through the clock data split circuit.
According to the preferred embodiment of the present invention, calculate the corresponding memory address step of waveform signal in above-mentioned DDS of above-mentioned clock information and comprise:
Above-mentioned DDS obtains the reference clock information on the veneer crystal oscillator, and in preset a period of time, calculates the frequency of above-mentioned reference clock information and above-mentioned client clock information respectively;
Then the frequency of above-mentioned reference clock information and the frequency of above-mentioned client clock information are subtracted each other, obtain the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information;
Above-mentioned frequency difference is done smoothing processing; Current frequency difference after level and smooth and above-mentioned DDS are added up according to all frequency differences that the clock information that receives before this calculates, and the value that obtains that adds up is the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information.
According to the preferred embodiment of the present invention, after above-mentioned waveform signal read successfully, above-mentioned DDS after above-mentioned PFD receives above-mentioned waveform signal, carried out phase discrimination processing to above-mentioned waveform signal with among the waveform signal input phase detection discriminator PFD that reads.
According to the preferred embodiment of the present invention, above-mentioned waveform signal carried out phase discrimination processing after, further comprising the steps of:
The control signal input voltage controlled oscillator VCO that above-mentioned PFD obtains phase demodulation;
Above-mentioned VCO generates the synchronised clock of above-mentioned customer data according to above-mentioned control signal.
Above-mentioned control signal reduces signal for the voltage increase signal or the voltage of the above-mentioned VCO voltage of control.
After above-mentioned VCO generates the synchronised clock of above-mentioned customer data according to above-mentioned control signal, further comprising the steps of:
Above-mentioned VCO is with in the above-mentioned synchronised clock input frequency divider;
Above-mentioned frequency divider carries out frequency division to above-mentioned synchronised clock, and the VCO frequency-dividing clock that frequency division obtains is imported among the above-mentioned PFD, makes above-mentioned PFD, above-mentioned VCO and above-mentioned distributor constitute a closed loop circuit.
Above-mentioned closed loop circuit locks the synchronised clock of above-mentioned customer data.
The present invention also adopts following technical scheme:
A kind of clock recovery device, said apparatus comprises: Direct Digital Frequency Synthesizers DDS, phase detection discriminator PFD and voltage controlled oscillator VCO;
Above-mentioned DDS is used for when receiving the clock information of customer data, calculates the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information, and reads the corresponding waveform signal of above-mentioned clock information according to above-mentioned memory address;
Above-mentioned PFD, the waveform signal that is used for above-mentioned DDS is read carries out phase discrimination processing;
Above-mentioned VCO is used for the control signal according to above-mentioned PFD phase demodulation output, generates the synchronised clock of above-mentioned customer data.
Said apparatus also comprises: clock data split circuit and frequency divider;
Above-mentioned clock data split circuit is used for isolating from customer data the clock information of above-mentioned DDS needs;
Above-mentioned frequency divider is used for that the synchronised clock that above-mentioned VCO generates is carried out frequency division and handles, and the VCO frequency-dividing clock that frequency division obtains is imported among the above-mentioned PFD, to lock above-mentioned synchronised clock.
Above-mentioned DDS comprises the clock acquisition module, frequency computation part module, frequency difference computing module, the even module of frequency difference, frequency difference accumulator module, memory module and signal reading module at random;
Above-mentioned clock acquisition module is used to obtain the reference clock information on the veneer crystal oscillator, or the clock information of above-mentioned clock data split circuit separation;
The said frequencies computing module is used in preset a period of time, calculating respectively the frequency of above-mentioned reference clock information and above-mentioned client clock information;
Above-mentioned frequency difference computing module is used for the frequency of above-mentioned reference clock information and the frequency of above-mentioned client clock information are subtracted each other, and obtains the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information;
The even module of above-mentioned frequency difference is used for the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information is done smoothing processing, eliminates high frequency content wherein;
Above-mentioned frequency difference accumulator module, be used for to above-mentioned frequency difference computing module this and before all frequency differences of calculating add up, and the value that obtains that will add up is made as the corresponding memory address of waveform signal in above-mentioned DDS of present clock information;
Above-mentioned memory module at random is used for the corresponding waveform signal of store clock information;
Above-mentioned signal reading module is used for the memory address according to above-mentioned frequency difference accumulator module output, reads the corresponding waveform signal of present clock information.
Compared with prior art, the present invention has following useful technique effect: the present invention adopts DDS adjustment phase place, can keep the phase place of recovered clock, reduces the shake of recovered clock, improves the quality of recovered clock, promotes the OTN technical development.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes a part of the present invention, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, does not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the clock recovery method flow chart of prior art;
Fig. 2 is the clock recovery method flow chart of the preferred embodiment of the present invention;
Fig. 3 is the clock recovery device module frame chart of the preferred embodiment of the present invention;
Fig. 4 is the block diagram of DDS in the preferred embodiment of the present invention.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and beneficial effect clearer, clear,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Fig. 2 is the clock recovery method flow chart of the preferred embodiment of the present invention.As shown in Figure 2, the method for the preferred embodiment of the present invention may further comprise the steps:
Step S201:, isolate the clock information of above-mentioned customer data through above-mentioned split circuit with pending customer data input clock data separation circuit;
Step S202: with above-mentioned clock information input DDS (Direct Digital Synthesizer, Direct Digital Frequency Synthesizers);
Step S203: above-mentioned DDS calculates the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information, reads the corresponding waveform signal of above-mentioned clock information according to above-mentioned memory address;
Store the corresponding waveform signal of various clock informations among the above-mentioned DDS; When these waveform signals are exported continuously; Can form the corresponding DDS recovered clock of customer data, in case after obtaining the DDS recovered clock, only need through PFD (Phase Frequent Detector; Phase detection discriminator) and VCO carry out phase demodulation frequency modulation and handle, the synchronised clock of promptly exportable final customer data.
In above-mentioned steps S203, above-mentioned DDS calculates the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information through following method:
Above-mentioned DDS obtains the reference clock information on the veneer crystal oscillator, and in preset a period of time, calculates the frequency of above-mentioned reference clock information and above-mentioned client clock information respectively;
Then the frequency of above-mentioned reference clock information and the frequency of above-mentioned client clock information are subtracted each other, obtain the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information;
Above-mentioned frequency difference is done smoothing processing; Current frequency difference after level and smooth and above-mentioned DDS are added up according to all frequency differences that the clock information that receives before this calculates, and the value that obtains that adds up is the corresponding memory address of waveform signal in above-mentioned DDS of above-mentioned clock information.
Wherein, above-mentioned preset a period of time can define according to actual conditions, for example can be 1 microsecond, also can be 500 microseconds; Choosing of above-mentioned reference clock information requires shake as far as possible little.
When calculating the frequency of above-mentioned reference clock information and above-mentioned client clock information; Can add up the number of the rising edge of above-mentioned reference clock information and above-mentioned client clock information in preset a period of time respectively; Then with the number of the rising edge of statistics divided by preset a period of time, can obtain the frequency of above-mentioned reference clock information and above-mentioned client clock information.
In the above-mentioned steps, the purpose of above-mentioned frequency difference being done smoothing processing is to eliminate the high frequency content in the above-mentioned frequency difference, with the chattering frequency of the synchronised clock that reduces final recovery.
Step S204: above-mentioned DDS is with among the waveform signal input PFD that reads;
Step S205: above-mentioned PFD carries out phase discrimination processing to the waveform signal of receiving, and the control signal that phase demodulation obtains is imported VCO;
Above-mentioned control signal comprises that the voltage of controlling above-mentioned VCO voltage increases signal UP or voltage reduces signal DOWN.The effect of UP is to increase voltage, thereby improves the output frequency of above-mentioned VCO, and the effect of DOWN is to reduce voltage, thereby reduces the output frequency of above-mentioned VCO.
Step S206: above-mentioned VCO generates the synchronised clock of above-mentioned customer data according to above-mentioned control signal, and with in the above-mentioned synchronised clock input frequency divider;
Step S207: above-mentioned frequency divider carries out frequency division to above-mentioned synchronised clock, and the VCO frequency-dividing clock that frequency division obtains is imported among the above-mentioned PFD;
Step S208: above-mentioned PFD, above-mentioned VCO and above-mentioned distributor constitute a closed loop circuit, and above-mentioned closed loop circuit locks the synchronised clock of above-mentioned customer data.
Above step has specified the clock recovery method of the preferred embodiment of the present invention.The preferred embodiment of the present invention adopts DDS adjustment phase place, can keep the phase place of recovered clock, reduces the shake of recovered clock, improves the quality of recovered clock, promotes the OTN technical development.
Fig. 3 is the clock recovery device module frame chart of the preferred embodiment of the present invention.As shown in Figure 3, the device of the preferred embodiment of the present invention comprises Direct Digital Frequency Synthesizers DDS31, phase detection discriminator PFD32, voltage controlled oscillator VCO 33, clock data split circuit 34 and frequency divider 35;
Above-mentioned DDS31 is used for when receiving the clock information of customer data, calculates the corresponding memory address of waveform signal in above-mentioned DDS31 of above-mentioned clock information, and reads the corresponding waveform signal of above-mentioned clock information according to above-mentioned memory address;
Above-mentioned PFD32 is used for the waveform signal that above-mentioned DDS31 reads is done phase discrimination processing;
Above-mentioned VCO33 is used for the control signal according to above-mentioned PFD32 phase demodulation output, generates the synchronised clock of above-mentioned customer data;
Above-mentioned clock data split circuit 34 is used for isolating from customer data the clock information of above-mentioned DDS needs;
Above-mentioned frequency divider 35 is used for that the synchronised clock that above-mentioned VCO33 generates is carried out frequency division and handles, and the VCO frequency-dividing clock that frequency division obtains is imported among the above-mentioned PFD32, to lock above-mentioned synchronised clock.
Fig. 4 is the block diagram of DDS in the preferred embodiment of the present invention.As shown in Figure 4, the DDS of the preferred embodiment of the present invention comprises clock acquisition module 311, frequency computation part module 312, frequency difference computing module 313, the even module 314 of frequency difference, frequency difference accumulator module 315, memory module 316 and signal reading module 317 at random;
Above-mentioned clock acquisition module 311 is used to obtain the reference clock information on the veneer crystal oscillator, or the clock information of above-mentioned clock data split circuit separation;
Said frequencies computing module 312 is used in preset a period of time, calculating respectively the frequency of above-mentioned reference clock information and above-mentioned client clock information;
Above-mentioned frequency difference computing module 313 is used for the frequency of above-mentioned reference clock information and the frequency of above-mentioned client clock information are subtracted each other, and obtains the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information;
The even module 314 of above-mentioned frequency difference is used for the frequency difference between above-mentioned reference clock information and the above-mentioned client clock information is done smoothing processing, eliminates high frequency content wherein;
Above-mentioned frequency difference accumulator module 315, be used for to above-mentioned frequency difference computing module this and before all frequency differences of calculating add up, and the value that obtains that will add up is made as the corresponding memory address of waveform signal in above-mentioned DDS of present clock information;
Above-mentioned memory module at random 316 is used for the corresponding waveform signal of store clock information;
Above-mentioned signal reading module 317 is used for the memory address according to above-mentioned frequency difference accumulator module output, reads the corresponding waveform signal of present clock information.
Above-mentioned explanation illustrates and has described the preferred embodiments of the present invention; But as previously mentioned; Be to be understood that the present invention is not limited to the form that this paper discloses, should do not regard eliminating as, and can be used for various other combinations, modification and environment other embodiment; And can in invention contemplated scope described herein, change through the technology or the knowledge of above-mentioned instruction or association area.And change that those skilled in the art carried out and variation do not break away from the spirit and scope of the present invention, then all should be in the protection range of accompanying claims of the present invention.
Claims (11)
1. a clock recovery method is characterized in that, may further comprise the steps:
When Direct Digital Frequency Synthesizers DDS receives the clock information of customer data, calculate the corresponding memory address of waveform signal in said DDS of said clock information, and read the corresponding waveform signal of said clock information according to said memory address;
After reading successfully, the waveform signal that reads is carried out phase discrimination processing, thereby generate the synchronised clock of said customer data.
2. method according to claim 1 is characterized in that: said clock information draws said customer data separation through the clock data split circuit.
3. method according to claim 2 is characterized in that, calculates the corresponding memory address step of waveform signal in said DDS of said clock information and comprises:
Said DDS obtains the reference clock information on the veneer crystal oscillator, and in preset a period of time, calculates the frequency of said reference clock information and said client clock information respectively;
Then the frequency of said reference clock information and the frequency of said client clock information are subtracted each other, obtain the frequency difference between said reference clock information and the said client clock information;
Said frequency difference is done smoothing processing; Current frequency difference after level and smooth and said DDS are added up according to all frequency differences that the clock information that receives before this calculates, and the value that obtains that adds up is the corresponding memory address of waveform signal in said DDS of said clock information.
4. according to claim 1 or 3 described methods, it is characterized in that: after reading successfully, said DDS after said PFD receives said waveform signal, carries out phase discrimination processing to said waveform signal with among the waveform signal input phase detection discriminator PFD that reads.
5. method according to claim 4 is characterized in that, said waveform signal is carried out phase discrimination processing after, further comprising the steps of:
The control signal input voltage controlled oscillator VCO that said PFD obtains phase demodulation;
Said VCO generates the synchronised clock of said customer data according to said control signal.
6. method according to claim 5 is characterized in that: said control signal reduces signal for the voltage increase signal or the voltage of the said VCO voltage of control.
7. method according to claim 5 is characterized in that, and is after said VCO generates the synchronised clock of said customer data according to said control signal, further comprising the steps of:
Said VCO is with in the said synchronised clock input frequency divider;
Said frequency divider carries out frequency division to said synchronised clock, and the VCO frequency-dividing clock that frequency division obtains is imported among the said PFD, makes said PFD, said VCO and said distributor constitute a closed loop circuit.
8. method according to claim 7 is characterized in that said closed loop circuit locks the synchronised clock of said customer data.
9. a clock recovery device is characterized in that, said device comprises: Direct Digital Frequency Synthesizers DDS, phase detection discriminator PFD and voltage controlled oscillator VCO;
Said DDS is used for when receiving the clock information of customer data, calculates the corresponding memory address of waveform signal in said DDS of said clock information, and reads the corresponding waveform signal of said clock information according to said memory address;
Said PFD, the waveform signal that is used for said DDS is read carries out phase discrimination processing;
Said VCO is used for the control signal according to said PFD phase demodulation output, generates the synchronised clock of said customer data.
10. device according to claim 9 is characterized in that, said device also comprises: clock data split circuit and frequency divider;
Said clock data split circuit is used for isolating from customer data the clock information of said DDS needs;
Said frequency divider is used for that the synchronised clock that said VCO generates is carried out frequency division and handles, and the VCO frequency-dividing clock that frequency division obtains is imported among the said PFD, to lock said synchronised clock.
11. device according to claim 10 is characterized in that, said DDS comprises the clock acquisition module, frequency computation part module, frequency difference computing module, the even module of frequency difference, frequency difference accumulator module, memory module and signal reading module at random;
Said clock acquisition module is used to obtain the reference clock information on the veneer crystal oscillator, or the clock information of said clock data split circuit separation;
Said frequency computation part module is used in preset a period of time, calculating respectively the frequency of said reference clock information and said client clock information;
Said frequency difference computing module is used for the frequency of said reference clock information and the frequency of said client clock information are subtracted each other, and obtains the frequency difference between said reference clock information and the said client clock information;
The even module of said frequency difference is used for the frequency difference between said reference clock information and the said client clock information is done smoothing processing, eliminates high frequency content wherein;
Said frequency difference accumulator module, be used for to said frequency difference computing module this and before all frequency differences of calculating add up, and the value that obtains that will add up is made as the corresponding memory address of waveform signal in said DDS of present clock information;
Said memory module at random is used for the corresponding waveform signal of store clock information;
Said signal reading module is used for the memory address according to said frequency difference accumulator module output, reads the corresponding waveform signal of present clock information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210158916.0A CN102684807B (en) | 2012-05-21 | 2012-05-21 | A kind of clock recovery method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210158916.0A CN102684807B (en) | 2012-05-21 | 2012-05-21 | A kind of clock recovery method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102684807A true CN102684807A (en) | 2012-09-19 |
| CN102684807B CN102684807B (en) | 2018-05-04 |
Family
ID=46816228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210158916.0A Active CN102684807B (en) | 2012-05-21 | 2012-05-21 | A kind of clock recovery method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102684807B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115425967A (en) * | 2022-08-31 | 2022-12-02 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
| CN115622655A (en) * | 2022-12-14 | 2023-01-17 | 中国科学技术大学 | Frequency self-adaptive clock distribution and synchronization method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536804A (en) * | 2003-04-09 | 2004-10-13 | 华为技术有限公司 | Digital clock recovery device in data communication system |
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN1889415A (en) * | 2005-06-27 | 2007-01-03 | 华为技术有限公司 | Apparatus and method for making master and spare clock plate phase position alignment |
| CN101414820A (en) * | 2007-10-17 | 2009-04-22 | 中兴通讯股份有限公司 | Digital frequency synthesis and synchronous circuit |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
-
2012
- 2012-05-21 CN CN201210158916.0A patent/CN102684807B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536804A (en) * | 2003-04-09 | 2004-10-13 | 华为技术有限公司 | Digital clock recovery device in data communication system |
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN1889415A (en) * | 2005-06-27 | 2007-01-03 | 华为技术有限公司 | Apparatus and method for making master and spare clock plate phase position alignment |
| CN101414820A (en) * | 2007-10-17 | 2009-04-22 | 中兴通讯股份有限公司 | Digital frequency synthesis and synchronous circuit |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115425967A (en) * | 2022-08-31 | 2022-12-02 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
| CN115425967B (en) * | 2022-08-31 | 2023-11-14 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
| CN115622655A (en) * | 2022-12-14 | 2023-01-17 | 中国科学技术大学 | Frequency self-adaptive clock distribution and synchronization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102684807B (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101098220B (en) | Digital phase-locked loop based clock synchronization method and system thereof | |
| CN103219946B (en) | Polar coordinates reflector, frequency modulation path and method, fixed phase generator and method | |
| US8803573B2 (en) | Serializer-deserializer clock and data recovery gain adjustment | |
| US8559581B2 (en) | CDR circuit, reception apparatus, and communication system | |
| WO2018137548A1 (en) | Clock synchronization device and method | |
| CN102223198B (en) | One realizes clock recovery method and device | |
| CN106341219B (en) | A kind of data synchronous transmission device based on spread spectrum | |
| CN103138754A (en) | Clock generator and a method of generating a clock signal | |
| US4763342A (en) | Digital phase-locked loop circuits with storage of clock error signal | |
| KR920003598B1 (en) | Frequency and phase detection circuit with the nrz synchronize | |
| US20160202722A1 (en) | Transmission device and method for controlling fifo circuit | |
| CN102684807A (en) | Clock recovering method and device | |
| US20070081619A1 (en) | Clock generator and clock recovery circuit utilizing the same | |
| CN113972893A (en) | Clock synchronization method and device, electronic equipment and storage medium | |
| US6577693B1 (en) | Desynchronizer for a synchronous digital communications system | |
| EP3142286B1 (en) | Synchronising devices and method | |
| CN101964688A (en) | Method and system for recovering data clock | |
| CN109286482B (en) | Method and device for realizing clock recovery | |
| CN108055036B (en) | Loop bandwidth adjusting method and device of clock data recovery circuit | |
| CN103051333B (en) | Phase-locked loop with rapid locking function | |
| US6959060B2 (en) | Jitter reducing apparatus using digital modulation technique | |
| JP5342690B1 (en) | Clock regeneration apparatus and method | |
| JP4789976B2 (en) | Clock generation enable generation circuit and clock recovery circuit | |
| CN114944973B (en) | Clock signal recovery method and system | |
| EP2290856A1 (en) | Clock reproduction signal generation method and clock reproduction circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |