CN104506270A - Time and frequency synchronization integration implementation system and method - Google Patents
Time and frequency synchronization integration implementation system and method Download PDFInfo
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- CN104506270A CN104506270A CN201410829415.XA CN201410829415A CN104506270A CN 104506270 A CN104506270 A CN 104506270A CN 201410829415 A CN201410829415 A CN 201410829415A CN 104506270 A CN104506270 A CN 104506270A
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Abstract
The invention discloses a time and frequency synchronization integration implementation system and method. The system comprises a time reference input unit, a frequency reference input unit, a clock-controlled unit, a time output unit, a frequency output unit, a system control unit, a power supply unit, a fan unit and a backboard unit. The time reference input unit and the frequency reference input unit are combined, alarm, input and output status and performance parameters of whole equipment are queried and subjected to configuration management through the system control unit, a function of simultaneously integrating time synchronization and frequency synchronization is realized, great convenience is brought to users for networking, networking cost is lowered, and the requirements of different users on different quantity demands of time and frequency synchronization can be met flexibly.
Description
Technical field
The invention belongs to temporal frequency simultaneous techniques field, be specifically related to a kind of temporal frequency synchronous integrated and realize system and implementation method.
Background technology
In the communications industry, synchronously there is higher requirement always to temporal frequency.Be the demand to Frequency Synchronization in the past, and now along with 3G/4G technical development and maturation, also had the development of the multiple emerging technologies such as synchronous ethernet, not only need Frequency Synchronization, also higher requirement is present in time synchronized.
At present, upper frequency synchronous and time synchronized in market is nearly all the 2 kinds of equipment separated, and user will realize frequency and time synchronized, just must purchase 2 kinds of equipment simultaneously, and in difference connecting system, so just there is networking cost higher, difficult in maintenance, maintenance cost is more high defect also.Along with the progress of technology and the demand in market, the trend that current 2 kinds of synchronizers combine together very obvious, single complete equipment meets the integration requirement of user to time and Frequency Synchronization simultaneously, also greatly facilitate for user's networking provides and reduce networking cost, and the requirement of different user to the time demand different with Frequency Synchronization can be met flexibly.
Summary of the invention
The object of the invention is to solve the problem, provide a kind of temporal frequency synchronous integrated to realize system and implementation method, this system can realize time synchronized and the Frequency Synchronization of single device simultaneously.
To achieve these goals, of the present invention adopted technical scheme is:
A kind of temporal frequency synchronous integrated realizes system, comprises time reference input unit, frequency reference input unit, clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit and backboard unit;
Time reference input unit is used for the input of time of reception reference signal;
Frequency reference input module is used for the input of receive frequency reference signal;
Clock unit is used for the reference signal of time of reception frequency reference input unit, and filtering, decoding, frequency discrimination and phase demodulation computing are carried out to these signals, calculate a split-second precision signal and high accuracy frequency signal, output to time output unit and frequency output unit;
Time output unit is used for carrying out time synchronizing signal output;
Frequency output unit is used for carrying out frequency synchronization signal output;
System control unit is inquired about and configuration management for the alarm to whole equipment, input/output state, performance parameter;
Power subsystem is used for powering to other unit of system;
Fan unit dispels the heat to other unit of system for being responsible for;
Backboard unit is used for providing physical connection to system unit, and backboard unit is also for the 1+1 protection output function of time output unit and frequency output unit provides corresponding hardware interface simultaneously.
Described time reference input unit adopts the mode of MAX3232ESE chip and RJ45 socket to carry out the input of time of reception reference signal.
Described frequency reference input module adopts the mode of DS26303 chip and CC4 coaxial head to carry out the input of receive frequency reference signal.
Described clock unit is made up of S3C2440, XC3S700AN and high accuracy rubidium clock.
Described time output unit adopts the mode of MAX3232ESE chip and RJ45 socket to carry out time synchronizing signal output.
Described frequency output unit adopts the mode of DS26303 and CC4 socket to carry out frequency synchronization signal output.
Described system control unit is made up of S3C2440, XC3S250E, XC95144XL and RTL8201CP.
Computer management software is communicated with system control unit by Ethernet, realizes the alarm to whole equipment, input/output state, performance parameter are inquired about, configuration management;
Wherein, S3C2440 is master cpu, for the collection of whole facility information with issue;
XC3S250E is used for carrying out hardware detection to the information of each functional unit, and is reported to CPU;
XC95144XL is used for expanding the I/O of XC3S250E;
RTL8201CP is used for that the information of CPU is converted to ethernet signal and uploads to computer management software.
A kind of temporal frequency synchronous integrated implementation method, comprises the following steps:
1) time reference input unit receives outside time signal, and decodes to time signal, and generation time, with reference to 1PPS signal and TOD signal, outputs to clock unit;
2) frequency reference input unit receives outside 2MBit signal and 2MHz signal, produces frequency reference 1PPS signal, output to clock unit by frequency division;
3) rubidium clock of clock unit produces 10MHz signal, by 10MHz signal generation system 1PPS;
4) when system only has frequency reference 1PPS signal to input, system 1PPS signal directly and frequency reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When system only time is with reference to the input of 1PPS signal, system 1PPS signal directly and time reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When the input of system existing time reference 1PPS signal, when having again frequency reference 1PPS signal to input, system 1PPS signal produces original phase demodulation data by deciding still to carry out phase demodulation computing with frequency reference 1PPS signal with time reference 1PPS signal according to the configuration of host computer;
5), after clock unit carries out medium filtering to original phase demodulation data, adjust according to the frequency of filtered phase demodulation data to rubidium clock.
Described step 5) in, concrete adjustment algorithm is as follows:
Be in init state Init when 5-1) device power starts, after detecting that each functional module all normally works, enter hold mode Hold;
5-2) after rubidium clock work is ready, equipment enters catches state Fasttrack soon, catching status system soon and can carry out rubidium clock according to phase demodulation value the adjustment of larger step-length, makes the 1PPS output accuracy of system within 400ns; After the 1PPS precision of continuous 10 points of master slave systems is all better than 400ns, equipment can enter following 4 kinds of states according to current tracking mode: Quadrant1, Quadrant2, Quadrant3 and Quadrant4,4 quadrants of these 4 kinds of corresponding SIN function of states difference;
5-3) system is just changed successively in these 4 kinds of states:
Quadrant1→Quadrant2→Quadrant3→Quadrant4→Quadrant1
Wherein, this two states of Quadrant2 → Quadrant3 and Quadrant4 → Quadrant1 is called system zero crossing, corresponding phase point is 0 and π, when zero crossing, rubidium clock adjustment amount linearly reduces than the adjustment amount of last time, reduce proportionality constant corresponding with the performance of rubidium clock, the output 1PPS phase place of system just presents damped oscillation, finally within stable ± 50ns.
Time reference input unit combines with frequency reference input unit by the present invention, by system control unit, the alarm of whole equipment, input/output state, performance parameter are inquired about and configuration management, achieve the function of the synchronous and Frequency Synchronization of simultaneously time of fusion, greatly facilitate for user's networking provides and reduce networking cost, and the requirement of different user to the time demand different with Frequency Synchronization can be met flexibly.Backboard unit of the present invention directly exports 1PPS+TOD time signal and 10MHz frequency signal, for time output board card, directly 1PPS+TOD signal is converted to the form of needs and exportable.For rate-adaptive pacemaker board; then the board of adjacent two slots forms protection group output; two boards in a protection group lock same 1PPS signal simultaneously; also send monitor signal mutually between board simultaneously; like this output frequency of these two boards and phase place just completely the same, meet YD/T 1479-2006 national standard.
Accompanying drawing explanation
Fig. 1 is logical construction block diagram of the present invention;
Fig. 2 is state transition diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described further
As shown in Figure 1, the present invention is a kind of logic diagram of temporal frequency synchronous integrated implementation.The program is made up of such as lower unit: time reference input unit, frequency reference input unit, clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit, backboard unit.
Time reference input unit adopts the mode of MAX3232ESE chip+RJ45 socket to carry out the input of time of reception reference signal.
Frequency reference input module adopts the mode of DS26303 chip+CC4 coaxial head to carry out the input of receive frequency reference signal.
Clock unit is the core of this programme.Clock unit is made up of S3C2440+XC3S700AN+ high accuracy rubidium clock.The reference signal of primary responsibility time of reception frequency reference input unit, and filtering is carried out to these signals, decoding, frequency discrimination, the digital operations such as phase demodulation, calculate a split-second precision signal and high accuracy frequency signal, output to time output unit and frequency output unit.
Time output unit adopts the mode of MAX3232ESE chip+RJ45 socket to carry out time synchronizing signal output.
Frequency output unit adopts the mode of DS26303+CC4 socket to carry out frequency synchronization signal output.
System control unit is made up of S3C2440+XC3S250E+XC95144XL+RTL8201CP.Computer management software is communicated with system control unit by Ethernet, realizes the alarm to whole equipment, input/output state, performance parameter are inquired about, configuration management.Wherein S3C2440 is master cpu, and be responsible for the collection of whole facility information and issue, XC3S250E carries out hardware detection to the information of each functional unit, and is reported to CPU.XC95144XL expands the I/O of XC3S250E.The information of CPU is converted to ethernet signal to upload to computer management software by RTL8201CP.
Power subsystem is responsible for powering to other unit of system.
Fan unit is responsible for dispelling the heat to other unit of system.
Backboard unit is then provide physical connection to system unit, and backboard unit is also for the 1+1 protection output function of time output unit and frequency output unit provides corresponding hardware interface simultaneously.
Workflow of the present invention:
Time reference input unit receives outside time signal, and decodes to time signal, and generation time, with reference to 1PPS signal and TOD signal, outputs to clock unit.
Frequency reference input unit receives outside 2MBit signal and 2MHz signal, produces frequency reference 1PPS signal, output to clock unit by frequency division.
The rubidium clock of clock unit produces 10MHz signal, by 10MHz signal generation system 1PPS.
When system only has frequency reference 1PPS signal to input, system 1PPS signal directly and frequency reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When system only time is with reference to the input of 1PPS signal, system 1PPS signal directly and time reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When the input of system existing time reference 1PPS signal, when having again frequency reference 1PPS signal to input, system 1PPS signal still carries out phase demodulation computing with frequency reference 1PPS signal by deciding according to the configuration of host computer with time reference 1PPS signal.
After clock unit carries out medium filtering to original phase demodulation data, adjust according to the frequency of filtered phase demodulation data to rubidium clock, adjustment algorithm is as follows:
Native system realizes temporal frequency to merge output, should ensure the precision of rate-adaptive pacemaker, ensures again therefore to need the precision that the time exports to use zero passage detection and damping adjustment technology.The present invention adopts FPGA to realize, and the state transitions of key component as shown in Figure 2.
Operation principle is as follows: be in Init (init state) when device power starts, after detecting that each functional module all normally works, enter Hold (hold mode), this is because rubidium clock normal working temperature is 60 DEG C, therefore just power on need during this period of time heating about about 10 minutes.After rubidium clock work is ready, equipment enters Fasttrack (catching state soon), catching status system soon and can carry out rubidium clock according to phase demodulation value the adjustment of larger step-length, makes the 1pps output accuracy of system within 400ns.After the 1pps precision of continuous 10 points of master slave systems is all better than 400ns, equipment can enter following 4 kinds of states according to current tracking mode: Quadrant1, Quadrant2, Quadrant3, Quadrant4, respectively 4 quadrants of corresponding SIN function.Then system is just changed successively in these 4 kinds of states: Quadrant1 → Quadrant2 → Quadrant3 → Quadrant4 → Quadrant1.Wherein Quadrant2 → Quadrant3, this two states of Quadrant4 → Quadrant1 is called system zero crossing, corresponding phase point is 0 and π, when zero crossing, rubidium clock adjustment amount linearly reduces than the adjustment amount of last time, reduce the performance of proportionality constant generally with rubidium clock relevant, the output 1pps phase place of such system just presents damped oscillation, finally within stable ± 50ns.
Temporal frequency integration exports: backboard unit of the present invention directly exports 1PPS+TOD time signal and 10MHz frequency signal, for time output board card, directly 1PPS+TOD signal is converted to the form of needs and exportable.For rate-adaptive pacemaker board; then the board of adjacent two slots forms protection group output; two boards in a protection group lock same 1PPS signal simultaneously; also send monitor signal mutually between board simultaneously; like this output frequency of these two boards and phase place just completely the same, meet YD/T 1479-2006 national standard.
Above content is only and technological thought of the present invention is described; protection scope of the present invention can not be limited with this; every technological thought proposed according to the present invention, any change that technical scheme basis is done, within the protection range all falling into claims of the present invention.
Claims (10)
1. temporal frequency synchronous integrated realizes a system, it is characterized in that: comprise time reference input unit, frequency reference input unit, clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit and backboard unit;
Time reference input unit is used for the input of time of reception reference signal;
Frequency reference input module is used for the input of receive frequency reference signal;
Clock unit is used for the reference signal of time of reception frequency reference input unit, and filtering, decoding, frequency discrimination and phase demodulation computing are carried out to these signals, calculate a split-second precision signal and high accuracy frequency signal, output to time output unit and frequency output unit;
Time output unit is used for carrying out time synchronizing signal output;
Frequency output unit is used for carrying out frequency synchronization signal output;
System control unit is inquired about and configuration management for the alarm to whole equipment, input/output state, performance parameter;
Power subsystem is used for powering to other unit of system;
Fan unit dispels the heat to other unit of system for being responsible for;
Backboard unit is used for providing physical connection to system unit, and backboard unit is also for the 1+1 protection output function of time output unit and frequency output unit provides corresponding hardware interface simultaneously.
2. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described time reference input unit adopts the mode of MAX3232ESE chip and RJ45 socket to carry out the input of time of reception reference signal.
3. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described frequency reference input module adopts the mode of DS26303 chip and CC4 coaxial head to carry out the input of receive frequency reference signal.
4. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described clock unit is made up of S3C2440, XC3S700AN and high accuracy rubidium clock.
5. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described time output unit adopts the mode of MAX3232ESE chip and RJ45 socket to carry out time synchronizing signal output.
6. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described frequency output unit adopts the mode of DS26303 and CC4 socket to carry out frequency synchronization signal output.
7. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterized in that: described system control unit is made up of S3C2440, XC3S250E, XC95144XL and RTL8201CP.
8. temporal frequency synchronous integrated according to claim 7 realizes system, it is characterized in that: computer management software is communicated with system control unit by Ethernet, realize the alarm to whole equipment, input/output state, performance parameter are inquired about, configuration management;
Wherein, S3C2440 is master cpu, for the collection of whole facility information with issue;
XC3S250E is used for carrying out hardware detection to the information of each functional unit, and is reported to CPU;
XC95144XL is used for expanding the I/O of XC3S250E;
RTL8201CP is used for that the information of CPU is converted to ethernet signal and uploads to computer management software.
9. as described in claim 1-8 any one, realize a temporal frequency synchronous integrated implementation method for system, it is characterized in that, comprise the following steps:
1) time reference input unit receives outside time signal, and decodes to time signal, and generation time, with reference to 1PPS signal and TOD signal, outputs to clock unit;
2) frequency reference input unit receives outside 2MBit signal and 2MHz signal, produces frequency reference 1PPS signal, output to clock unit by frequency division;
3) rubidium clock of clock unit produces 10MHz signal, by 10MHz signal generation system 1PPS;
4) when system only has frequency reference 1PPS signal to input, system 1PPS signal directly and frequency reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When system only time is with reference to the input of 1PPS signal, system 1PPS signal directly and time reference 1PPS signal carry out phase demodulation and produce original phase demodulation data; When the input of system existing time reference 1PPS signal, when having again frequency reference 1PPS signal to input, system 1PPS signal produces original phase demodulation data by deciding still to carry out phase demodulation computing with frequency reference 1PPS signal with time reference 1PPS signal according to the configuration of host computer;
5), after clock unit carries out medium filtering to original phase demodulation data, adjust according to the frequency of filtered phase demodulation data to rubidium clock.
10. temporal frequency synchronous integrated implementation method according to claim 9, is characterized in that, described step 5) in, concrete adjustment algorithm is as follows:
Be in init state Init when 5-1) device power starts, after detecting that each functional module all normally works, enter hold mode Hold;
5-2) after rubidium clock work is ready, equipment enters catches state Fasttrack soon, catching status system soon and can carry out rubidium clock according to phase demodulation value the adjustment of larger step-length, makes the 1PPS output accuracy of system within 400ns; After the 1PPS precision of continuous 10 points of master slave systems is all better than 400ns, equipment can enter following 4 kinds of states according to current tracking mode: Quadrant1, Quadrant2, Quadrant3 and Quadrant4,4 quadrants of these 4 kinds of corresponding SIN function of states difference;
5-3) system is just changed successively in these 4 kinds of states:
Quadrant1→Quadrant2→Quadrant3→Quadrant4→Quadrant1
Wherein, this two states of Quadrant2 → Quadrant3 and Quadrant4 → Quadrant1 is called system zero crossing, corresponding phase point is 0 and π, when zero crossing, rubidium clock adjustment amount linearly reduces than the adjustment amount of last time, reduce proportionality constant corresponding with the performance of rubidium clock, the output 1PPS phase place of system just presents damped oscillation, finally within stable ± 50ns.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104935329A (en) * | 2015-06-29 | 2015-09-23 | 大唐电信（成都）信息技术有限公司 | Multi-channel reference source soft switching method and system of time synchronizer |
| CN109194431A (en) * | 2018-08-13 | 2019-01-11 | 郑州威科姆华大北斗导航科技有限公司 | A kind of clock time-frequency one transmission method and device |
| CN110752877A (en) * | 2019-11-04 | 2020-02-04 | 深圳市慧宇系统有限公司 | System and method for transmitting time frequency signal in optical fiber |
| CN112187363A (en) * | 2020-09-18 | 2021-01-05 | 中国科学院上海光学精密机械研究所 | High-precision optical fiber time frequency transmission system and method compatible with Ethernet |
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| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102064827A (en) * | 2010-11-11 | 2011-05-18 | 国网电力科学研究院 | Rubidium oscillator-based standard frequency and time adjusting method |
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| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102064827A (en) * | 2010-11-11 | 2011-05-18 | 国网电力科学研究院 | Rubidium oscillator-based standard frequency and time adjusting method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935329A (en) * | 2015-06-29 | 2015-09-23 | 大唐电信（成都）信息技术有限公司 | Multi-channel reference source soft switching method and system of time synchronizer |
| CN104935329B (en) * | 2015-06-29 | 2018-09-25 | 大唐电信（成都）信息技术有限公司 | A kind of soft reverse method of time synchronism equipment multichannel reference source and system |
| CN109194431A (en) * | 2018-08-13 | 2019-01-11 | 郑州威科姆华大北斗导航科技有限公司 | A kind of clock time-frequency one transmission method and device |
| CN109194431B (en) * | 2018-08-13 | 2020-04-21 | 郑州威科姆华大北斗导航科技有限公司 | Clock time-frequency integrated transmission method and device |
| CN110752877A (en) * | 2019-11-04 | 2020-02-04 | 深圳市慧宇系统有限公司 | System and method for transmitting time frequency signal in optical fiber |
| CN110752877B (en) * | 2019-11-04 | 2021-12-07 | 深圳市慧宇系统有限公司 | System and method for transmitting time frequency signal in optical fiber |
| CN112187363A (en) * | 2020-09-18 | 2021-01-05 | 中国科学院上海光学精密机械研究所 | High-precision optical fiber time frequency transmission system and method compatible with Ethernet |
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Application publication date: 20150408 Assignee: DATANG TELECOM (CHENGDU) INFORMATION TECHNOLOGY CO., LTD. Assignor: Datang Telecommunication Science & Technology Co., Ltd. Contract record no.: 2019990000003 Denomination of invention: Time and frequency synchronization integration implementation system and method Granted publication date: 20170616 License type: Common License Record date: 20190107 |
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