CN104881388A - FPGA (field programmable gate array) based USB3.0 interface module - Google Patents
FPGA (field programmable gate array) based USB3.0 interface module Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F2213/0042—Universal serial bus [USB]
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Abstract
The invention discloses an FPGA (field programmable gate array) based USB3.0 interface module, and relates to a USB3.0 interface module in order to realize compatibility with a USB2.0 high-speed interface as well as high-speed data transmission between a computer and an FPGA. According to the interface module, the FPGA is adopted to realize logic control, and the high-speed data transmission is realized through data read-write operation of synchronous slave equipment FIFO (first input first output) in a chip FX3; the interface module control logic comprises a USB3.0 transmitting module, a USB3.0 receiving module, an FIFO transmitting module for clock domain crossing operation and an FIFO receiving module for the clock domain crossing operation. The FPGA based USB3.0 ultrahigh-speed interface is compatible with the USB2.0 high-speed interface, and the high-speed data transmission between the computer and the FPGA is realized.
Description
Technical field
The present invention relates to a kind of USB 3.0 interface module.
Background technology
Computing machine is conventional data Storage & Display equipment, but its data-handling capacity is more weak, is unfavorable for large data processing.Along with developing by leaps and bounds of infotech, the data of explosive increase propose new challenge to data processing and transmission.And the feature such as FPGA is fast with its processing speed, process data volume is large, become the ideal platform of data processing.In order to realize the data transmission between computing machine and FPGA, design is needed to realize a kind of high-speed interface based on FPGA.
Computing machine common interfaces has USB 2.0, USB 3.0, PCI and Ethernet etc.Because USB 2.0 transfer rate is lower, only up to 480Mbps, pci bus is not supported hot plug and is only limitted to desk-top computer, and Ethernet propagation delay time is very large.USB 3.0 is with the hypervelocity of its 5Gbps, compared with low transmission time delay and the feature such as portable, become a kind of data transmission interface of widespread use.
Consider based on above reason, we wish to design a kind of USB 3.0 high-speed interface based on FPGA, are convenient to the data transmission between equipment and FPGA such as computing machine.
Summary of the invention
The present invention is to realize compatible USB2.0 high-speed interface, realizes between computing machine and FPGA high speed data transfer, thus proposes a kind of USB 3.0 interface module based on FPGA.
Based on USB 3.0 interface module of FPGA, this interface module adopts FPGA to realize logic control, and synchronously realizes high speed data transfer from the data read-write operation of equipment FIFO by chip FX3 inside;
This interface module steering logic comprise USB 3.0 sending module, USB 3.0 receiver module, for cross clock domain operation transmission First Input First Output fifo module and for cross clock domain operation reception First Input First Output fifo module;
Described USB 3.0 sending module comprises following state:
USB_out_idle state: under this state, all registers of initialization and signal;
USB_out_flagc_rcvd state: when zone bit flagc=1 being detected, it is full for sending thread producer USB socket, that is: the data that USB sends detected, then start the transmission to data;
USB_out_wait_flagd state: postpone a clock period, waits the transmission thread producer to be detected synchronously full from equipment FIFO;
USB_out_read state: when zone bit flagd=1 being detected, sending thread synchronization is full from equipment FIFO, activates read control signal, and FPGA reads synchronous from equipment data fifo;
USB_out_read_rd_oe_delay state: as zone bit flagd=0, chip FX3 carries out the sampling of three clock period to the read signal being in state of activation, read signal and output enable signal effective all the time;
USB_out_read_oe_delay state: after chip FX3 completes and samples to the read signal being in state of activation, output enable signal demand jumps to USB_out_idle state after keeping four clock period;
Described USB 3.0 receiver module comprises following state:
USB_in_idle state: under this state, all registers of initialization and signal;
USB_in_wait_flagb state: as zone bit flaga=1, receiving thread consumer USB socket is empty, that is: USB does not send data, then start the reception to data;
USB_in_write state: when zone bit flagb=1 being detected, the receiving thread producer is synchronously empty from equipment FIFO, FPGA by synchronous for data write from equipment FIFO;
USB_in_write_wr_delay state: when zone bit flagb=0 being detected, chip FX3 carries out the sampling of two clock period to the write signal being in state of activation, jumps to USB_in_idle state afterwards.
The model C YUSB3014 of chip FX3.
FPGA is connected with CYUSB3014 chip by GPIF II interface, and the USB interface of CYUSB3014 chip is connected with MicroB interface, adopts I2C interface to guide and starts, if I2C configuration failure, then uses usb mode configuration to start.
Also jtag interface is embedded with, for as debugging interface in CYUSB3014 chip.
When carrying out FX3 firmware design, be first synchronous from equipment fifo interface by GPIF II interface configuration; GPIF IIDesigner instrument is adopted to realize GPIF II interface configuration.
FX3 firmware program, FX3 firmware frame, FX3API storehouse and RTOS module;
Described RTOS module: for creating multiple thread;
FX3API storehouse: for providing the interface controlling with FX3 hardware implementing to transmit with data;
FX3 firmware frame: for the firmware program of development of user customization, comprises and starting and the driver of modules such as setup code and USB, GPIFII;
FX3 firmware program comprises initialization subroutine and application subprogram.
The concrete manner of execution of initialization subroutine is:
FX3 firmware program first call function CyU3PFirmwareEntry () realizes MMU and storehouse initialization, and eliminates invalid cache;
CyU3PToolChainInit () function is used for initialization tools chain, realizes the initialization in storehouse and C language storehouse;
Device initialize: perform following FOUR EASY STEPS successively:
Steps A, device initialize: by calling CyU3PDeviceInit () function setup cpu clock, initialization VIC and configuration PLL;
Step B, equipment cached configuration: FX3 equipment has 8KB data buffer storage and 8KB order buffer memory, only needs enable command buffer memory;
Step C, I/O configure: the interface of configuration FX3, comprise: GPIF II interface, SPI interface, I2C interface, I2S interface, GPIO interface and UART interface, call CyU3PDeviceConfigureIOMatrix () and initialization is carried out to I/O matrix data structure;
Step D, call RTOS: call ThreadX OS operating system by CyU3PKernelEntry (), complete ThreadXOS initialization and OS clock is set;
Creating application thread: after initialization ThreadX OS, creating application program threads by calling CyFxApplicationDefine ().
The concrete manner of execution of initialization subroutine is:
Debug module initialization: call CyFxSlFifoApplnDebugInit () and realize Debug module initialization, first initialization configure UART state, call CyU3PDebugInit () initialization Debug afterwards again and apply;
Customized application initialization: application initializes comprises two parts, GPIF II initialization and USB initialization, to be loaded into GPIF II register from equipment FIFO descriptor and start GPIF II state machine in GPIF II initialization, USB descriptor will be set in USB initialization, and create USB and connect with event and USB descriptor is set;
Process USB request: decoding USB request signal, process is set up USB connection request and is removed USB connection request;
USB event handling: USB comprises configuring request, resets and disconnects 3 kinds of events, starts USB transmission application when configuring request being detected, otherwise, stop USB application;
Start USB transmission application: configuring request detected, firmware starts USB transmission application, according to USB transfer rate determination data package size and DMA buffer size, creates DMA transmission channel;
Stop USB application: the request that resets/disconnect detected, releasing memory, closedown DMA passage;
USB to Processor passage/Processor to USB passage: call DMA function transfer data, U2P/P2U passage realizes automatic DMA passage.
In FX3 firmware, arrange two DMA passages: sendaisle is U2P passage, receiving cable is P2U passage, and these two DMA channel settings are the automatic DMA passage that transfer rate is higher.
The data-transmission mode of this USB 3.0 interface module is bulk transfer, when carrying out FX3 firmware configuration, increasing U2P channel buffer size, reducing P2U channel buffer size.
The present invention proposes a kind of USB 3.0 very high-speed interfaces based on FPGA, can compatible USB2.0 high-speed interface, realize the high speed data transfer between computing machine and FPGA, and transfer rate reaches as high as 2.5Gbps; To the FPGA of other USB 3.0 controllers and other series of part, there is certain versatility simultaneously.
Accompanying drawing explanation
Fig. 1 is the logic diagram of CYUSB3014;
Fig. 2 is synchronously from the USB 3.0 interface module principle schematic of equipment based on FX3;
Fig. 3 is USB 3.0 interface logic block diagram;
Fig. 4 is USB 3.0 sending module state transition graph;
Fig. 5 is USB 3.0 receiver module state transition graph;
Fig. 6 is GPIF II configuration flow schematic diagram;
Fig. 7 is FX3 firmware structure schematic diagram;
Fig. 8 is initialization subroutine schematic flow sheet;
Fig. 9 is user's application subprogram schematic flow sheet;
Figure 10 is FX3 firmware program DMA channel setting schematic diagram;
Embodiment
Embodiment one, composition graphs 1 to Figure 10 illustrate this embodiment, based on USB 3.0 interface module of FPGA,
The present invention is based on the USB 3.0 peripheral control unit FX3 family chip CYUSB3014 of CYPRESS company, using the FPGA of altera corp as main control chip control FX3 chip read-write sequence, to realize USB 3.0 high-speed interface for target, design the data transmission interface reaching as high as 2.5Gbps transfer rate.
1, hardware circuit
The main flow that CYPRESS company FX3 series CYUSB3014 chip becomes USB 3.0 peripheral control unit with its highly integrated flexible nature is selected.Inner integrated 32 the ARM926EJ-S microprocessors of FX3, frequency of operation is 200MHz, has powerful data-handling capacity.This integrated chip USB 3.0 and USB 2.0 Physical layer, and provide SPI, I2C, UART to communicate with external unit with I2S interface.FX3 has a high-performance, high flexibility ratio, the parallel general programmable interface GPIF II (General Programmable InterFace II) that can configure completely, can with the random processor seamless links such as FPGA, transfer rate can reach 2.5Gbps.Sheet carries 512KB RAM and is applicable to code and data store, and inner integrated inter-port DMA framework, can realize the data transmission capabilities more than 3.2Gbps.CYUSB3014 logic diagram as shown in Figure 1.
The present invention adopts based on the USB3.0 Interface design of CYUSB3014, is synchronously applicable to from equipment fifo interface ppu (FPGA/ASIC/DSP) needs to carry out data read-write operation application to the inner fifo buffer of EZ-USB FX3.Be synchronously the main embodiment of GPIF II from equipment fifo interface, can meet the transmission requirement of high-throughput, the design uses and carries out Interface design from equipment FIFO, and its hardware system block diagram as shown in Figure 2.FPGA is connected with CYUSB3014 chip by GPIF II interface, and USB interface is connected with Micro B interface.Adopt I2C interface to guide to start, if I2C configuration failure, use usb mode to configure and start.Meanwhile, reserved jtag interface is to debug.
2, interface logic
USB 3.0 Interface Controller realizes primarily of fpga logic, by synchronously realizing high speed data transfer from the data read-write operation of equipment FIFO to FX3 inside.Interface logic comprises two module: USB 3.0 sending modules, USB 3.0 receiver module, and for cross clock domain operation transmission FIFO (First Input First Output, First Input First Output) with receive FIFO.Meanwhile, compatible USB 2.0 interface of this interface logic.
2.1, USB 3.0 sending module
USB 3.0 sending module mainly realizes the sending function of computer data, and its data volume is large, and transmission rate request is high.Synchronously read sequential from equipment fifo interface according to FX, design USB sending module state machine as shown in Figure 4:
(1), USB_out_idle state: all registers of this state initialization and signal;
(2), USB_out_flagc_rcvd state: flagc=1, it be full for sending thread producer USB socket, the data that USB sends namely detected, startup transmission state machine;
(3), USB_out_wait_flagd state: postpone a clock period, wait the transmission thread producer to be detected synchronously full from equipment FIFO;
(4), USB_out_read state: flagd=1, sending thread synchronization be full from equipment FIFO, activates read control signal, and FPGA reading is synchronously from equipment data fifo;
(5), USB_out_read_rd_oe_delay state: flagd=0, FX3 need the sampling read signal being in state of activation being carried out to three clock period, read signal and output enable signal effective all the time;
(6), USB_out_read_oe_delay state: FX3 complete to be in state of activation read signal sampling after, output enable signal demand keeps four clock period can jump to USB_out_idle state.
2.2, USB 3.0 receiver module
USB receiver module mainly realizes the passback of FPGA data, and its data volume is large, and transmission rate request is high.Synchronously write sequential from equipment fifo interface according to FX, design USB receiver module state machine as shown in Figure 5:
(1), USB_in_idle state: all registers of this state initialization and signal;
(2), USB_in_wait_flagb state: flaga=1, receiving thread consumer USB socket is empty, and namely USB does not send data, starts receive state machine;
(3), USB_in_write state: flagb=1, the receiving thread producer is synchronously empty from equipment FIFO, FPGA by synchronous for data write from equipment FIFO;
(4), USB_in_write_wr_delay state: flagb=0, FX3 need the sampling write signal being in state of activation being carried out to two clock period, jump to USB_in_idle state afterwards.
3, firmware program
In order to realize the high speed data transfer of USB 3.0 interface, design firmware program is needed to be configured FX3.
3.1, GPIF II interface configuration
When carrying out FX3 firmware design, first need to be synchronous from equipment fifo interface by GPIF II interface configuration.CYPRESS company provides GPIF II Designer instrument and realizes GPIF II interface configuration, and its configuration flow as shown in Figure 6.GPIF II configuration data calls for firmware program as the bottom data of FX3 firmware program.
3.2, FX3 firmware structure
CYPRESS provides FX3SDK (Software Development Kit) and firmware structure, to develop USB firmware application in the ARM9 processor of FX3 inside.FX3 firmware structure is as shown in Figure 7:
(1), RTOS (Real Time Operating System): FX3 firmware embedded ThreadX Real Time OS (multithreading real time operating system), there is small scale, real-time, reliability is high, be easy to the features such as use, multiple thread can be created to simplify firmware flow process by RTOS;
(2), FX3API storehouse: FX3API (Application Programming Interface) storehouse provides a series of interface controlling to transmit with data with FX3 hardware implementing, comprises module and the ThreadX OS interfaces such as FX3, GPIF II, USB;
(3), FX3 firmware frame: FX3SDK provides a series of firmware frame generated based on API storehouse, comprise and starting and the driver of modules such as setup code and USB, GPIF II, the firmware program utilizing this firmware frame development of user to customize has very strong dirigibility, can shorten the R&D cycle;
(4), FX3 firmware program: the customized firmware program of satisfying the demand developed based on FX3 firmware frame and FX3API.FX3 firmware program comprises two parts: initialization subroutine and application subprogram.
3.3, initialization subroutine
Before the application firmware program of designing user customization, first need to carry out initialization to equipment, RTOS etc., firmware initialization subroutine process flow diagram as shown in Figure 8.
(1), FX3 firmware program first call function CyU3PFirmwareEntry () realize MMU (MemoryManagement Unit) and storehouse initialization, and eliminate invalid cache, this function is defined in FX3API storehouse and invisible to user;
(2), the function of CyU3PToolChainInit () function is initialization tools chain, realizes the initialization in storehouse and C language storehouse;
(3), device initialize: device initialize needs to perform following FOUR EASY STEPS:
1), device initialize: by calling CyU3PDeviceInit () function setup cpu clock, initialization VIC (VectoredInterrupt Controller) and configuration PLL (Phase Locking Loop);
2), equipment cached configuration: FX3 equipment has 8KB data buffer storage and 8KB order buffer memory, only needs enable command buffer memory;
3), I/O configuration: configure the various interface of FX3 (GPIF II, SPI, I2C, I2S, GPIO and UART), call CyU3PDeviceConfigureIOMatrix () and initialization is carried out to I/O matrix data structure;
4), call RTOS: call ThreadX OS operating system by CyU3PKernelEntry (), complete ThreadX OS initialization and OS clock is set.
(4), creating application thread: after initialization ThreadX OS, creating application program threads by calling CyFxApplicationDefine ().
3.4, user's application subprogram
After completing firmware initialization, call SlFifoAppThread_Entry () function and enter user's application subprogram.The application firmware subroutine of customization completes DMA passage, DMA buffer zone, USB transmission mode and from configurations such as equipment FIFO, realizes USB data transmission.User's application subprogram flow process as shown in Figure 9.
(1), Debug module initialization: call CyFxSlFifoApplnDebugInit () and realize Debug module initialization, Debug module need use UART to export Debug information, therefore first need initialization and configure UART state, calling CyU3PDebugInit () initialization Debug afterwards again and apply;
(2), customized application initialization: application initializes comprises two parts, GPIF II initialization and USB initialization, to be loaded into GPIF II register from equipment FIFO descriptor and start GPIF II state machine in GPIFII initialization, USB descriptor will be set in USB initialization, and create USB and connect with event and USB descriptor is set;
(3), process USB request: decoding USB request signal, processes and set up USB connection request and remove USB connection request etc.;
(4), USB event handling: USB comprises configuring request, resets and disconnects 3 kinds of events, starts USB transmission application when configuring request being detected, otherwise, stop USB application;
(5), start USB transmission application: configuring request detected, firmware starts USB transmission application, determines data package size and DMA buffer size, create DMA transmission channel according to USB transfer rate (FS/HS/SS);
(6), USB application is stopped: the request that resets/disconnect being detected, releasing memory, closedown DMA passage;
(7), USB to Processor (U2P) passage/Processor to USB (P2U) passage: call DMA function transfer data, owing to not requiring in the present invention that the data stream of FX3CPU to transmission is modified process, U2P/P2U passage will realize automatic DMA passage.
In order to realize the bidirectional data transfers of USB 3.0, need arrange 2 DMA passages in firmware: sendaisle is U2P passage, receiving cable is P2U passage.Because USB 3.0 interface in the design is only for data transmission, and carrying out data processing at FPGA, is therefore the automatic DMA passage that transfer rate is higher by DMA channel setting.USB supports four kinds of basic data-transmission modes: controls transfer, isochronous transfers, interrupt transfer and bulk transfer.Wherein, bulk transfer data stream, the idle bandwidth of usb bus is mainly utilized to carry out data transmission, can within the uncertain time transferring large number of data, be suitable for the occasion that data volume is large, the requirement of data transmission correctness is high, USB 3.0 data transmission mode setting is bulk transfer by the design in FX3 firmware.When carrying out FX3 firmware configuration, increasing U2P channel buffer size, suitably reducing P2U channel buffer size.In the design, each DMA buffer size is set to 16KB, and U2P passage DMA buffer count is 8, P2U passage DMA buffer count is 4.FX3 firmware program DMA channel setting as shown in Figure 10.
Because USB 2.0 and the firmware program Main Differences of USB 3.0 are DMA buffer size, in order to compatible USB 2.0 interface, when designing firmware program, connecting interface is judged, after being judged as USB 3.0 or USB 2.0 interface, corresponding DMA buffer zone is set.
Specific embodiment:
1, sendaisle:
1) host software that, CYPRESS company provides sends data;
2) data that, FX3 chip firmware process accepts host software sends also write from equipment FIFO;
3), USB 3.0 firmware program exports transmission state to USB 3.0 interface logic;
4), USB 3.0 interface logic sending module to get the hang of conversion, and detects FX3 firmware state;
5), USB 3.0 interface logic sending module reads data from FX3 chip from equipment FIFO;
2, receiving cable:
1), the host software transmission and reception request that provides of CYPRESS company;
2), USB 3.0 firmware program exports accepting state to USB 3.0 interface logic;
3), USB 3.0 interface logic receiver module gets the hang of conversion, receives data;
4), USB 3.0 interface logic receiver module will receive data write FX3 chip from equipment FIFO;
5), USB 3.0 drives reading FX chip from the data equipment FIFO and passes to host software.
The effect that the present invention reaches:
1, realize hypervelocity USB 3.0 interface, transfer rate can reach 2.5Gbps;
2, compatible USB 2.0 interface, can realize USB 2.0 interface communication between computing machine and FPGA;
3, the read-write sequence realizing USB 3.0 controller FX3 chip by control chip fpga logic controls;
4, interface logic is sent FIFO to dock with reception FIFO, can loop transfer be realized.
Claims (10)
1. based on USB 3.0 interface module of FPGA, it is characterized in that: this interface module adopts FPGA to realize logic control, and synchronously realize high speed data transfer from the data read-write operation of equipment FIFO by chip FX3 inside;
This interface module steering logic comprise USB 3.0 sending module, USB 3.0 receiver module, for cross clock domain operation transmission First Input First Output fifo module and for cross clock domain operation reception First Input First Output fifo module;
Described USB 3.0 sending module comprises following state:
USB_out_idle state: under this state, all registers of initialization and signal;
USB_out_flagc_rcvd state: when zone bit flagc=1 being detected, it is full for sending thread producer USB socket, that is: the data that USB sends detected, then start the transmission to data;
USB_out_wait_flagd state: postpone a clock period, waits the transmission thread producer to be detected synchronously full from equipment FIFO;
USB_out_read state: when zone bit flagd=1 being detected, sending thread synchronization is full from equipment FIFO, activates read control signal, and FPGA reads synchronous from equipment data fifo;
USB_out_read_rd_oe_delay state: as zone bit flagd=0, chip FX3 carries out the sampling of three clock period to the read signal being in state of activation, read signal and output enable signal effective all the time;
USB_out_read_oe_delay state: after chip FX3 completes and samples to the read signal being in state of activation, output enable signal demand jumps to USB_out_idle state after keeping four clock period;
Described USB 3.0 receiver module comprises following state:
USB_in_idle state: under this state, all registers of initialization and signal;
USB_in_wait_flagb state: as zone bit flaga=1, receiving thread consumer USB socket is empty, that is: USB does not send data, then start the reception to data;
USB_in_write state: when zone bit flagb=1 being detected, the receiving thread producer is synchronously empty from equipment FIFO, FPGA by synchronous for data write from equipment FIFO;
USB_in_write_wr_delay state: when zone bit flagb=0 being detected, chip FX3 carries out the sampling of two clock period to the write signal being in state of activation, jumps to USB_in_idle state afterwards.
2. USB 3.0 interface module based on FPGA according to claim 1, is characterized in that the model C YUSB3014 of chip FX3.
3. USB 3.0 interface module based on FPGA according to claim 2, it is characterized in that FPGA is connected with CYUSB3014 chip by GPIFII interface, the USB interface of CYUSB3014 chip is connected with Micro B interface, adopt I2C interface to guide to start, if I2C configuration failure, then usb mode configuration is used to start.
4. USB 3.0 interface module based on FPGA according to claim 3, is characterized in that also being embedded with jtag interface in CYUSB3014 chip, for as debugging interface.
5. USB 3.0 interface module based on FPGA according to claim 4, is characterized in that when carrying out FX3 firmware design, is first synchronous from equipment fifo interface by GPIF II interface configuration; GPIF II Designer instrument is adopted to realize GPIF II interface configuration.
6. USB 3.0 interface module based on FPGA according to claim 5, is characterized in that FX3 firmware program, FX3 firmware frame, FX3API storehouse and RTOS module;
Described RTOS module: for creating multiple thread;
FX3API storehouse: for providing the interface controlling with FX3 hardware implementing to transmit with data;
FX3 firmware frame: for the firmware program of development of user customization, comprises and starting and the driver of modules such as setup code and USB, GPIFII;
FX3 firmware program comprises initialization subroutine and application subprogram.
7. USB 3.0 interface module based on FPGA according to claim 6, is characterized in that the concrete manner of execution of initialization subroutine is:
FX3 firmware program first call function CyU3PFirmwareEntry () realizes MMU and storehouse initialization, and eliminates invalid cache;
CyU3PToolChainInit () function is used for initialization tools chain, realizes the initialization in storehouse and C language storehouse;
Device initialize: perform following FOUR EASY STEPS successively:
Steps A, device initialize: by calling CyU3PDeviceInit () function setup cpu clock, initialization VIC and configuration PLL;
Step B, equipment cached configuration: FX3 equipment has 8KB data buffer storage and 8KB order buffer memory, only needs enable command buffer memory;
Step C, I/O configure: the interface of configuration FX3, comprise: GPIF II interface, SPI interface, I2C interface, I2S interface, GPIO interface and UART interface, call CyU3PDeviceConfigureIOMatrix () and initialization is carried out to I/O matrix data structure;
Step D, call RTOS: call ThreadX OS operating system by CyU3PKernelEntry (), complete ThreadXOS initialization and OS clock is set;
Creating application thread: after initialization ThreadX OS, creating application program threads by calling CyFxApplicationDefine ().
8. USB 3.0 interface module based on FPGA according to claim 7, is characterized in that the concrete manner of execution of initialization subroutine is:
Debug module initialization: call CyFxSlFifoApplnDebugInit () and realize Debug module initialization, first initialization configure UART state, call CyU3PDebugInit () initialization Debug afterwards again and apply;
Customized application initialization: application initializes comprises two parts, GPIF II initialization and USB initialization, to be loaded into GPIF II register from equipment FIFO descriptor and start GPIF II state machine in GPIF II initialization, USB descriptor will be set in USB initialization, and create USB and connect with event and USB descriptor is set;
Process USB request: decoding USB request signal, process is set up USB connection request and is removed USB connection request;
USB event handling: USB comprises configuring request, resets and disconnects 3 kinds of events, starts USB transmission application when configuring request being detected, otherwise, stop USB application;
Start USB transmission application: configuring request detected, firmware starts USB transmission application, according to USB transfer rate determination data package size and DMA buffer size, creates DMA transmission channel;
Stop USB application: the request that resets/disconnect detected, releasing memory, closedown DMA passage;
USB to Processor passage/Processor to USB passage: call DMA function transfer data, U2P/P2U passage realizes automatic DMA passage.
9. USB 3.0 interface module based on FPGA according to claim 8, it is characterized in that in FX3 firmware, arrange two DMA passages: sendaisle is U2P passage, receiving cable is P2U passage, and these two DMA channel settings are the automatic DMA passage that transfer rate is higher.
10. USB 3.0 interface module based on FPGA according to claim 9, it is characterized in that the data-transmission mode of this USB 3.0 interface module is bulk transfer, when carrying out FX3 firmware configuration, increasing U2P channel buffer size, reducing P2U channel buffer size.
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| CN105786752A (en) * | 2016-01-22 | 2016-07-20 | 北京大学 | Method and system for USB communication between computing device and FPGA |
| CN106331452A (en) * | 2016-08-24 | 2017-01-11 | 宁波舜宇光电信息有限公司 | Device and method for performing image acquisition by utilizing synchronous slave SLAVEFIFO manner |
| CN106681944A (en) * | 2016-11-25 | 2017-05-17 | 南京美乐威电子科技有限公司 | FX3-FPGA (field programmable gate array) rapid starting method and FX3-FPGA rapid starting system based on single SPI (serial peripheral interface) flash memory |
| CN106851183A (en) * | 2015-12-04 | 2017-06-13 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN107391404A (en) * | 2016-05-16 | 2017-11-24 | 深圳市中兴微电子技术有限公司 | A kind of data transmission method and device based on hardware port |
| CN107590380A (en) * | 2017-08-17 | 2018-01-16 | 杰创智能科技股份有限公司 | A kind of high-speed space-time calculating platform |
| CN108631442A (en) * | 2018-05-28 | 2018-10-09 | 康桂文 | A kind of power transformer remote monitoring system based on optical fiber transmission |
| CN108647173A (en) * | 2018-08-01 | 2018-10-12 | 中国电子科技集团公司第三十四研究所 | A kind of synchronous start pulse signal regenerating unit and its operation method |
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| CN106851183B (en) * | 2015-12-04 | 2020-08-21 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN106851183A (en) * | 2015-12-04 | 2017-06-13 | 宁波舜宇光电信息有限公司 | Multi-channel video processing system and method based on FPGA |
| CN105718410A (en) * | 2016-01-19 | 2016-06-29 | 山东超越数控电子有限公司 | Adaptor for converting LPC (Low Pin Count) into SPI (Serial Peripheral Interface) and I2C based on FPGA (Field-Programmable Gate Array) and realizing method of adaptor |
| CN105718410B (en) * | 2016-01-19 | 2018-05-18 | 山东超越数控电子有限公司 | A kind of LPC based on FPGA and SPI and I2C conversion adapters and its implementation |
| CN105786752B (en) * | 2016-01-22 | 2018-08-28 | 北京大学 | Usb communication method and communication system between a kind of computing device and FPGA |
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| CN106681944A (en) * | 2016-11-25 | 2017-05-17 | 南京美乐威电子科技有限公司 | FX3-FPGA (field programmable gate array) rapid starting method and FX3-FPGA rapid starting system based on single SPI (serial peripheral interface) flash memory |
| WO2018188404A1 (en) * | 2017-04-14 | 2018-10-18 | 中兴通讯股份有限公司 | Usb device configuration method and host |
| CN107590380A (en) * | 2017-08-17 | 2018-01-16 | 杰创智能科技股份有限公司 | A kind of high-speed space-time calculating platform |
| CN107590380B (en) * | 2017-08-17 | 2020-05-22 | 杰创智能科技股份有限公司 | High-speed space-time computing platform |
| CN108631442A (en) * | 2018-05-28 | 2018-10-09 | 康桂文 | A kind of power transformer remote monitoring system based on optical fiber transmission |
| CN108647173A (en) * | 2018-08-01 | 2018-10-12 | 中国电子科技集团公司第三十四研究所 | A kind of synchronous start pulse signal regenerating unit and its operation method |
| CN108647173B (en) * | 2018-08-01 | 2023-08-01 | 中国电子科技集团公司第三十四研究所 | Synchronous trigger pulse signal regeneration device and operation method thereof |
| CN109446134A (en) * | 2018-09-18 | 2019-03-08 | 天津大学 | A kind of USB high-speed interface based on FPGA |
| CN109359083A (en) * | 2018-09-27 | 2019-02-19 | 浙江大学 | The hardware implementation method of restructural series bus controller in a kind of chip |
| CN110069435A (en) * | 2019-05-07 | 2019-07-30 | 珠海达明科技有限公司 | Turn the more camera module configuration devices and method of SCCB based on USB3.0 |
| CN110941583A (en) * | 2019-12-10 | 2020-03-31 | 云南大学 | USB3.0 data transmission system control method based on FPGA |
| WO2022088542A1 (en) * | 2020-11-02 | 2022-05-05 | 芯启源(上海)半导体科技有限公司 | Fpga-based usb3.0/3.1 control system |
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