WO2015024414A1

WO2015024414A1 - Chip and method for debugging mcu by using i2c slave device

Info

Publication number: WO2015024414A1
Application number: PCT/CN2014/080725
Authority: WO
Inventors: 郭正伟; 王光耀
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2013-08-22
Filing date: 2014-06-25
Publication date: 2015-02-26
Also published as: CN103440216B; CN103440216A

Abstract

Disclosed are a chip and a method of debugging an MCU by using I2C slave device. The present invention relates to the technical field of electronic circuits. The chip comprises: an I2C bus, an MCU connected through the ICU bus, an I2C slave device, and at least two peripheral units. The I2C slave device is further configured to enter or exit an MCU debugging mode under the control of an I2C master device outside the chip. By means of embodiments of the present invention, an I2C slave device can further be used as a debugging interface without affecting a general function of the I2C slave device, a debugging function can be performed without additionally adding another debugging interface, thereby reducing consumption of resources.

Description

A chip and method for debugging an MCU through an I2C slave device

Technical field

The present invention relates to the field of electronic circuit technologies, and in particular, to a chip and method for debugging an MCU through an I2C slave device. Background technique

In traditional chip systems, I2C slaves are typically used as general purpose data transfer interfaces. The external communication and debugging of the chip and the MCU mainly use JTAG, UART, etc., so that when the chip does not integrate JTAG, UART and other interfaces, additional interfaces are added for debugging, which wastes system resources. Summary of the invention

In view of this, the technical problem to be solved by the present invention is to provide a chip and a method for debugging an MCU through an I2C slave device, so that the I2C slave device can stop and release the MCU at any time, and can perform a handshake operation with a program executed by the MCU. The I2C slave device is used to implement peripheral debugging of the MCU, saving system resources and making debugging more flexible.

The technical solution adopted by the present invention to solve the above technical problems is as follows:

According to an aspect of the present invention, a chip for debugging an MCU through an I2C slave device includes an I2C bus, an MCU connected through an I2C bus, an I2C slave device, and two or more peripheral devices, wherein the I2C slave device is further used for Enter or exit the mode of debugging MCU under the control of the external I2C master of the chip.

Preferably, the I2C slave device includes an I2C finite state machine, a command parsing module, an I2C interrupt processing module, an I2C register, a FIFO write module, and a FIFO read module, wherein the command parsing module, the I2C interrupt processing module, the I2C register, the FIFO write module, and The FIFO read module is connected to the I2C finite state machine, and the FIFO write module and the FIFO read module are also respectively connected to the command parsing module, and the I2C register is also connected to the I2C interrupt processing module;

The I2C slave device further includes a mode control module, and the mode control module is respectively connected to the command parsing module and the I2C finite state machine, and is configured to receive the first predetermined character string sent by the command parsing module, and then send the stop MCU to the instruction state machine of the MCU. Signal, and wait for a predetermined number of system clock cycles after occupying The bus handshaking between the I2C master device external to the chip and the program executed by the MCU; and is further configured to: after receiving the second predetermined character string sent by the command parsing module, release the bus, and send a signal for releasing the MCU to the instruction state machine of the MCU. .

Preferably, the debug control module comprises:

a monitoring unit, configured to monitor whether a first predetermined character string or a second predetermined character string is received;

The MCU control unit is configured to: after receiving the first predetermined character string, send a signal for stopping the MCU to the instruction state machine of the MCU; and further, after receiving the second predetermined character string, send the release to the instruction state machine of the MCU. MCU signal.

The bus control unit is configured to: after receiving the first predetermined character string, wait for a predetermined number of system clock cycles to occupy the bus; and further, after receiving the second predetermined character string, release the bus.

Preferably, the debug control module comprises:

String register 701, comparator 702, first flip flop 703, first NOT gate 704, second NOT gate 705, first AND gate 706, second AND gate 707, first OR gate 708, counter 709, first MUX 710, second MUX 71 second OR gate 712, second flip-flop 713, third AND gate 714, and third flip-flop 715, wherein:

a string register 701, configured to receive a string written by the I2C master device;

The comparator 702 is configured to compare the string of the string register 701 with the preset string, and output a high level or low level signal to the first flip flop 703 according to the comparison result;

The first trigger 703 is configured to register the result of the comparator 702 once, and output to the first NOT gate 704 and the second AND gate 707;

The first NOT gate 704 is configured to invert the output of the first flip-flop 703 and then output to the first AND gate

706;

The first AND gate 706 is configured to perform an AND operation according to the comparison result of the comparator 702 and the result of the first NOT gate 704, for grabbing the rising edge of the signal output by the comparator 702, and when the rising edge thereof comes, generating a The high pulse of the cycle is output to the first OR gate 708;

a second NOT gate 705 for inverting the output of the comparator 702 and then outputting to the second AND gate 707; a second AND gate 707; for outputting according to the second NOT gate 705 and the output of the first flip-flop 703 Performing an AND operation for grabbing the falling edge of the output signal of the comparator 702, and when its falling edge comes, generating a high pulse signal of one cycle is output to the first OR gate 708;

a first OR gate 708 for continuing the two from the first AND gate 706 and the second AND gate 707 The high pulse signal of the cycle is output to the counter 709;

The counter 709 is configured to start a pulse count of the clock cycle according to a high pulse signal of one cycle from the first OR gate 708, and output a pulse of one clock cycle to the first MUX 710 and the second MUX after the counting is completed. 711 ;

The first MUX 710 is configured to select whether to output the low level or the output value of the second flip-flop 713 as an input of the second OR gate 712. When the output of the counter 709 is high, select the low level as the output, otherwise, Selecting an output value of the second flip-flop 713 as an output;

The second MUX 711 is configured to select whether to output the high level or the output value of the third flip-flop 715 as an input of the third AND gate 714. When the output of the counter 709 is high, select the high level as the output, otherwise, Selecting an output value of the third flip-flop 715 as an output;

The second OR gate 712 and the second flip-flop 713 are configured to generate a signal for stopping the MCU. When the output of the comparator 702 transitions to high, the output thereof is correspondingly turned high, and remains high until the comparator When the output of 702 transitions to low, and the counter 709 thus triggered counts and the high pulse of one cycle generated by the end of the counting comes, the output is pulled low;

The third AND gate 714 and the third flip-flop 715 are configured to generate a signal that the I2C occupies the bus, when the output of the comparator 702 transitions to high, and the counter 709 thus triggered counts and the count ends, a mid-term high When the pulse arrives, its output transitions high and remains high until the output of comparator 702 goes low, pulling its output low.

Preferably, the handshake of the I2C master device external to the chip and the program executed by the MCU includes: control of the read or write operation of the peripheral by the I2C master device outside the chip.

Preferably, the predetermined number of system clock cycles is determined based on the number of clock cycles required by the MCU to perform the longest execution of its instruction set.

Preferably, the on-chip peripherals include: a read register, a write register, a program memory, and/or a data memory.

According to another aspect of the present invention, a method for debugging an MCU through an I2C slave device is provided:

After receiving the first predetermined character string from the device, the I2C first sends a signal to the MCU's instruction state machine to stop the MCU;

Waiting for a predetermined number of system clock cycles, occupying the bus for the I2C master device outside the chip to handshake with the program executed by the MCU; After receiving the second predetermined character string, the bus is released first, and then the signal of the release MCU is sent to the instruction state machine of the MCU.

Preferably, the handshake of the I2C master device external to the chip and the program executed by the MCU includes: the I2C master device outside the chip controls the read or write operation of the chip peripheral device.

The invention provides a chip and a method for debugging an MCU through an I2C slave device, so that the I2C slave device can access all peripheral devices in the chip while not affecting the general functions of the I2C slave device, and can also stop and The MCU is released, and the debugging interface is used to implement the function of debugging and MCU handshake of the MCU of the chip by the external I2C master device. In the case that the chip system has the function of the I2C slave device, the debugging function can be realized without additional debugging interface, and the resource consumption is saved. DRAWINGS

FIG. 1 is a schematic diagram of control of a chip for debugging an MCU through an I2C slave device according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of an I2C slave device according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a mode control module according to an embodiment of the present invention.

4 is a circuit timing diagram of an embodiment of the preferred invention.

FIG. 5 is a flowchart of a method for debugging an MCU by using an I2C slave device according to an embodiment of the present invention. FIG. 6 is a flow chart of a method for debugging an MCU through an I2C slave device according to a preferred embodiment of the present invention. detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Embodiment 1

1 is a control schematic diagram of a chip for debugging an MCU through an I2C slave device according to an embodiment of the present invention. The system includes a chip 10 and an I2C master device 20, wherein:

Chip 10, including I2C bus 101, MCU 102, I2C slave device 103 and more than two peripherals 104. The MCU 102, the I2C slave device 103 and the peripheral device 104 are connected through the I2C bus 101.

The I2C bus 101 and the MCU 102 belong to the prior art. In addition to maintaining the existing universal data transmission interface function, the I2C slave device 103 can also be used as a debugging interface to enter or exit the debugging MCU under the control of the external I2C master device 20 of the chip. The mode is thus chosen to be used for a general data transfer interface or a debug interface. Peripherals 104 are also conventional and include, but are not limited to, read registers, write registers, program memory, and data memory.

The I2C master device 20 is configured to control the I2C slave device 103 of the chip 10 as a general data transmission interface or a debug interface by transmitting a preset character string.

Specifically, when the I2C master device 20 needs to debug the MCU 102 or access the peripheral device 104 in the chip, the preset first character string is sent to the chip internal I2C slave device 103, and the I2C slave device 103 receives the preset. After the first string, the MCU 102 is stopped first, and all its states are kept unchanged, and then the I2C bus 101 is occupied. At this time, the external I2C master device 20 can complete any operations required; after the operation is completed, the external After the I2C master device 20 receives the second character string preset by the internal I2C slave device 103, and after the I2C slave device 103 receives the preset second character string, the I2C bus 101 is released first, and then the MCU 102 is released. The internal I2C slave device 103 can control all of the internal peripherals 104 of the chip like the MCU 102, so that all debugging work is transparent to the MCU 102, and the MCU 102 can continue to execute correctly after being released. FIG. 2 is a schematic structural diagram of an I2C slave device according to an embodiment of the present invention, including an I2C finite state machine 1031, a command parsing module 1032, an I2C interrupt processing module 1033, an I2C register 1034, a FIFO write module 1035, and a FIF0 read. Module 1036 and mode control module 1037, command parsing module 1032, I2C interrupt processing module 1033, I2C register 1034, FIF0 write module 1035, and FIFO read module 1036 are all coupled to I2C finite state machine 1031, FIFO write module 1036 and FIFO read module 1036. Also connected to the command parsing module 1032, the I2C register 1034 is also connected to the I2C interrupt processing module 1033; the mode control module 1037 is connected to the I2C finite state machine 1031 and the command parsing module 1032, respectively:

The I2C Finite State Machine 1031 is used to control the working state of the I2C slave device and receive and transmit data with the I2C master device.

Command Decode 1032 is used to parse commands received by the I2C slave device. I2C interrupt processing module (Interrupts) 1033, used for interrupt control of I2C slave devices, which is a common communication function of I2C slave devices.

The I2C register (Registers) 1034 is used for the interaction between the I2C slave device and the MCU, which is a common communication function of the I2C slave device.

The FIFO write module 1035 is used for I2C slave device write control of the on-chip peripherals.

The FIFO write module 1036 is used for I2C slave device read control of the on-chip peripherals.

The mode control module 1037 is configured to: after receiving the first predetermined character string sent by the command parsing module 1032, send a signal for stopping the MCU to the instruction state machine of the MCU, and wait for a predetermined number of system clock cycles to occupy the bus. The I2C master device external to the chip performs a handshake with the program executed by the MCU; and is further configured to: after receiving the second predetermined character string sent by the command parsing module 1032, release the bus, and send the release MCU to the instruction state machine of the MCU. signal.

Here, waiting for the predetermined number of system clock cycles is to enable the MCU to have enough time to execute the currently executing instruction, so the predetermined number of clock cycles can be based on the clock cycle required by the MCU to execute the longest execution in its instruction set. Number to determine.

The mode control module 1037 can be implemented by a hardware circuit or by running a software program on the I2C slave device. Divided by functional modules, the mode control module may include: a monitoring unit, an MCU control unit, and a bus control unit, where:

a monitoring unit, configured to monitor whether a first predetermined character string or a second predetermined character string is received; the MCU control unit, configured to send the MCU to the instruction state machine of the MCU after receiving the first predetermined character string The signal is further configured to send a signal for stopping the MCU to the instruction state machine of the MCU after receiving the second predetermined character string.

The I2C slave device provided in this embodiment controls the stop or release operation of the MCU and the complete occupation or release of the bus during the MCU being stopped by adding the mode control module, thereby controlling the entry or exit of the debugging. The MCU mode enables the I2C slave device to act as a general data transfer interface or debug interface as needed. FIG. 3 is a schematic structural diagram of a mode control module according to an embodiment of the present invention. The module includes: a string register 701, a comparator 702, a first flip-flop 703, and a first NOT gate 704. Second NOT gate 705, first AND gate 706, second AND gate 707, first OR gate 708, counter 709, first

MUX (multiplexer) 710, second MUX 711, second OR gate 712, second flip-flop 713, third AND gate 714, and third flip-flop 715, wherein:

The comparator 702 is configured to compare whether the character string of the string register 701 is the same as the preset character string, and output a high level or a low level signal according to the comparison result (in the logic structure shown in the figure, both are high-powered The level is valid as an example, but it can also be set to be active low. When the active low level is set, the subsequent circuits are reversely adjusted) to the first flip-flop 703;

706;

The first AND gate 706 is configured to perform an AND operation according to the comparison result of the comparator 702 and the result of the first NOT gate 704 for grabbing the rising edge of the signal output by the comparator 702 (because the example image is high in comparison result) The circuit structure diagram of the level effective mode design, when its rising edge (ie, the comparison result is changed from unequal to equal), a high pulse output of one cycle is generated to the first OR gate 708;

a second NOT gate 705 for inverting the output of the comparator 702 and then outputting to the second AND gate 707; a second AND gate 707; for outputting according to the second NOT gate 705 and the output of the first flip-flop 703 Performing an AND operation to capture the falling edge of the output signal of the comparator 702 (because the example figure is a circuit structure diagram designed in a highly efficient manner of comparison), when its falling edge (ie, the comparison result is changed from equal to unequal) When coming, generate a cycle of high pulse signal output to the first OR gate 708;

a first OR gate 708 for outputting two high pulse signals from the first AND gate 706 and the second AND gate 707 for one cycle to a subsequent counter 709;

The counter 709 is configured to start a pulse counting of the clock cycle according to a high pulse signal of one cycle from the first OR gate 708, and output a pulse of one clock cycle to the first MUX 710 and the second MUX 711 after the counting is completed. . Among them, the number of counting cycles is to ensure that the longest instruction of the MCU can be executed as a standard.

The first MUX 710 is configured to select whether to output a low level ("0") or an output value of the second flip-flop 713 as an input of the following second OR gate 712. When the output of the counter 709 is high, select low. Level as an output, otherwise, the output value of the second flip-flop 713 is selected as an output; The second MUX 711 is configured to select whether to output a high level ("1") or an output value of the third flip-flop 715 as an input of the following third AND gate 714. When the output of the counter 709 is high, select high. Level as an output, otherwise, the output value of the third flip-flop 715 is selected as an output;

The second OR gate 712 and the second flip-flop 713 are configured to generate a signal for stopping the MCU. In this example, the signal is high-efficiency as an example. When the output of the comparator 702 transitions to high (ie, equal), its output The corresponding transition is high and remains high until the output of comparator 702 transitions low (ie, unequal), and the counter 709 thus triggered counts and the high pulse of one cycle resulting from the end of the count arrives, Pull its output low;

a third AND gate 714 and a third flip-flop 715 for generating a signal that the I2C occupies the bus. In this example, the signal is exemplified by high efficiency, when the output of the comparator 702 transitions high (ie, equal), and When the counter 709 thus triggered counts and the mid-high pulse generated by the end of the count comes, its output transitions to high and remains high until the output of comparator 702 transitions low (ie, not equal). When you pull its output low.

The mode control module of this embodiment is merely illustrative. In this example, all signals are designed with high efficiency as the premise, including the intermediate signal in the circuit implementation process and the final output signal (stopping the MCU signal and occupying the bus signal). The corresponding circuit waveform diagram is shown in Fig. 4. The double slash "〃" in Fig. 4 indicates that several cycles are omitted, and the specific situation is determined by the designer. In a specific implementation, as long as the correspondence between the output of the comparator 702 of the string sequence and the output signal (stopping the MCU signal and occupying the bus signal) can be ensured, other parts can be replaced; the input, the output signal, and the middle Whether the signal is active high or low is valid by the designer. FIG. 5 is a flowchart of a method for debugging an MCU by using an I2C slave device according to an embodiment of the present invention, where the method includes:

After receiving the first preset character string, the S50U I2C sends a signal to stop the MCU to the instruction state machine of the MCU;

5502. After waiting for a predetermined number of system clock cycles, occupy the bus for the I2C master device outside the chip to handshake with the program executed by the MCU;

5503. After receiving the second predetermined character string, release the bus, and send a signal for releasing the MCU to the instruction state machine of the MCU.

The method of this example can be implemented by a hardware circuit or by running on an I2C slave device. Software program to achieve. When the I2C slave detects the first predetermined character string sent by the I2C master device, stops the MCU first, keeps all its states unchanged, and then occupies the bus. At this time, the I2C master device can complete any required After the operation is completed, the I2C master device sends a second predetermined string to the internal I2C slave device. After the I2C slave device detects the second predetermined string, the bus is released and the MCU is released. All debugging work is transparent to the MCU, and the MCU can continue to execute the next instruction of the executed instruction before it is released. FIG. 6 is a flowchart of a method for debugging an MCU by using an I2C slave device according to a preferred embodiment of the present invention, where the method includes:

5601, I2C slave device maintains common functions;

5602. Determine whether the predetermined first character string is received. If yes, execute step S603; otherwise, return to step S601;

S603. Send a signal for stopping the MCU to the instruction execution state machine of the MCU.

5604. Wait for a predetermined clock cycle, suspending the MCU;

5605, occupying the bus for use by the I2C master device;

5606. The I2C master device performs an operation.

5607. The I2C master device sends a second preset character string.

5608, I2C slave bus releases the bus;

5609. Send a signal for releasing the MCU to the instruction state machine of the MCU.

5610. The MCU continues to perform the original function, and then proceeds to step S601.

The preferred embodiments of the present invention have been described above with reference to the drawings, and are not intended to limit the scope of the invention. A person skilled in the art can implement the invention in various variants without departing from the scope and spirit of the invention. For example, the features of one embodiment can be used in another embodiment to obtain a further embodiment. Any modifications, equivalent substitutions and improvements made within the technical concept of the invention are intended to be included within the scope of the invention. Industrial applicability

The invention provides a chip and a method for debugging an MCU through an I2C slave device, so that the I2C slave device can access all peripheral devices in the chip while not affecting the general functions of the I2C slave device, and can also stop and Release the MCU and use the debug interface to implement the external I2C master device to the MCU of the chip. The function of line debugging and MCU handshake. In the case that the chip system has the function of the I2C slave device, the debugging function can be realized without adding another debugging interface, and the resource consumption is saved.

Claims

claims

1. A chip for debugging an MCU through an I2C slave device. The chip includes an I2C bus, an MCU, an I2C slave device and two or more peripherals connected through the I2C bus, wherein the I2C slave device is also used for Enter or exit the debugging MCU mode under the control of the external I2C master device of the chip.

2. The chip according to claim 1, wherein the I2C slave device includes an I2C finite state machine, a command parsing module, an I2C interrupt processing module, an I2C register, a FIFO writing module and a FIFO reading module, wherein the command parsing module, the I2C interrupt processing module, the I2C register, the FIFO writing module and the FIFO reading module are all connected to the I2C finite state machine, and the FIFO writing module and the FIFO reading module are also connected to the FIFO reading module respectively. The command parsing module is connected, and the I2C register is also connected to the I2C interrupt processing module;

The I2C slave device also includes a mode control module, which is connected to the command parsing module and the I2C finite state machine respectively, and is used to receive the first predetermined string sent by the command parsing module, Send a signal to stop the MCU to the instruction state machine of the MCU, and after waiting for a predetermined number of system clock cycles, occupy the bus for the I2C master device outside the chip to shake hands with the program executed by the MCU; also used to receive the command After parsing the second predetermined string sent by the module, the bus is released, and a signal to release the MCU is sent to the instruction state machine of the MCU.

3. The chip according to claim 2, wherein the debugging control module includes:

The monitoring unit is used to monitor whether the first predetermined character string or the second predetermined character string is received; the MCU control unit is used to send a message to the MCU's instruction state machine to stop the MCU after receiving the first predetermined character string. Signal; also used to send a signal to release the MCU to the instruction state machine of the MCU after receiving the second predetermined string.

The bus control unit is configured to wait for a predetermined number of system clock cycles before occupying the bus after receiving the first predetermined string; and to release the bus after receiving the second predetermined string.

4. The chip according to claim 2, wherein the debugging control module includes:

String register (701), comparator (702), first flip-flop (703), first NOT gate (704), second NOT gate (705), first AND gate (706), second AND gate (706) 707), first OR gate (708), counter (709), first MUX (710), second MUX (711), second OR gate (712), second flip-flop (713), third AND gate (714) and the third flip-flop (715), where: String register (701), used to receive strings written by the I2C master device;

The comparator (702) is used to compare whether the string in the string register (701) is the same as the preset string, and output a high level or low level signal to the first flip-flop (703) according to the comparison result; the first Flip-flop (703), used to register the result of the comparator (702) once and output it to the first NOT gate (704) and the second AND gate (707);

The first NOT gate (704) is used to invert the output of the first flip-flop (703), and then output it to the first AND gate (706);

The first AND gate (706) is used to perform an AND operation based on the comparison result of the comparator (702) and the result of the first NOT gate (704), and is used to capture the rising edge of the signal output by the comparator (702). When When its rising edge arrives, a period of high pulse is generated and output to the first OR gate (708);

The second NOT gate (705) is used to invert the output of the comparator (702), and then output it to the second AND gate (707);

The second AND gate (707) is used to perform an AND operation based on the output of the second NOT gate (705) and the output of the first flip-flop (703), and is used to capture the falling edge of the output signal of the comparator (702), When its falling edge arrives, a periodic high pulse signal is generated and output to the first OR gate (708);

The first OR gate (708) is used to output two high pulse signals lasting one cycle from the first AND gate (706) and the second AND gate (707) to the counter (709);

The counter (709) is used to start pulse counting of a clock cycle based on the high pulse signal lasting one cycle from the first OR gate (708) as a trigger condition, and after the counting is completed, output a pulse of a clock cycle to the first MUX (710 ) and the second MUX (711);

The first MUX (710) is used to select whether to output a low level or the output value of the second flip-flop (713) as an input of the second OR gate (712). When the output of the counter (709) is high, select The low level is used as the output, otherwise, the output value of the second flip-flop (713) is selected as the output;

The second MUX (711) is used to select whether to output a high level or the output value of the third flip-flop (715) as an input of the third AND gate (714). When the output of the counter (709) is high, select High level is used as the output, otherwise, the output value of the third flip-flop (715) is selected as the output;

The second OR gate (712) and the second flip-flop (713) are used to generate a signal to stop the MCU. When the output of the comparator (702) changes to high, its output correspondingly changes to high and remains high. The output is high until the output of the comparator (702) changes to low and the counter (709) triggered thereby counts and the high pulse of one cycle generated when the counting ends arrives, and its output is pulled low; The third AND gate (714) and the third flip-flop (715) are used to generate a signal that the I2C occupies the bus. When the output of the comparator (702) transitions to high, and the counter (709) triggered thereby counts and counts When a mid-term high pulse generated at the end arrives, its output correspondingly changes to high, and remains high until the output of the comparator (702) changes to low, and its output is pulled low.

5. The chip according to claim 2, wherein the handshake between the I2C master device outside the chip and the program executed by the MCU includes: the I2C master device outside the chip controls the read or write operation of the peripheral device.

6. The chip according to claim 2, wherein the predetermined number of system clock cycles is determined based on the number of clock cycles required by the MCU to execute the longest one in its instruction set.

7. The chip according to any one of claims 1 to 6, wherein the internal peripherals of the chip include: read registers, write registers, program memory, and/or data memory.

8. A method of debugging MCU through I2C slave device, wherein the method includes:

After the I2C slave device receives the first predetermined string, it first sends a signal to the MCU's command state machine to stop the MCU;

After waiting for a predetermined number of system clock cycles, the bus is occupied for handshaking between the I2C master device outside the chip and the program executed by the MCU;

After receiving the second predetermined string, the bus is first released, and then a signal to release the MCU is sent to the instruction state machine of the MCU.

9. The method of claim 8, wherein the predetermined number of system clock cycles is determined based on the number of clock cycles required by the MCU to execute the longest one in its instruction set.

10. The method according to claim 8, wherein the handshake between the I2C master device outside the chip and the program executed by the MCU includes: the I2C master device outside the chip controls the read or write operation of the chip peripherals.