CN103810127B - USB low-speed devices data transfer control method and controller - Google Patents

USB low-speed devices data transfer control method and controller Download PDF

Info

Publication number
CN103810127B
CN103810127B CN201210453547.8A CN201210453547A CN103810127B CN 103810127 B CN103810127 B CN 103810127B CN 201210453547 A CN201210453547 A CN 201210453547A CN 103810127 B CN103810127 B CN 103810127B
Authority
CN
China
Prior art keywords
packet
signal wires
host computer
computer side
token
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210453547.8A
Other languages
Chinese (zh)
Other versions
CN103810127A (en
Inventor
张妍彦
赵远鸿
康利云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen ZTE Microelectronics Technology Co Ltd
Original Assignee
Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen ZTE Microelectronics Technology Co Ltd filed Critical Shenzhen ZTE Microelectronics Technology Co Ltd
Priority to CN201210453547.8A priority Critical patent/CN103810127B/en
Priority to PCT/CN2013/085995 priority patent/WO2014075545A1/en
Publication of CN103810127A publication Critical patent/CN103810127A/en
Application granted granted Critical
Publication of CN103810127B publication Critical patent/CN103810127B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a kind of USB low-speed devices data transfer control method and controller.This method includes:When transmitting beginning, the D+ signal wires and D signal wires of USB low-speed devices are detected, if D+ signal wires and D signal wires are in idle condition, D+ signal wires are drawn high;After host computer side drags down D+ signal wires, reset state is directly entered, and draw high D+ signal wires;After the completion of host computer side reset, control data transmission channel EP simultaneously carries out data transmission with host computer side, and after the end of transmission, D+ signal wires and D signal wires are disposed as into idle condition.By means of technical scheme, the USB device of former compatibility USB low speed is set only to support the peripheral functionality of USB low speed, the area of controller reduces 50%, and according to the USB interface communication that correctly realizes between physical layer of protocol requirement transmit and transmission in the detection of passage shake hands.

Description

USB low-speed devices data transfer control method and controller
Technical field
The present invention relates to field of mobile communication, more particularly to a kind of USB(IntelUniversalSeria L Bus, referred to as USB)Low-speed device data transfer control method and controller.
Background technology
USB is widely known data transmission interface, and first draft is born so far from November, 1994, USB interface with Its plug and play(Plug&Play), simple interface circuit, low cost and the characteristics of fast transmission speed, it has also become it is nearly all The standard of the electronic equipment carried out data transmission is needed to be equipped with;Application field includes personal computer, consumption and mobile class product Fast synchronization instantaneous transmission;USB interface develop into today it is most widely used be two versions of USB2.0 and USB3.0, USB3.0 Backward compatible USB2.0, the performance comparison of the two is as shown in table 1:
Table 1
In the prior art, USB device type(device class)Some USB essential characteristic will be shown, But USB device is still segmented into some common types, the equipment of same type can possess some common behavioural characteristics and Operating protocol, table 2 is classified for some basic USB device type.
Table 2
Device type(device class) Equipment is illustrated
Audio(audio) Loudspeaker
Communication MODEM
Human interface device(HID) Keyboard, mouse
Image Video camera, scanner
Display Monitor
Physics responds equipment Dynamic feedbacks formula game operation bar
Power supply Uninterrupted power source is powered
Printer apparatus class Printer
Bulk memories Hard disk
Storage device class CD_ROM, mobile hard disk
From Table 2, it can be seen that USB human interface devices(Human Interface Device, referred to as HID)Class is One than larger class, HID classes be mainly used in computer operation some aspect, for example:USB mouse, USB keyboard, USB game Action bars, USB touch pads, USB trace balls, dialing equipment, analog tape recorder and reproducer(Video Cassette Recorder, referred to as VCR)The equipment such as remote control;There is referred to as form in HID exchange data storage(report)Structure in. Main frame is sent and request form in controlling transmission and interruption transmission, so as to send and receive data, report tableau format has very much Elasticity, can handle any kind of data;Equipment can send information to main frame in the unexpected time, for example:Keyboard The movement of button or mouse, so main frame meeting automatic regular polling equipment, to obtain newest data;For HID device, its Transmission speed is 1.5Mbps, belongs to low-speed peripheral;In most USB2.0 devices, low-speed peripheral is all as compatible Device exist, but for HID device, it is only necessary to the apparatus of low speed, therefore on the basis of USB2.0 USB low-speed peripheral part is extracted, USB high speeds, full speed and function limitation main frame is removed(OTG)Function so that USB's Low-speed peripheral devices area is smaller, more efficient;Design a kind of low speed(LS)Transmission external device be a kind of preferable scheme.
The concrete application target of USB LS transmission external device includes:The LS peripheral hardwares transmission control of protocol layer is realized, is led to Cross UTMI(USB2.0 Transceiver Macrocell Interface)During interface and physical layer carry out data transmission Control and error detection, carry out physical layer and internal damping register(buffer)Data exchange, it is total by advanced microcontroller Line(Advanced Microcontroller Bus Architecture, referred to as AMBA)Advanced High-Performance Bus (Advanced High performance Bus, referred to as AHB)Interface and nuclear control device are communicated, so as to complete basic Bulk IN/OUT, controlling transmission and interrupt transmission etc..
Fig. 1 is the module diagram of USB LS in the prior art, as shown in figure 1, mainly including UTM data syn-chronizations, Bao Xie Code and decoding, RAM controls, data transmission channel(EP)Control, four parts of cpu i/f;Due to usual physical layer clock and The clock of controller is not belonging to same clock zone, so data carry out data syn-chronization, subsequent decoding/decoding mould by UTM first Block processing transmission bag, includes processing, data transfer and the CRC check in packet header;EP is the data transmission pipe in USB, EP controls The control of molding block is divided into general EP controls and EP0 controls two parts, EP controls when carrying out data transmission;Cpu i/f allows CPU By the control inside bus access device, status register, and each EP FIFO, cpu i/f can support 32bit's Data;The access of single port RAM between RAM control modules control USB and CPU.
USB2.0 of the prior art controller can support high speed, full-speed/low-speed, and can be used as main frame (HOST)And equipment(DEVICE), or function limitation main frame(OTG), such controller can complete USB2.0 agreements regulation Major function, its basic state of a control machine step is as follows(It is abnormal unlisted):
When step 1, transmission start, D+/D- signal wires are detected, if the two is in idle condition, the ID of itself, root are detected According to physical layer(Physical Layer, referred to as PHY)The data of offer, it can be determined that controller oneself be DEVICE or HOST, if HOST, into step 2;Otherwise, into step 5;Wherein, D+ signal wires and D- signal wires are USB user data The differential lines of transmission.
Step 2, HOST are by controlling UTMI signal wires, the operation that D+/D- lines are drawn high and dragged down by PHY, with DEVICE is attached;Into step 3;
Reset operation is carried out after step 3, successful connection, the process of reset can be by DEVICE ends on D+/D- lines Operation judges DEVICE is any speed;Into step 4;
After the completion of step 4, reset, controller is controlled the transmission of information and packet according to the speed judged;Pass It is defeated to terminate, IDLE state is returned to, wait is transmitted next time;
If step 5, detecting controller for DEVICE, OTG pattern can be entered, SRP is initiated(USB2.0 OTG associations Wake-up part in view), wake operation is carried out to HOST side, after main frame is successfully waken up, controller exits OTG patterns, with HOST sides are attached;Into step 6;
Step 6, main frame and DEVICE connections, DEVICE carry out reset operation according to the speed of register configuration, if At a high speed, then DEVCIE can draw high D- lines first, represent to reset at a high speed, if full speed and low speed, then DEVICE can be first D+ lines are drawn high, represent that full-speed/low-speed resets;Into step 7;
After the completion of step 7, reset, HOST is controlled the transmission of information and packet according to the speed judged;DEVIE Controller receives command token bag, is responded according to order bag, for example, transmission packet or the information such as shake hands, enter simultaneously The judgement that row packet is correctly transmitted, including:Whether CRC check, transmission packet meets requirement of transport-type etc. in agreement; The end of transmission, returns to IDLE state, and wait is transmitted next time.
It can be seen that in the prior art from above-mentioned processing, USB LS control is all together with the state machine of full speed Complete, so for only requiring that LS equipment wastes substantial amounts of design resource, the peripheral hardware for only needing the LS with USB For, and do not need function at full speed with high speed.
The content of the invention
The present invention provides a kind of USB low-speed devices data transfer control method and controller, with solve in the prior art by USB LS equipment wastes substantial amounts of set caused by USB LS control is completed together with the control of full speed and high speed The problem of counting resource.
The present invention provides a kind of USB low-speed devices data transfer control method, including:When transmitting beginning, detection USB is low The D+ signal wires and D- signal wires of fast equipment, if D+ signal wires and D- signal wires are in idle condition, draw high D+ signals Line;After host computer side drags down D+ signal wires, reset state is directly entered, and draw high D+ signal wires;Reset and complete in host computer side Afterwards, control data transmission channel EP and carry out data transmission with host computer side, after the end of transmission, by D+ signal wires and D- signal wires It is disposed as idle condition.
Preferably, control EP is specifically included:Step 1, judge whether EP is ready to receive token packet, if the judgment is Yes, Step 2 is then performed, if the judgment is No, then EP idle condition is set to;Step 2, EP First Input First Output FIFO is updated The data of middle storage, receive token packet, and enter row decoding parsing to token packet;Step 3, judge whether token packet carries data Bag, if the judgment is Yes, performs step 4, otherwise performs step 5;Step 4, token packet is handled, correct response is returned, and will EP is set to idle condition;Step 5, token packet is handled, if token packet is IN business transmission tokens, EP is set to send State;If token packet, which is OUT transaction, transmits token, EP is set to reception state.
Preferably, when EP is transmission state, carry out data transmission specifically including with host computer side:Judge whether EP is ready to Packet is sent, if the judgment is Yes, then OUT token packets are received, and sends packet, data outage is sent to master while producing Pusher side, otherwise, terminates to send, and notify host computer side.
Preferably, when EP is reception state, carry out data transmission specifically including with host computer side:It is reception state in EP When, judge whether EP gets out received data packet, if the judgment is Yes, then receive IN token packets, and packet is sent, produce simultaneously Hair tonic send data outage to host computer side, otherwise, terminates to receive, and notify host computer side.
Preferably, the above method also includes:It is pre-configured with the big of EP number and each EP First Input First Output It is small;Mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption;Stop the scheduled time in data transfer Afterwards, produce pause to interrupt, notify physical layer to enter park mode into park mode, and by halt signal, called out detecting Wake up after signal or reset signal, exit park mode, and notify physical layer to exit park mode.
Present invention also offers a kind of controller, the data transfer for controlling USB low-speed devices, including:Detection module, For when transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices being detected, if D+ signal wires and D- signal wires are equal In idle condition, then D+ signal wires are drawn high;Reseting module, it is multiple for after host computer side drags down D+ signal wires, being directly entered Position state, and draw high D+ signal wires;Transport module, after the completion of being resetted in host computer side, control data transmission channel EP and with Host computer side carries out data transmission, after the end of transmission, and D+ signal wires and D- signal wires are disposed as into idle condition.
Preferably, transport module is specifically included:First judging submodule, for judging whether EP is ready to receive token Bag, if the judgment is Yes, then calls renewal submodule, if the judgment is No, then EP is set into idle condition;Update submodule The data stored in block, the First Input First Output FIFO for updating EP;Receiving submodule, for receiving token packet;At first Submodule is managed, for entering row decoding parsing to token packet;Second judging submodule, for the processing according to the first processing submodule As a result judge whether token packet carries packet, if the judgment is Yes, call second processing submodule, otherwise, call the 3rd Handle submodule;Second processing submodule, for handling token packet, returns to correct response, and EP is set into idle condition; 3rd processing submodule, for handling token packet, if token packet is IN business transmission tokens, EP is set to send shape State;If token packet, which is OUT transaction, transmits token, EP is set to reception state.
Preferably, transport module is specifically included:3rd judging submodule, for when EP is transmission state, judging that EP is It is no to be ready for packet, if the judgment is Yes, then the first sending submodule is called, otherwise, terminate to send, and notify main frame Side;First sending submodule, for receiving OUT token packets, and sends packet, data outage is sent to main frame while producing Side.
Preferably, transport module is specifically included:4th judging submodule, for when EP is reception state, judging that EP is It is no to get out received data packet, if the judgment is Yes, then the second sending submodule is called, otherwise, terminate to receive, and notify main frame Side;Second sending submodule, for receiving IN token packets, and sends packet, data outage is sent to host computer side while producing.
Preferably, controller noted above further comprises:Configuration module, the number for configuring EP, and each EP elder generation Enter the size of first dequeue;Correction module, for the mistake in automatic detection data transmitting procedure, in notifying host computer side and producing It is disconnected;Suspend module, interrupted for after data transfer stops the scheduled time, producing pause, into park mode, and pass through pause Signal notifies physical layer to enter park mode, after wake-up signal or reset signal is detected, exits park mode, and notify thing Reason layer exits park mode.
The present invention has the beneficial effect that:
By remove in controller at full speed and high speed control, solve in the prior art due to USB LS control with The problem of USB LS equipment wastes substantial amounts of design resource caused by being completed at full speed together with the control of high speed, makes original The USB device of compatible USB low speed only supports the peripheral functionality of USB low speed, and the area of controller reduces 50%, and according to USB's The detection of passage is shaken hands during protocol requirement correctly realizes the interface communication transmission between physical layer and transmitted.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention, And can be practiced according to the content of specification, and in order to allow above and other objects of the present invention, feature and advantage can Become apparent, below especially exemplified by the embodiment of the present invention.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit is common for this area Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings:
Fig. 1 is the module diagram of USB LS in the prior art;
Fig. 2 is the flow chart of the USB low-speed device data transfer control methods of the embodiment of the present invention;
Fig. 3 is a kind of connection for using for reference scheme when the USB2.0 LS peripheral hardware verification environments of the embodiment of the present invention are built Schematic diagram;
Fig. 4 is the flow chart of the EP0 of embodiment of the present invention control major state transfer;
Fig. 5 be the embodiment of the present invention EP0 be IDLE patterns when control flow chart;
Fig. 6 be the embodiment of the present invention EP0 enter sending mode after control flow chart;
Fig. 7 be the embodiment of the present invention EP0 enter reception pattern after control flow chart;
The waveform diagram that Fig. 8 resets when being the initialization of the embodiment of the present invention;
Fig. 9 is the waveform diagram when EP0 of the embodiment of the present invention is controlled IN controlling transmissions;
Waveform diagram when Figure 10 is the EP4 progress OUT transmission of the embodiment of the present invention;
Figure 11 is the structural representation of the controller of the embodiment of the present invention.
Embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in accompanying drawing Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here Limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure Complete conveys to those skilled in the art.
In order to solve in the prior art because USB LS control causes with completing at full speed and together with the control of high speed USB LS equipment waste it is substantial amounts of design resource the problem of, the invention provides a kind of USB low-speed devices data transfer Control method and controller, in embodiments of the present invention, structure and principle based on USB2.0 are changed on the original basis Enter, the USB2.0 devices of former compatibility USB low speed is only supported the device functions of USB low speed so that USB2.0 devices originally The device of USB low speed can be only completed(Peripheral hardware)Function so that area reduces 50%, and correct according to USB protocol requirement The detection for realizing passage in the transmission of the interface communication between physical layer and transmission is shaken hands.Below in conjunction with accompanying drawing and embodiment, The present invention will be described in further detail.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, Do not limit the present invention.
Embodiment of the method
Embodiments in accordance with the present invention are there is provided a kind of USB low-speed devices data transfer control method, and Fig. 2 is the present invention The flow chart of the USB low-speed device data transfer control methods of embodiment, as shown in Fig. 2 USB according to embodiments of the present invention is low Fast device data transfer control method includes following processing:
Step 201, when transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices are detected, if D+ signal wires Idle condition is in D- signal wires, then draws high D+ signal wires;
Step 202, after host computer side drags down D+ signal wires, reset state is directly entered, and draw high D+ signal wires;
Step 203, after the completion of host computer side reset, control data transmission channel EP simultaneously carries out data transmission with host computer side, After the end of transmission, D+ signal wires and D- signal wires are disposed as idle condition.
In step 203, control EP is specifically included:
Step 1, judge whether EP is ready to receive token packet, if the judgment is Yes, then perform step 2, if it is determined that It is no, then EP is set to idle condition;
Step 2, the data stored in the First Input First Output FIFO for updating EP, receive token packet, and token packet is carried out Decoding parsing;
Step 3, judge whether token packet carries packet, if the judgment is Yes, perform step 4, otherwise perform step 5;
Step 4, token packet is handled, correct response is returned to, and EP is set to idle condition;
Step 5, token packet is handled, if token packet is IN business transmission tokens, EP is set to transmission state;If Token packet is that OUT transaction transmits token, then EP is set into reception state.
When EP is transmission state, carry out data transmission specifically including with host computer side:Judge whether EP is ready for number According to bag, if the judgment is Yes, then OUT token packets are received, and send packet, data outage is sent to host computer side while producing, Otherwise, terminate to send, and notify host computer side.
When EP is reception state, carry out data transmission specifically including with host computer side:When EP is reception state, EP is judged Received data packet whether is got out, if the judgment is Yes, then IN token packets are received, and sends packet, number is sent while producing According to interrupting to host computer side, otherwise, terminate to receive, and notify host computer side.
Preferably, in embodiments of the present invention, EP number and each EP First Input First Output can be pre-configured with Size;Mistake in acceptable automatic detection data transmitting procedure, notifies host computer side simultaneously to produce interruption;Stop in data transfer After the scheduled time, produce pause and interrupt, notify physical layer to enter park mode into park mode, and by halt signal, Detect after wake-up signal or reset signal, exit park mode, and notify physical layer to exit park mode.
It can be seen that in embodiments of the present invention from above-mentioned processing, controller enters line number by utmi interface and physical layer According to exchange, the PHY of isochronous controller clock zone, such controller inside can be just operated under bus clock, without It is consistent with PHY;Fig. 3 is that a kind of when the USB2.0LS peripheral hardware verification environments of the embodiment of the present invention are built uses for reference scheme Connection diagram, as shown in figure 3, when controller is connected with PHY, it is only necessary to which the MiniAB interfaces in Fig. 3 are changed into HOST's Vip interface, EBI is passed through in controller end(AHB interface)It is connected with CPU.
The control device of the embodiment of the present invention can be encoded, decoded, error correction and control all USB sent and received Packet, the control data stream of IN transmission is carried out by the transmission FIFO of peripheral hardware, and the control data stream of OUT transmission passes through peripheral hardware FIFO is received to carry out;The controller of the embodiment of the present invention supports dynamic FIFO.
In addition, the embodiment of the present invention supports configurable EP numbers, EP numbers are 0 ~ 4, can be configured according to transmission requirement, For example:RX endpoint are may be configured as BULK OUT operations EP, TX is may be configured as BULKIN operations EP endpoint;In addition, EP FIFO is configurable to different sizes, the requirement of different transmission is met, is that transmittability is various Change;Main frame can be received(HOST)The SOF bags that side is sent, and produce SOF interruptions;And corresponding control is produced in the data transmission Interrupt.
The controller of the embodiment of the present invention also supports the pause of DEVICE patterns(SUSPEND)Operation, for example, when on USB When not having data transfer 3ms, controller can produce SUSPEND interruptions, into SUSPEND patterns, in this mode, controller By SUSPEND signals notify PHY enter SUSPEND patterns, now PHY clocks turn off, until monitored in bus wake up or Person's reset signal, controller exits SUSPEND and notifies PHY, PHY to exit SUSPEND states by SUSPEND signals.
The controller of the embodiment of the present invention also supports the CRC of data(Cyclic RedundancyCheck, Referred to as CRC), with error correction capability, the protocol error during USB transmission can be detected automatically, and return to STALL Bag, and interruption is produced, when CPU receives the interruption, current transmission can be terminated, STALL interrupt bit is removed, controller is certainly It is dynamic to return to IDLE state.
Below in conjunction with accompanying drawing, by taking USB2.0 versions as an example, the above-mentioned technical proposal to the embodiment of the present invention is carried out in detail Explanation.
In the prior art, for low speed device, many functions in USB controller are unwanted, for example, HOST Function, highspeed portion and OTG functions etc.;The embodiment of the present invention is in order to realize to the transmission control based on USB2.0 low speed devices System, remains low speed sections DEVICE control section, and the part that CRC check and agreement judge, eliminates HOST functions, The partial function of highspeed portion and OTG;The basic state of a control machine step of the embodiment of the present invention is as follows(It is abnormal unlisted):
When step 1, transmission start, D+/D- signal wires are detected, if the two is in idle condition, SRP operations are initiated, i.e., Draw high D+ lines;Wait the response of HOST sides;
Step 2, HOST sides drag down D+ lines, represent to be waken up, and DEVICE jumps out SRP states and is directly entered reset state, Draw high D+ lines;Into step 3;
Step 3, in this state, FS is consistent with LS reset, is all to draw high D+ lines, HOST receives reset signal Afterwards, start to reset operation, after the completion of reset, HOST proceeds by the transmission of packet and command information;Into step 4;
Step 4, in data transmission procedure, low-speed device for D+/D- lines condition adjudgement with full speed and high speed on the contrary, Traditional controller is by judging that UTMI signal linstate state distinguishes full speed and low speed, and the embodiment of the present invention need not Carry out velocity estimated;
Step 5, the end of transmission, return to IDLE state, and wait is transmitted next time.
Pass through the explanation of the host state machine of controller noted above, it can be seen that the embodiment of the present invention eliminates most control State and judgment part, have reached the purpose of reduction circuit resource.
Basic USB2.0 controllers are also needed to complete the control to EP, according to USB2.0 agreements, and connection is set up between EP, Form the pipeline of data transfer;The embodiment of the present invention extracts USB low-speed peripheral on the basis of USB2.0, and to internal state Machine is controlled:Including host state machine, to control the overall work of USB device, the control to USB device inside EP is completed.This Inventive embodiments use single state of a control machine for EP control, control single EP data channel, and EP0 is compared in EP Special one, for completing the operation of the initialization such as LINK UP, illustrates the present apparatus to EP's by taking EP0 controlling transmission as an example Control process;
Fig. 4 is the flow chart of the EP0 of embodiment of the present invention control major state transfer, and traditional USB controller is software By reading EP0 status registers, judge that EP0, whether in the free time, if it does, can hang up, or sends SETUP tokens Bag;Subsequently into IDLE state;The embodiment of the present invention can also read EP0 state by software, but not initiate SETUP orders Board, because command token can only be sent by HOST;The EP0 of the embodiment of the present invention is directly in IDLE state;Afterwards, it is traditional USB controller can be by software merit rating, enters EP0 and sends or reception pattern;The embodiment of the present invention can wait to be received The token packet of HOST sides, if IN is operated, then EP enters transmission state, if OUT is operated, then EP enters reception state.
Fig. 5 be the embodiment of the present invention EP0 be IDLE patterns when control flow chart, as shown in figure 5, the present invention implementation In example, when upper electricity and reset, EP enters IDLE patterns;In host state machine, enumerated when carrying out SETUP transmission, i.e. USB During state, into IDLE patterns;Into after IDLE patterns, follow the steps below:
Step 1, prepare received data packet or token packet, if be not ready for, return to IDLE state, turn after getting ready, Into step 2;
Step 2, the data stored in FIFO are updated, order is received;
Step 3, receive after order, enter row decoding, order is parsed, command commands are judged according to USB2.0 agreement Whether board carries packet, if entering step 4 without packet, otherwise into step 5;
Step 4, token packet is handled, data are set, and returns to correct response, IDLE state is returned to;
Step 5, token packet is handled, data are set;Judge whether it is IN business transmission tokens, sending mode is entered if being (Fig. 6), it is not then to enter step 6;
Step 6, transmitted into OUT transaction, into reception pattern(Fig. 7).
Fig. 6 be the embodiment of the present invention EP0 enter sending mode after control flow chart, if as shown in fig. 6, EP0 is TX patterns, traditional USB controller can send and receive OUT token packets, and the embodiment of the present invention is merely able to receive OUT token packets; All IN token packets received can all be taken as data processing, if now receiving SETUP orders or OUT token packets, SETUPEND condition can be produced, EP0 exits TX patterns, be configured most in addition, if the length of the packet of transmission is less than EP0 Big packet length, or empty bag is received, USB exits the state;Other EP TX patterns are similar, and process step is as follows:
Step 1, it is ready for sending bag to judge, if not turning to get ready, directly terminates to send, return to STALL responses, represent number According to being not ready for, otherwise into step 2;
Step 2, OUT token packets are received, DATA0 packets are sent, data outage is sent to CPU while producing;
Step 3, OUT transaction terminates.
Fig. 7 be the embodiment of the present invention EP0 enter reception pattern after control flow chart, as shown in fig. 7, EP0 is in RX moulds Formula is that traditional USB controller can send and receive IN token packets, and the embodiment of the present invention is merely able to receive IN token packets;It is all The OUT token packets received can all be taken as data processing, if receiving SETUP or OUT token packets, can produce SETUPEND conditions, RX mode ends;If other host side sends invalid token packet or empty bag, or the bag sent Length is less than maximum packet length, can also produce SETUPEND conditions;Its EP TX patterns are similar, and process step is as follows:
Step 1, prepare to receive bag judgement, if not turning to get ready, directly terminate to send, return to STALL responses, represent number According to being not ready for, otherwise into step 2;
Step 2, receive after IN token packets, send packet, data outage is sent to CPU while producing;
Step 3, IN affairs terminate.
In embodiments of the present invention, the state of the controller is mainly DP/DM signals by physical layer interface signal and controlled, It is expressed as two states, K state and J states;The state is represented by the linestate of UTMI signaling interfaces, specific as follows: Assign j=linestate [1] & ~ linestate [0];Assign k=~ linestate [1] &linestate [0].Fig. 8 The waveform diagram resetted during the initialization for being the embodiment of the present invention, as shown in figure 8, dm signals are drawn high, dp is constant, by SE0 Dm signals are drawn high after state;Fig. 9 is the waveform diagram when EP0 of the embodiment of the present invention is controlled IN controlling transmissions, such as Fig. 9 Shown, one of SETADDR packet is as follows:HOST ends set address to be 5b, and it is d2, CLK that controller, which responds token packet, For 1.5Mbps;Waveform diagram when Figure 10 is the EP4 progress OUT transmission of the embodiment of the present invention, as shown in Figure 10, data are long Spend for 64.
In summary, by means of the technical scheme of the embodiment of the present invention, by removing in controller at full speed and high speed Control, solves USB caused by being completed in the prior art due to USB LS control together with the control of full speed and high speed The problem of LS equipment wastes substantial amounts of design resource, makes the USB device of former compatibility USB low speed only support the outer of USB low speed If function, the area of controller reduces 50%, and correctly realizes the interface between physical layer according to USB protocol requirement and lead to The detection of passage is shaken hands in letter transmission and transmission.
Device embodiment
Embodiments in accordance with the present invention are there is provided a kind of controller, the data transfer for controlling USB low-speed devices, figure 11 be the structural representation of the controller of the embodiment of the present invention, and as shown in figure 11, controller according to embodiments of the present invention includes: The modules of the embodiment of the present invention are carried out in detail by detection module 110, reseting module 112 and transport module 114 below Explanation.
Detection module 110, for when transmitting beginning, detecting the D+ signal wires and D- signal wires of USB low-speed devices, if D+ signal wires and D- signal wires are in idle condition, then draw high D+ signal wires;
Reseting module 112, for after host computer side drags down D+ signal wires, being directly entered reset state, and draws high D+ letters Number line;
Transport module 114, after the completion of being resetted in host computer side, control data transmission channel EP simultaneously enters line number with host computer side According to transmission, after the end of transmission, D+ signal wires and D- signal wires are disposed as idle condition.
Transport module 114 is specifically included:
First judging submodule, for judging whether EP is ready to receive token packet, if the judgment is Yes, then calls renewal Submodule, if the judgment is No, is then set to idle condition by EP;
Update the data stored in submodule, the First Input First Output FIFO for updating EP;
Receiving submodule, for receiving token packet;
First processing submodule, for entering row decoding parsing to token packet;
Second judging submodule, for judging whether token packet carries number according to the result of the first processing submodule According to bag, if the judgment is Yes, second processing submodule is called, otherwise, call the 3rd processing submodule;
Second processing submodule, for handling token packet, returns to correct response, and EP is set into idle condition;
3rd processing submodule, for handling token packet, if token packet is IN business transmission tokens, EP is set to Transmission state;If token packet, which is OUT transaction, transmits token, EP is set to reception state.
3rd judging submodule, for when EP is transmission state, judging whether EP is ready for packet, if sentenced It is yes to break, then calls the first sending submodule, otherwise, terminates to send, and notify host computer side;
First sending submodule, for receiving OUT token packets, and sends packet, at the same produce send data outage to Host computer side.
4th judging submodule, for when EP is reception state, judging whether EP gets out received data packet, if sentenced It is yes to break, then calls the second sending submodule, otherwise, terminates to receive, and notify host computer side;
Second sending submodule, for receiving IN token packets, and sends packet, data outage is sent to master while producing Pusher side.
Preferably, in embodiments of the present invention, controller further comprises:
The size of configuration module, the number for configuring EP, and each EP First Input First Output;
Correction module, for the mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption;
Suspend module, interrupt, into park mode, and lead to for after data transfer stops the scheduled time, producing pause Crossing halt signal notifies physical layer to enter park mode, after wake-up signal or reset signal is detected, exits park mode, and Physical layer is notified to exit park mode.
It can be seen that in embodiments of the present invention from above-mentioned processing, controller enters line number by utmi interface and physical layer According to exchange, the PHY of isochronous controller clock zone, such controller inside can be just operated under bus clock, without It is consistent with PHY;Fig. 3 is that one kind when the USB2.0 LS peripheral hardware verification environments of the embodiment of the present invention are built can use for reference scheme Connection diagram, as shown in figure 3, when controller is connected with PHY, it is only necessary to which the MiniAB interfaces in Fig. 3 are changed into HOST Vip interface, pass through EBI in controller end(AHB interface)It is connected with CPU.
The control device of the embodiment of the present invention can be encoded, decoded, error correction and control all USB sent and received Packet, the control data stream of IN transmission is carried out by the transmission FIFO of peripheral hardware, and the control data stream of OUT transmission passes through peripheral hardware FIFO is received to carry out;The controller of the embodiment of the present invention supports dynamic FIFO.
In addition, the embodiment of the present invention supports configurable EP numbers, EP numbers are 0 ~ 4, can be configured according to transmission requirement, For example:RX endpoint are may be configured as BULK OUT operations EP, TX is may be configured as BULKIN operations EP endpoint;In addition, EP FIFO is configurable to different sizes, the requirement of different transmission is met, is that transmittability is various Change;Main frame can be received(HOST)The SOF bags that side is sent, and produce SOF interruptions;And corresponding control is produced in the data transmission Interrupt.
The controller of the embodiment of the present invention also supports the pause of DEVICE patterns(SUSPEND)Operation, for example, when on USB When not having data transfer 3ms, controller can produce SUSPEND interruptions, into SUSPEND patterns, in this mode, controller By SUSPEND signals notify PHY enter SUSPEND patterns, now PHY clocks turn off, until monitored in bus wake up or Person's reset signal, controller exits SUSPEND and notifies PHY, PHY to exit SUSPEND states by SUSPEND signals.
The controller of the embodiment of the present invention also supports the CRC of data(Cyclic RedundancyCheck, Referred to as CRC), with error correction capability, the protocol error during USB transmission can be detected automatically, and return to STALL Bag, and interruption is produced, when CPU receives the interruption, current transmission can be terminated, STALL interrupt bit is removed, controller is certainly It is dynamic to return to IDLE state.
Below in conjunction with accompanying drawing, by taking USB2.0 versions as an example, the above-mentioned technical proposal to the embodiment of the present invention is carried out in detail Explanation.
In the prior art, for low speed device, many functions in USB controller are unwanted, for example, HOST Function, highspeed portion and OTG functions etc.;The embodiment of the present invention is in order to realize to the transmission control based on USB2.0 low speed devices System, remains low speed sections DEVICE control section, and the part that CRC check and agreement judge, eliminates HOST functions, The partial function of highspeed portion and OTG;The basic state of a control machine step of the embodiment of the present invention is as follows(It is abnormal unlisted):
When step 1, transmission start, D+/D- signal wires are detected, if the two is in idle condition, SRP operations are initiated, i.e., Draw high D+ lines;Wait the response of HOST sides;
Step 2, HOST sides drag down D+ lines, represent to be waken up, and DEVICE jumps out SRP states and is directly entered reset state, Draw high D+ lines;Into step 3;
Step 3, in this state, FS is consistent with LS reset, is all to draw high D+ lines, HOST receives reset signal Afterwards, start to reset operation, after the completion of reset, HOST proceeds by the transmission of packet and command information;Into step 4;
Step 4, in data transmission procedure, low-speed device for D+/D- lines condition adjudgement with full speed and high speed on the contrary, Traditional controller is by judging that UTMI signal linstate state distinguishes full speed and low speed, and the embodiment of the present invention need not Carry out velocity estimated;
Step 5, the end of transmission, return to IDLE state, and wait is transmitted next time.
Pass through the explanation of the host state machine of controller noted above, it can be seen that the embodiment of the present invention eliminates most control State and judgment part, have reached the purpose of reduction circuit resource.
Basic USB2.0 controllers are also needed to complete the control to EP, according to USB2.0 agreements, and connection is set up between EP, Form the pipeline of data transfer;The embodiment of the present invention extracts USB low-speed peripheral on the basis of USB2.0, and to internal state Machine is controlled:Including host state machine, to control the overall work of USB device, the control to USB device inside EP is completed.This Inventive embodiments use single state of a control machine for EP control, control single EP data channel, and EP0 is compared in EP Special one, for completing the operation of the initialization such as LINK UP, illustrates the present apparatus to EP's by taking EP0 controlling transmission as an example Control process;
Fig. 4 is the flow chart of the EP0 of embodiment of the present invention control major state transfer, and traditional USB controller is software By reading EP0 status registers, judge that EP0, whether in the free time, if it does, can hang up, or sends SETUP tokens Bag;Subsequently into IDLE state;The embodiment of the present invention can also read EP0 state by software, but not initiate SETUP orders Board, because command token can only be sent by HOST;The EP0 of the embodiment of the present invention is directly in IDLE state;Afterwards, it is traditional USB controller can be by software merit rating, enters EP0 and sends or reception pattern;The embodiment of the present invention can wait to be received The token packet of HOST sides, if IN is operated, then EP enters transmission state, if OUT is operated, then EP enters reception state.
Fig. 5 be the embodiment of the present invention EP0 be IDLE patterns when control flow chart, as shown in figure 5, the present invention implementation In example, when upper electricity and reset, EP enters IDLE patterns;In host state machine, enumerated when carrying out SETUP transmission, i.e. USB During state, into IDLE patterns;Into after IDLE patterns, follow the steps below:
Step 1, prepare received data packet or token packet, if be not ready for, return to IDLE state, turn after getting ready, Into step 2;
Step 2, the data stored in FIFO are updated, order is received;
Step 3, receive after order, enter row decoding, order is parsed, command commands are judged according to USB2.0 agreement Whether board carries packet, if entering step 4 without packet, otherwise into step 5;
Step 4, token packet is handled, data are set, and returns to correct response, IDLE state is returned to;
Step 5, token packet is handled, data are set;Judge whether it is IN business transmission tokens, sending mode is entered if being (Fig. 6), it is not then to enter step 6;
Step 6, transmitted into OUT transaction, into reception pattern(Fig. 7).
Fig. 6 be the embodiment of the present invention EP0 enter sending mode after control flow chart, if as shown in fig. 6, EP0 is TX patterns, traditional USB controller can send and receive OUT token packets, and the embodiment of the present invention is merely able to receive OUT token packets; All IN token packets received can all be taken as data processing, if now receiving SETUP orders or OUT token packets, SETUPEND condition can be produced, EP0 exits TX patterns, be configured most in addition, if the length of the packet of transmission is less than EP0 Big packet length, or empty bag is received, USB exits the state;Other EP TX patterns are similar, and process step is as follows:
Step 1, it is ready for sending bag to judge, if not turning to get ready, directly terminates to send, return to STALL responses, represent number According to being not ready for, otherwise into step 2;
Step 2, OUT token packets are received, DATA0 packets are sent, data outage is sent to CPU while producing;
Step 3, OUT transaction terminates.
Fig. 7 be the embodiment of the present invention EP0 enter reception pattern after control flow chart, as shown in fig. 7, EP0 is in RX moulds Formula is that traditional USB controller can send and receive IN token packets, and the embodiment of the present invention is merely able to receive IN token packets;It is all The OUT token packets received can all be taken as data processing, if receiving SETUP or OUT token packets, can produce SETUPEND conditions, RX mode ends;If other host side sends invalid token packet or empty bag, or the bag sent Length is less than maximum packet length, can also produce SETUPEND conditions;Its EP TX patterns are similar, and process step is as follows:
Step 1, prepare to receive bag judgement, if not turning to get ready, directly terminate to send, return to STALL responses, represent number According to being not ready for, otherwise into step 2;
Step 2, receive after IN token packets, send packet, data outage is sent to CPU while producing;
Step 3, IN affairs terminate.
In embodiments of the present invention, the state of the controller is mainly DP/DM signals by physical layer interface signal and controlled, It is expressed as two states, K state and J states;The state is represented by the linestate of UTMI signaling interfaces, specific as follows: assign j=linestate[1] &~linestate[0];assign k=~linestate[1]&linestate[0].Fig. 8 The waveform diagram resetted during the initialization for being the embodiment of the present invention, as shown in figure 8, dm signals are drawn high, dp is constant, by SE0 Dm signals are drawn high after state;Fig. 9 is the waveform diagram when EP0 of the embodiment of the present invention is controlled IN controlling transmissions, such as Fig. 9 Shown, one of SETADDR packet is as follows:HOST ends set address to be 5b, and it is d2, CLK that controller, which responds token packet, For 1.5Mbps;Waveform diagram when Figure 10 is the EP4 progress OUT transmission of the embodiment of the present invention, as shown in Figure 10, data are long Spend for 64.
In summary, by means of the technical scheme of the embodiment of the present invention, by removing in controller at full speed and high speed Control, solves USB caused by being completed in the prior art due to USB LS control together with the control of full speed and high speed The problem of LS equipment wastes substantial amounts of design resource, makes the USB device of former compatibility USB low speed only support the outer of USB low speed If function, the area of controller reduces 50%, and correctly realizes the interface between physical layer according to USB protocol requirement and lead to The detection of passage is shaken hands in letter transmission and transmission.
Algorithm and display be not inherently related to any certain computer, virtual system or miscellaneous equipment provided herein. Various general-purpose systems can also be used together with based on teaching in this.As described above, construct required by this kind of system Structure be obvious.In addition, the present invention is not also directed to any certain programmed language.It is understood that, it is possible to use it is various Programming language realizes the content of invention described herein, and the description done above to language-specific is to disclose this hair Bright preferred forms.
In the specification that this place is provided, numerous specific details are set forth.It is to be appreciated, however, that the implementation of the present invention Example can be put into practice in the case of these no details.In some instances, known method, structure is not been shown in detail And technology, so as not to obscure the understanding of this description.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each inventive aspect, exist Above in the description of the exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention:It is i.e. required to protect The application claims of shield features more more than the feature being expressly recited in each claim.More precisely, such as following Claims reflect as, inventive aspect is all features less than single embodiment disclosed above.Therefore, Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself All as the separate embodiments of the present invention.
Those skilled in the art, which are appreciated that, to be carried out adaptively to the module in the equipment in embodiment Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use any Combination is to this specification(Including adjoint claim, summary and accompanying drawing)Disclosed in all features and so disclosed appoint Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification(Including adjoint power Profit requires, made a summary and accompanying drawing)Disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation Replace.
Although in addition, it will be appreciated by those of skill in the art that some embodiments described herein include other embodiments In included some features rather than further feature, but the combination of the feature of be the same as Example does not mean in of the invention Within the scope of and form different embodiments.For example, in the following claims, times of embodiment claimed One of meaning mode can be used in any combination.
The present invention all parts embodiment can be realized with hardware, or with one or more processor run Software module realize, or realized with combinations thereof.It will be understood by those of skill in the art that can use in practice Microprocessor or digital signal processor(DSP)It is according to embodiments of the present invention to realizeControllerIn it is some or all The some or all functions of part.The present invention be also implemented as a part for performing method as described herein or Whole equipment or program of device(For example, computer program and computer program product).Such journey for realizing the present invention Sequence can be stored on a computer-readable medium, or can have the form of one or more signal.Such signal can Obtained with being downloaded from internet website, either provide or provided in any other form on carrier signal.
It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims, Any reference symbol between bracket should not be configured to limitations on claims.Word "comprising" is not excluded the presence of not Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such Element.The present invention can be by means of including the hardware of some different elements and coming real by means of properly programmed computer It is existing.In if the unit claim of equipment for drying is listed, several in these devices can be by same hardware branch To embody.The use of word first, second, and third does not indicate that any order.These words can be explained and run after fame Claim.

Claims (10)

1. a kind of USB low-speed devices data transfer control method, it is characterised in that including:
When transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices are detected, if the D+ signal wires and the D- Signal wire is in idle condition, then draws high D+ signal wires;
After host computer side drags down the D+ signal wires, reset state is directly entered, and draw high D+ signal wires;
After the completion of host computer side reset, control data transmission channel EP simultaneously carries out data transmission with the host computer side, is passing After defeated end, the D+ signal wires and the D- signal wires are disposed as idle condition;
Methods described, in addition to:Pre-set EP First Input First Output FIFO size;
After data transfer stops the scheduled time, produce pause and interrupt, physics is notified into park mode, and by halt signal Layer enters park mode, after wake-up signal or reset signal is detected, exits the park mode, and notify the physical layer Exit the park mode.
2. the method as described in claim 1, it is characterised in that the control EP is specifically included:
Step 1, judge whether EP is ready to receive token packet, if the judgment is Yes, then perform step 2, if the judgment is No, then The EP is set to idle condition;
Step 2, the data stored in the First Input First Output FIFO for updating the EP, receive the token packet, and to the order Board bag enters row decoding parsing;
Step 3, judge whether the token packet carries packet, if the judgment is Yes, perform step 4, otherwise perform step 5;
Step 4, the token packet is handled, correct response is returned to, and the EP is set to idle condition;
Step 5, the token packet is handled, if the token packet is IN business transmission tokens, the EP is set to send State;If the token packet, which is OUT transaction, transmits token, the EP is set to reception state.
3. method as claimed in claim 2, it is characterised in that when the EP is transmission state, carried out with the host computer side Data transfer is specifically included:
Judge whether the EP is ready for packet, if the judgment is Yes, then receive OUT token packets, and send packet, Produce simultaneously and send data outage to the host computer side, otherwise, terminate to send, and notify the host computer side.
4. method as claimed in claim 2, it is characterised in that when the EP is reception state, carried out with the host computer side Data transfer is specifically included:
When the EP is reception state, judges whether the EP gets out received data packet, if the judgment is Yes, then receive IN Token packet, and packet is sent, data outage is sent to the host computer side while producing, and otherwise, terminates to receive, and notify described Host computer side.
5. the method as described in claim 1, it is characterised in that methods described also includes:
It is pre-configured with EP number;
Mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption.
6. a kind of controller, it is characterised in that the data transfer for controlling USB low-speed devices, the controller is specifically included:
Detection module, for when transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices being detected, if the D+ Signal wire and the D- signal wires are in idle condition, then draw high D+ signal wires;
Reseting module, for after host computer side drags down the D+ signal wires, being directly entered reset state, and draw high D+ signals Line;
Transport module, for after the completion of host computer side reset, control data transmission channel EP simultaneously to be carried out with the host computer side Data transfer, after the end of transmission, idle condition is disposed as by the D+ signal wires and the D- signal wires;
Configuration module, the size of the First Input First Output for pre-setting EP;
Suspend module, interrupted for after data transfer stops the scheduled time, producing pause, into park mode, and by temporary Stopping signal notifies physical layer to enter park mode, after wake-up signal or reset signal is detected, exits the park mode, and The physical layer is notified to exit the park mode.
7. controller as claimed in claim 6, it is characterised in that the transport module is specifically included:
First judging submodule, for judging whether EP is ready to receive token packet, if the judgment is Yes, then calls renewal submodule Block, if the judgment is No, is then set to idle condition by the EP;
Update the data stored in submodule, the First Input First Output FIFO for updating the EP;
Receiving submodule, for receiving the token packet;
First processing submodule, for entering row decoding parsing to the token packet;
Second judging submodule, for judging whether the token packet carries according to the result of the described first processing submodule There is packet, if the judgment is Yes, call second processing submodule, otherwise, call the 3rd processing submodule;
Second processing submodule, for handling the token packet, returns to correct response, and the EP is set into idle shape State;
3rd processing submodule,, will be described if the token packet is IN business transmission tokens for handling the token packet EP is set to transmission state;If the token packet, which is OUT transaction, transmits token, the EP is set to reception state.
8. controller as claimed in claim 7, it is characterised in that the transport module is specifically included:
3rd judging submodule, for when the EP is transmission state, judging whether the EP is ready for packet, such as Fruit is judged as YES, then calls the first sending submodule, otherwise, terminates to send, and notify the host computer side;
First sending submodule, for receiving OUT token packets, and sends packet, data outage is sent to described while producing Host computer side.
9. controller as claimed in claim 7, it is characterised in that the transport module is specifically included:
4th judging submodule, for when the EP is reception state, judging whether the EP gets out received data packet, such as Fruit is judged as YES, then calls the second sending submodule, otherwise, terminates to receive, and notify the host computer side;
Second sending submodule, for receiving IN token packets, and sends packet, data outage is sent to the master while producing Pusher side.
10. controller as claimed in claim 6, it is characterised in that the controller further comprises:
Configuration module, the number for configuring EP;
Correction module, for the mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption.
CN201210453547.8A 2012-11-13 2012-11-13 USB low-speed devices data transfer control method and controller Expired - Fee Related CN103810127B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201210453547.8A CN103810127B (en) 2012-11-13 2012-11-13 USB low-speed devices data transfer control method and controller
PCT/CN2013/085995 WO2014075545A1 (en) 2012-11-13 2013-10-25 Data transmission control method of low-speed usb device and controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210453547.8A CN103810127B (en) 2012-11-13 2012-11-13 USB low-speed devices data transfer control method and controller

Publications (2)

Publication Number Publication Date
CN103810127A CN103810127A (en) 2014-05-21
CN103810127B true CN103810127B (en) 2017-09-08

Family

ID=50706919

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210453547.8A Expired - Fee Related CN103810127B (en) 2012-11-13 2012-11-13 USB low-speed devices data transfer control method and controller

Country Status (2)

Country Link
CN (1) CN103810127B (en)
WO (1) WO2014075545A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106294265A (en) * 2015-05-19 2017-01-04 深圳市超越自然多媒体有限公司 A kind of audio data transmission method between USB sound card and smart machine
CN106293594A (en) * 2015-05-19 2017-01-04 深圳市超越自然多媒体有限公司 A kind of audio data transmission method for USB sound card
CN106294248A (en) * 2015-05-19 2017-01-04 深圳市超越自然多媒体有限公司 A kind of for the control method between smart machine and USB sound card
CN105701049B (en) * 2016-03-23 2019-03-01 Oppo广东移动通信有限公司 System, method, apparatus and the mobile terminal of charge flag position is written
CN114244485B (en) * 2021-12-03 2023-06-09 威创集团股份有限公司 Data management method for USB signal long-distance transmission
CN114356815A (en) * 2021-12-09 2022-04-15 青岛信芯微电子科技股份有限公司 USB controller, chip, display device and control method
CN114564099B (en) * 2022-01-20 2024-06-04 珠海亿智电子科技有限公司 Method for reducing USB transmission power consumption and electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1650249A (en) * 2002-12-27 2005-08-03 富士通株式会社 USB device and method for controlling USB device
CN101256452A (en) * 2007-03-01 2008-09-03 昆盈企业股份有限公司 USB input device and method for expansion of band width

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM240048U (en) * 2002-01-16 2004-08-01 Elan Microelectronics Corp USB interface controller chip
CN1459695A (en) * 2002-05-15 2003-12-03 义隆电子股份有限公司 USB interface controller chip
DE10239814B4 (en) * 2002-08-29 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale Extended test mode support for host controllers
CN100533419C (en) * 2007-03-13 2009-08-26 威盛电子股份有限公司 USB peripheral equipment and mode detecting method thereof
CN101339542B (en) * 2008-06-04 2012-08-29 炬才微电子(深圳)有限公司 Data transmission device, control circuit chip and operation mode control method
CN101520767B (en) * 2009-04-07 2011-02-09 上海炬力集成电路设计有限公司 Data transmission speed self-adapting method and device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1650249A (en) * 2002-12-27 2005-08-03 富士通株式会社 USB device and method for controlling USB device
CN101256452A (en) * 2007-03-01 2008-09-03 昆盈企业股份有限公司 USB input device and method for expansion of band width

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
USB2.0主机控制器内核SIE的设计;张爱丽;《中国优秀硕士学位论文全文数据库》;20071231(第5期);文献14-26、28-31页 *
USB电气特性;陈启美等;《电力自动化设备》;20010930;第21卷(第9期);全文 *

Also Published As

Publication number Publication date
CN103810127A (en) 2014-05-21
WO2014075545A1 (en) 2014-05-22

Similar Documents

Publication Publication Date Title
CN103810127B (en) USB low-speed devices data transfer control method and controller
US7822907B2 (en) Methods and apparatuses for serial bus sideband communications
CN101799795B (en) 1553B bus monitor and bus system with same
CN102347896B (en) Ethernet-based platform for loading FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implementation method thereof
CN103914424B (en) LPC peripheral expansion method based on GPIO interface and device
US20030229749A1 (en) Data transfer control device, electronic equipment, and data transfer control method
CN105573951B (en) A kind of ahb bus interface system for data stream transmitting
CN106462528A (en) Power-saving mode for USB power delivery sourcing device
EP2987087A1 (en) Device, method and system for operation of a low power phy with a pcie protocol stack
CN108255776B (en) I3C master device compatible with APB bus, master-slave system and communication method
WO2015024414A1 (en) Chip and method for debugging mcu by using i2c slave device
CN106933760A (en) A kind of dma controller and data uploading method based on AXI protocol
CN108768981A (en) A kind of IP kernel for realizing the communication of Powerlink industry real-time ethernets
JP2010086524A (en) Bridge device with function to save power
CN108650136A (en) A kind of design method of master/slave station card that realizing the communication of Powerlink industry real-time ethernets
CN109062850B (en) Data sending and receiving method of single chip microcomputer
CN101763324B (en) Method for realizing equipment simulating and device thereof
CN101937413A (en) Communication method of I2C bus
US7469304B2 (en) Data transfer control device, electronic equipment, and method for a data transfer through a bus, the data transfer control device including a register and a packet buffer that are commonly used during a host operation and a peripheral operation
CN105718396B (en) A kind of I of big data master transmissions2C bus units and its means of communication
US20070061491A1 (en) Communication method and apparatus
CN103226535B (en) A kind of microserver and management method thereof
US6874047B1 (en) System and method for implementing an SMBus/I2C interface on a network interface card
CN102081455A (en) Multicomputer switcher and adapter thereof
CN104156336A (en) Control method of USB2.0 interface chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
EE01 Entry into force of recordation of patent licensing contract

Application publication date: 20140521

Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd.

Assignor: SANECHIPS TECHNOLOGY Co.,Ltd.

Contract record no.: 2019440020036

Denomination of invention: Data transmission control method and controller for USB (universal serial bus) low-speed device

Granted publication date: 20170908

License type: Common License

Record date: 20190619

EE01 Entry into force of recordation of patent licensing contract
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170908

Termination date: 20211113

CF01 Termination of patent right due to non-payment of annual fee