CN116068873A - Time-to-digital converter - Google Patents

Abstract

The present invention provides a time-to-digital converter that can achieve high accuracy, high resolution, and high speed without the need for an ASIC and/or analog circuit design. The time-to-digital converter for measuring a time interval T between a first time point T1 and a second time point T2 in an input waveform is provided with: a reference counting unit that counts the main time interval TM as an integer multiple of the period of the input reference clock; a zero number counting unit that counts the zero number time intervals TF as a margin or a shortage of the main time interval TM with respect to the time interval T; and a counting/converting unit that calculates a time interval T based on the main time interval TM and the zero-number time interval TF, converts the time interval T into a digital value, the zero-number counting unit having: n frequency multiplication units that generate m-multiplied signals that become reference clocks, respectively; and a phase shift unit for shifting the respective phases of the signals outputted from the n frequency multiplication units by 360 DEG/n one by one.

Description

Time-to-digital converter

Technical Field

The present invention relates to a time-to-digital converter, and more particularly, to a time-to-digital converter suitable for use in a semiconductor inspection apparatus (semiconductor tester).

Background

Conventionally, a semiconductor inspection apparatus for inspecting an object to be inspected, for example, an IC, LSI, or the like, has been known as an apparatus for measuring a time of a signal (for example, refer to patent document 1).

As a method for measuring time and/or frequency, various methods have been proposed so far, and typical methods include a general-purpose counting method, a time-spread method, a time-voltage conversion method, a time-vernier method, and the like.

For example, in the general counting method, a time measurement is performed by performing a specified time measurement on a built-in reference clock input signal. The time-expansion method is a method of measuring a time converted into a voltage, and is a method of charging and discharging a pulse width of zero-number time by an integrating circuit and expanding the pulse width.

Prior art literature

Patent literature

Patent document 1: japanese patent laid-open publication No. 2003-139817

Disclosure of Invention

Technical problem

However, in the case of performing time measurement as a function of the semiconductor inspection apparatus, there is a limit in the conventional method.

That is, in the semiconductor inspection apparatus, although time measurement can be performed by including a time-to-digital converter, in this case, as a general-purpose technology that does not require ASIC (application specific integrated circuit: application specific integrated circuit) and/or analog circuit design, a time-to-digital converter using an FPGA (field-programmable gate array: field programmable gate array) is generally used. In a typical FPGA, the clock frequency is several hundred MHz, and the minimum amount that can be measured is limited to the nsec order.

On the other hand, in a time-to-digital converter used in a semiconductor inspection apparatus, it is important to measure (measure) the height of the resolution, the extent of the measurement dynamic range, and the high-speed performance of the measurement, and in the present state, for example, measurement at a resolution of about 100ps is desired. In this case, 10GHz is required as a reference clock, and in order to achieve high accuracy, high resolution, and high speed, it is necessary to manufacture an ASIC or design an analog circuit separately, which results in a problem that the cost of the time-to-digital converter increases. This is not limited to the general counting method, and there is a problem that the time-to-digital converter using other methods known in the past is also low.

In addition, although high-accuracy and high-resolution measurement can be performed using an oscilloscope and a PC (personal computer), in this case, there is a limit to high-speed processing.

In view of the above, the present invention provides a time-to-digital converter that can achieve high accuracy, high resolution, and high speed without the need for ASIC and/or analog circuit design.

Technical proposal

The present invention relates to a time-to-digital converter for measuring a time interval between a first time point and a second time point in an input waveform, the time-to-digital converter comprising: a reference counting unit that counts a main time interval with respect to the time interval as an integer multiple of a period of a reference clock; a zero number counting unit that counts a zero number time interval as a margin or a shortage of the master time interval with respect to the time interval; and a count/conversion unit that calculates the time interval based on the main time interval and the zero-number time interval and converts it into a digital value, the zero-number count unit having: a frequency multiplication unit group including n (n is an integer of 2 or more) frequency multiplication units each configured to generate a signal obtained by sampling a signal corresponding to the zero-number time interval by m times (m is an integer of 2 or more) the reference clock; and a phase shift unit that shifts the respective phases of the signals generated by the n frequency multiplication units by 360 °/n one by one.

Technical effects

According to the present invention, there is provided an excellent effect that a high-precision, high-resolution, high-speed time-to-digital converter can be realized without requiring ASIC and/or analog circuit design.

Drawings

Fig. 1 is a diagram illustrating a time-to-digital converter according to the present embodiment, fig. 1 (a) is a schematic block diagram showing an example of a circuit configuration of the time-to-digital converter, and fig. 1 (B) is a schematic diagram of time measurement in the time-to-digital converter.

Fig. 2 is a schematic diagram of time measurement in the time-to-digital converter of the present embodiment, and is a partial enlarged diagram of fig. 1 (B).

Fig. 3 is a schematic circuit block diagram showing an example of the arithmetic unit of the present embodiment.

Fig. 4 is a circuit block schematic diagram showing an example of the zero-number counting unit according to the present embodiment.

Fig. 5 is a circuit block schematic diagram showing an example of the sampling circuit of the present embodiment.

Fig. 6 shows an example of a sampling clock in the zero-number counting unit according to the present embodiment.

Fig. 7 is an image obtained by capturing a state of wiring from the signal generating unit to the frequency multiplying unit in the present embodiment.

Fig. 8 is an image obtained by capturing a state of wiring from the signal generating unit to the frequency multiplying unit in the present embodiment.

Symbol description

10: time-to-digital converter

11: attenuator

12: filtering circuit

13: first signal generating unit

14: second signal generating unit

15: counting unit

16: reference counting unit

17: zero number counting unit

19: counting/converting unit

20: arithmetic unit

171. 171A to 171H: a frequency multiplication unit;

172. 172A to 172H: phase shift unit

TF, TF1, TF2: zero time interval

TM: master time interval

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Like reference numerals refer to like parts throughout the various figures of the present embodiment.

Fig. 1 is a diagram showing an outline of the time-to-digital converter 10 according to the present embodiment, and (a) of the diagram is a schematic block diagram showing an example of a circuit configuration of the time-to-digital converter 10, and (B) of the diagram is a schematic diagram of time measurement in the time-to-digital converter 10 according to the present embodiment. Fig. 2 is an enlarged view of a part (waveforms of the comparators a and B) of fig. 1 (B).

Referring to fig. 1 (a), the time-to-digital converter 10 of the present embodiment includes, for example, an attenuator 11, a filter circuit (e.g., a low-pass filter) 12, a first signal generation unit 13, a second signal generation unit 14, and an arithmetic unit 20. The arithmetic unit 20 has a counting unit 15 (reference counting unit 16 and zero number counting unit 17), a counting/converting unit 19, and the like.

Referring to fig. 1 (B), the time-to-digital converter 10 measures a time interval T between a first time point T1 and a second time point T2 in an input waveform input via the attenuator 11 and the filter circuit 12. The time-to-digital converter 10 of the present embodiment is connected to a DUT (object to be measured, for example, a semiconductor element) not shown (via a buffer circuit if necessary) upstream of the attenuator 11, for example. That is, the input waveform is, for example, a voltage waveform output from the semiconductor element to be measured in this example. As an example of the time measurement in this case, measurement of a time interval T between a first time point T1 at which va (for example, 20%) of the voltage (waveform) output by the DUT is reached and a second time point T2 at which vb (for example, 80%) of the voltage (waveform) output by the DUT is reached, and the like. The time-to-digital converter 10 constitutes a semiconductor inspection device together with, for example, other information processing devices (e.g., a PC or the like).

The first time point t1 and the second time point t2 are time points when the generation of a predetermined signal (timing signal, trigger signal) is triggered, respectively. As an example, the time-to-digital converter 10 has a first signal generation unit 13 and a second signal generation unit 14, and the predetermined signal is a signal generated by the two signal generation units 13, 14. That is, the first signal generating unit 13 generates a first signal (timing signal, trigger signal) that is a trigger at the first time point t1, and the second signal generating unit 14 generates a second signal (timing signal, trigger signal) that is a trigger at the second time point t2. The first signal generating unit 13 and the second signal generating unit 14 are, for example, a comparator (comparator) a, a comparator (comparator) B, respectively.

As an example, the first signal generating unit 13 compares the first reference voltage Vref1 with the voltage Vin of the input waveform, outputs "L" (off) when the voltage Vin of the input waveform is lower than the first reference voltage Vref1, and outputs "H" (on) as the first signal when the voltage Vin of the input waveform is higher than the first reference voltage Vref 1. The second signal generation unit 14 compares the second reference voltage Vref2 with the voltage Vin of the input waveform, outputs "L" (off) when the voltage Vin of the input waveform is lower than the second reference voltage Vref2, and outputs "H" (on) as the second signal if the voltage Vin of the input waveform is higher than the second reference voltage Vref 2. That is, the output timing of the first signal ("H") is the first time point t1, and the output timing of the second signal ("H") is the second time point t2.

In the example of fig. 1B, the time when the first signal generating means becomes "H" (first time point T1) is the time when the measurement starts, the time when the second signal generating means becomes "H" (second time point T2) is the time when the measurement ends, and the time interval T from the first time point T1 to the second time point T2 is the measurement target.

The counting unit 15 is a unit that counts the time interval T based on the reference clock, and has a reference counting unit 16 and a zero number counting unit 17. Here, the reference clock is an internal clock generated by, for example, a phase synchronization circuit (PLL: phase locked loop: PLL circuit) based on an external clock input from a crystal oscillator or the like. The reference counting unit 16 counts the generated reference clock as the Main sampling clock Main CLK and the time interval T as an integer multiple of one cycle of the reference clock. Specifically, referring to fig. 2, the reference counting unit 16 counts the number of clocks (integers) included in the time interval T using, for example, a reference clock (internal clock) having a frequency of 125MHz (one period of 8 ns) as the sampling clock Main CLK. Here, the arbitrary time interval T is not necessarily an integer multiple of one cycle of the sampling clock Main CLK (reference clock).

The reference counting unit 16 sets the sampling clock Main CLK as a start clock (1 st clock) when the start time point of the time interval T is synchronized with the sampling clock Main CLK, and sets the sampling clock Main CLK, which arrives first after the start time point, as a start clock (1 st clock) when the start time point of the time interval T is not synchronized with the sampling clock Main CLK, for example. When the end time point of the time interval T is synchronous with the sampling clock Main CLK, the sampling clock Main CLK is set as an end clock (nth clock, N is an integer), and when the end time point of the time interval T is not synchronous with the sampling clock Main CLK, the sampling clock Main CLK which arrives first after the end time point is set as an end clock (nth clock, N is an integer). Then, the number of clocks (N-1 clocks) included in the time interval T is counted, and the time corresponding to the number of clocks is measured as the master time interval TM.

In the example shown in fig. 2, the first time point T1 and the second time point T2 are each located midway of 1 cycle of the sampling clock Main CLK, that is, the start time point (T1) and the end time point (T2) of the time interval T are each not synchronized with the sampling clock Main CLK. In this case, the reference counting unit 16 counts the number of clocks (11=12-1) included from the start clock (the sampling clock Main CLK (the "1" th clock) that comes first after the start time point) to the end clock (the sampling clock Main CLK (the "12" th clock) that comes first after the end time point) as the sampling clock Main CLK (corresponding to the Main time interval TM) included in the time interval T.

The zero-number counting unit 17 counts the zero-number time interval TF as a margin or shortage of the main time interval TM with respect to the time interval T. That is, for a time (zero-number time interval TF shown by hatching in fig. 2) which is not longer than 1 cycle of the sampling clock Main CLK, counting is performed with a cycle (high resolution) shorter than 1 cycle of the sampling clock Main CLK.

In the example shown in fig. 2, if the time interval T of the measurement target is compared with the Main time interval TM, there are a time interval (zero-number time interval on the measurement start side) TF1 from the first time point T1 to the rising edge of the start clock (1 st sampling clock Main CLK) and a time interval (zero-number time interval on the measurement end side) TF2 from the second time point T2 to the timing of the rising edge of the end clock (12 th sampling clock Main CLK). The zero number counting unit 17 counts the number of clocks corresponding to the zero number time interval TF1 and the zero number time interval TF2, but 1 cycle of the clock in this case is a cycle shorter than 1 cycle of the sampling clock Main CLK, which will be described later.

The counting/converting unit 19 calculates a time interval based on the count result of the reference counting unit and the count result of the zero number counting unit, and converts it into a digital value. Specifically, the time interval T is calculated by adding or subtracting the zero-number time interval TF1 to or from the main time interval TM and subtracting or adding (substantially subtracting) the zero-number time interval TF2. In this example, time interval t=master time interval tm+zero time interval TF 1-zero time interval TF2. In addition, the count/conversion unit 19 digitally converts the calculated time interval T and outputs it.

The zero number counting unit 17 will be described with reference to fig. 3 to 6. Fig. 3 is a circuit block diagram schematically showing an example of the operation unit 20, fig. 4 is a circuit block diagram schematically showing an example of the zero-number counting unit 17, fig. 5 is a circuit block diagram schematically showing an example of the sampling circuit 170, and fig. 6 is an example of the sampling clock Main CLK in the zero-number counting unit 17.

As shown in fig. 3, the arithmetic unit 20 of the present embodiment includes a reference counting unit 16, a zero number counting unit 17, and a counting/converting unit 19, and is configured by an FPGA (field-programmable gate array: field programmable gate array) application, for example. The data from the first signal generating unit 13 and the second signal generating unit 14 are input to the zero number counting unit 17. The zero number counting unit 17 is an element applied to, for example, an FPGA, and can perform processing such as frequency division, frequency multiplication, and phase shift of a clock. It should be noted that these processes may also be constituted by a Digital Clock Manager (DCM).

In the present embodiment, the zero number counting unit 17 includes a frequency multiplication unit group including n (n is an integer of 2 or more) frequency multiplication units 171, and a phase shift unit 172. In the present embodiment, the first signal generating unit 13 and the second signal generating unit 14 are connected to the frequency multiplier unit group, respectively. Since the configuration of the frequency multiplication unit groups is the same, the frequency multiplication unit groups (frequency multiplication units 171A to 171H) connected to the first signal generation unit 13 will be described below as an example, but the frequency multiplication unit groups (frequency multiplication units 171I to 171P) connected to the second signal generation unit 14 are also the same.

The frequency multiplication unit group is constituted by a plurality of frequency multiplication units 171 (for example, frequency multiplication units 171A to 171H), and the frequency multiplication units 171 are respectively constituted by, for example, SERDES circuits (SERializer/deseriaalizer: serial-parallel interconversion circuits). The frequency multiplying unit 171 generates a signal that samples the signal (data corresponding to the zero-number time intervals TF1, TF 2) input from the first signal generating unit 13 (the second signal generating unit 14) with m-multiplication (m is an integer of 2 or more) of the reference clock (the sampling clock Main CLK).

The n phase shift units 172 shift the phase of the multiplied sampling clock MCLK generated by the n multiplying units 171 one by 360 °/n (the number of multiplying units 171), for example, a unit including a phase synchronization circuit (PLL circuit).

Here, n is 8 and m is 8 as an example (n and m may not be the same number). That is, in the example shown in fig. 3, the zero number count unit 17 has a frequency multiplication unit group constituted by 8 frequency multiplication units (SERDES circuits) 171A to 171H, and a frequency multiplication unit group constituted by 8 frequency multiplication units (SERDES circuits) 171I to 171P. Each of the frequency multiplying units 171A to 171P generates a signal (frequency-multiplied sampling clock MCLK (see fig. 2)) that samples data corresponding to the zero-number time intervals TF1, TF2 by 8 times the reference clock (sampling clock Main CLK).

The phase shift unit 172 shifts the phase of the multiplied sampling clock MCLK generated by one multiplying unit group (multiplying units 171A to 171H) one by 45 ° (=360/8°). In the present embodiment, the phase shift sections 172 are provided corresponding to the frequency multiplication sections 171A to 171H, but as an example, 4 phase shift sections (PLL circuits) 172 (172A, 172C, 172E, 172G) are provided with inverting circuits (not shown) respectively, and are configured as phase inverting circuits (phase shift sections) 172B, 172D, 172F, 172H, as a section for shifting the phase of the frequency multiplied sampling clock MCLK generated by the frequency multiplication sections 171A to 171H. Instead of using a phase inverting circuit, 8 phase shift units (PLL circuits) 172A to 172H corresponding to the frequency multiplication units 171A to 171H may be provided.

In the circuit diagram shown in fig. 3, as an example, the phase shift units 172A to 172H, the reference count unit 16, and the count/conversion unit 19 are shared by the frequency multiplication unit group (frequency multiplication units 171A to 171H) connected to the first signal generation unit 13, and the frequency multiplication unit group (frequency multiplication units 171I to 171P) connected to the second signal generation unit 14. However, the configuration is not limited to this, and the phase shift section 172, the reference count section 16, and the count/conversion section 19 may be provided in correspondence with the frequency multiplication section group.

The specific description will be given with reference to fig. 4. The drawing is a circuit block diagram showing the zero number counter 17 (the frequency multiplier unit group connected to the first signal generator 13) of fig. 3.

The phase shift unit 172A holds the multiplied sampling clock MCLK generated by the multiplying unit 171A at the same phase (phase 0 °) as the timing of the rising edge of a certain period of the reference clock (sampling clock Main CLK) (hereinafter referred to as reference timing), and generates (generates, outputs) the multiplied sampling clock MCLK1.

The phase shift unit 172C shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171C by 45 ° from the above reference timing, generating a multiplied sampling clock MCLK3.

The phase shift unit 172E shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171E by 90 ° from the reference timing, generating a multiplied sampling clock MCLK5.

The phase shift unit 172G shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171G by 135 ° from the reference timing, generating a multiplied sampling clock MCLK7.

The phase shift unit 172B shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171B. In this example, the phase shift unit 172B inverts the output of the phase shift unit 172A by 180 ° by an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK2 whose phase is shifted by 180 ° from the reference timing.

The phase shift unit 172D shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171D. In this example, the phase shift unit 172D inverts the output of the phase shift unit 172C by 180 ° by an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK4 whose phase is shifted by 225 ° from the reference timing.

The phase shift unit 172F shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171F. In this example, the phase shift unit 172F inverts the output of the phase shift unit 172E by 180 ° by an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK6 whose phase is shifted 270 ° from the reference timing.

The phase shift unit 172H shifts the phase of the multiplied sampling clock MCLK generated by the frequency multiplication unit 171H. In this example, the phase shift unit 172H inverts the output of the phase shift unit 172G by 180 ° by an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK8 whose phase is shifted by 315 ° from the reference timing.

In this way, the sampling circuit 170 is constituted by the set of the frequency multiplying unit 171 and the phase shifting unit 172, and the zero number counting unit 17 has a plurality (here, 8) of sampling circuits 170A to 170H.

Fig. 5 is a schematic block diagram showing an example of the configuration of the sampling circuit 170 (for example, the sampling circuit 170A including the frequency multiplier 171A and the phase shifter 172A).

The frequency multiplication unit 171 (for example, the frequency multiplication unit 171A) has a reception circuit (for example, a flip-flop circuit) 201, a 1/m frequency divider 202, and 1: m-demultiplexer (Demux) 203.m is the frequency multiplication number (frequency multiplication, here, m=8 as an example) as described above. In addition, the phase shift unit 172 (for example, the phase shift unit 172A) has a PLL circuit 204 that performs frequency multiplication processing on an input signal and a phase adjuster 205.

In the phase shift unit 172, an input of an external clock CLK (here, a clock of a crystal oscillator of, for example, 50 MHz) is received, which is multiplied by, for example, 20 times in the PLL path 204, thereby generating a clock RCLK of 1 GHz. The phase adjuster 205 generates a multiplied sampling clock MCLK in which the phase of the clock RCLK is shifted (delayed) 360 °/n (here, n=8) one by one from the reference timing, and outputs it to the receiving circuit 201 of the multiplying unit 171.

Here, the phase shift amount of the phase shift unit 172A from the reference time is set to 0 °, and the other phase shift units 172B to 172H are shifted 45 ° (=360 °/8) from the reference time one by one.

The receiving circuit 201 of the frequency multiplication unit 171 receives input data Din (data corresponding to the zero-number time interval TF based on the first signal or the second signal) from the comparator (comparator a or comparator B) and transmits a serial data signal of the number of bits (8 bits in this case) corresponding to the frequency multiplication (8 in this case) to the Demux203 bit by bit in synchronization with the frequency multiplication sampling clock MCLK of 1 GHz. That is, in this case, the input data Din is sampled at a period of 1 GHz.

The 1/n (hereinafter, 1/8) divider 202 divides the multiplied sampling clock MCLK (1 GHz) generated by the phase adjuster 205 by the inverse (1/8) of the multiplied frequency to generate a divided clock (125 MHz). The frequency (125 MHz) is an internal clock (sampling clock Main CLK).

In Demux203, the serial data signal is converted into an 8-bit parallel data signal based on the serial data signal output from reception circuit 201 and the frequency division clock (125 MHz), and is output as an 8-bit parallel data signal Dout in synchronization with the frequency division clock. That is, the output from Demux203 is multiplied (8 times) by the number of data with respect to 1 input of Din.

In each sampling circuit 170, the phase-shifted multiplied sampling clock MCLK, the parallel data signal Dout as the output of Demux203, and the divided clock (sampling clock Main CLK) of 125MHz divided by 1/8 are generated from the clock RCLK of 1GHz and are all of the same phase.

In each of the sampling circuits 170 (170A to 170H), the phase shift amount (phase change rate) by the phase adjuster 205 is 360 °/n, and n in this case is the number of inputs to the receiving circuit 201. For the phase adjuster 205, a number equivalent to the input number or the input number/2 (in the case of using an inverting circuit) is required.

With this configuration, the zero number counting unit 17 according to the present embodiment obtains the number of samples (resolution) represented by the following equation 1.

Number of samples (resolution) =

Inverse of reference clock (sampling clock Main CLK)/(number of frequency multiplication units 171 (number of inputs) ×number of frequency multiplication) (1)

Specifically, in the example of the present embodiment, resolution= (1/125 MHz)/(8×8) =125 ps.

As a result, as shown in fig. 6, the zero count counting unit 17 can measure the zero count time interval TF (based on the signals of the first signal and the second signal) input by the frequency-multiplied sampling clocks MCLK1 to MCLK8 (1 GHz, 1-cycle-of-resolution 125 ps) obtained by (apparently) multiplying the sampling clock Main CLK (125 MHz, 1-cycle-of-resolution 8 ns) by 64 analog.

That is, the zero-number time intervals TF1 (corresponding to the number of clocks of the zero-number time interval TF 1) based on the generation of the first signal shown in fig. 2 are counted by the double sampling clocks MCLK1 to MCLK8, and the zero-number time intervals TF2 (corresponding to the number of clocks of the zero-number time interval TF 2) based on the generation of the second signal are similarly counted by the double sampling clocks MCLK1 to MCLK8 of the zero-number counting means 17.

In the counting/converting unit 19, the number of clocks corresponding to the main time interval TM and the number of clocks corresponding to the zero-number time intervals TF1, TF2 are calculated to calculate the time interval T. In this example, time interval t=master time interval tm+zero number time interval TF 1-zero number time interval TF2 (see fig. 2). In addition, the count/conversion unit 19 digitally converts the calculated time interval T and outputs it.

Although not shown in detail, for example, data sampled by shifting the phase (data obtained by multiplying sampling clocks MCLK1 to MCLK8 having a phase of 45 ° to 315 °) are all adjusted (restored) to the same phase (phase 0 °) based on the sampling clock Main CLK (125 MHz) in the counter/converter unit 19, and are calculated by being arranged (sequentially rearranged).

As described above, in the present embodiment, n (8 in this example) frequency doubling units 171 capable of generating frequency-doubled sampling clocks that multiply the reference clock (sampling clock Main CLK) by m (for example, 8 frequency doubling) are provided, whereby the sampling clock Main CLK of, for example, 125MHz (1 period of 8 ns) can be frequency-doubled by 64 to become frequency-doubled sampling clocks of 125ps. Thus, the zero-number time intervals TF1 and TF2 can be counted with high resolution (high accuracy), and the time-to-digital converter 10 suitable for the semiconductor inspection apparatus for performing time measurement of the DUT can be provided.

Further, since the arithmetic unit 20 (the frequency multiplication unit 171, the phase shift unit 172, the count/conversion unit 19, and the like) can be constituted by an FPGA, the cost can be suppressed and the resolution (high accuracy) can be realized without requiring an ASIC analog circuit design. In addition, although high-accuracy and high-resolution measurement can be performed by using an oscilloscope and a PC (personal computer), there is a limit to high-speed processing. According to the present embodiment, the arithmetic unit 20 can be constituted by an FPGA, and therefore, high-speed processing can be performed in addition to high resolution (high accuracy).

Here, the configuration of the frequency multiplication cell groups (frequency multiplication cells 171A to 171H) connected to the first signal generation cell 13 is the same as the configuration of the frequency multiplication cell groups (171I to 171P) connected to the second signal generation cell 14, and each wiring is equal in length when the frequency multiplication cell groups are connected to the frequency multiplication cell 171 that generates the frequency multiplication sampling clock MCLK of the same phase.

Specifically, the first signal generating unit 13 is connected to the frequency doubling unit 171A (phase shift 0 °) through a first wiring WA1, and the second signal generating unit 14 is connected to the frequency doubling unit 171I (phase shift 0 °) through a second wiring WA 2. The first wiring WA1 is equal in length to the second wiring WA 2. In this embodiment, the term "equal length" of the wirings means that a plurality of wirings (for example, the first wiring WA1 and the second wiring WA 2) have equal and substantially equal lengths (substantially) in terms of design (although there are cases where errors in design are included, the lengths are not intentionally changed).

Similarly, the first signal generating unit 13 is connected to the frequency doubling unit 171B (phase offset 180 °) through the first wiring WB1, and the second signal generating unit 14 is connected to the frequency doubling unit 171J (phase offset 180 °) through the second wiring WB 2. The first wiring WB1 is equal in length to the second wiring WB 2.

The first signal generation unit 13 is connected to the frequency multiplication unit 171C (phase shift 45 °) through a first wiring WC1, and the second signal generation unit 14 is connected to the frequency multiplication unit 171K (phase shift 45 °) through a second wiring WC 2. The first wiring WC1 is equal in length to the second wiring WC 2.

The first signal generation unit 13 is connected to the frequency multiplication unit 171D (phase shift 225 °) through a first wiring WD1, and the second signal generation unit 14 is connected to the frequency multiplication unit 171L (phase shift 225 °) through a second wiring WD 2. The first wiring WD1 and the second wiring WD2 are equal in length.

The first signal generating unit 13 is connected to the frequency doubling unit 171E (phase shift 90 °) through a first wiring WE1, and the second signal generating unit 14 is connected to the frequency doubling unit 171M (phase shift 90 °) through a second wiring WE 2. The first wiring WE1 and the second wiring WE2 are equal in length.

The first signal generating unit 13 is connected to the frequency doubling unit 171F (phase shift 270 °) through a first wiring WF1, and the second signal generating unit 14 is connected to the frequency doubling unit 171N (phase shift 270 °) through a second wiring WF 2. The first wiring WF1 is equal in length to the second wiring WF 2.

The first signal generating unit 13 is connected to the frequency doubling unit 171G (phase shift 135 °) through a first wiring WG1, and the second signal generating unit 14 is connected to the frequency doubling unit 171O (phase shift 135 °) through a second wiring WG 2. Further, the first wiring WG1 and the second wiring WG2 are equal in length.

The first signal generating unit 13 is connected to the frequency doubling unit 171H (phase shift 315 °) through a first wiring WH1, and the second signal generating unit 14 is connected to the frequency doubling unit 171P (phase shift 315 °) through a second wiring WH 2. The first wiring WH1 and the second wiring WH2 are equal in length.

Fig. 7 and 8 are images obtained by capturing the actual wiring from the first signal generating unit 13 and the second signal generating unit 14 to the frequency doubling unit 171, for example, fig. 7 (a) is an image showing the first wiring WA1 and the second wiring WA2 in the vicinity of the frequency doubling units 171A, 171I, fig. 7 (B) is an image showing the first wiring WB1 and the second wiring WB2 in the vicinity of the frequency doubling units 171B, 171J, fig. 8 (a) is an image showing the first wiring WC1 and the second wiring WC2 in the vicinity of the frequency doubling units 171C, 171K, and fig. 8 (B) is an image showing the first wiring WD1 and the second wiring WD2 in the vicinity of the frequency doubling units 171D, 171L. As described above, the frequency doubling units 171A to 171D and 171I to 171L are incorporated in, for example, an FPGA.

Thus, when the zero-number time interval TF1 on the measurement start side and the zero-number time interval TF2 on the measurement end side are counted, the wiring lengths up to the generation unit (the frequency multiplication unit 171) that becomes the frequency-multiplied sampling clock of the same phase are equal. That is, when time measurement is performed with the first signal output from the first signal generating unit 13 and the second signal output from the second signal generating unit 14 as a trigger, signal delay due to a difference in wiring length can be avoided.

In the present embodiment, sampling of 125ps can be performed for 1 cycle by apparently multiplying the sampling clock Main CLK by 64. On the other hand, the time interval T to be measured is a time between the time when the first signal is the trigger and the time when the second signal is the trigger (because two signals are used), and delay in input of the first signal and/or the second signal becomes a fatal problem in measurement on the picosecond scale.

Specifically, for example, if the wiring lengths of the first wiring WA1 and the second wiring WA2 are different, unintended time variation (in extreme cases, time reversal of arrival of the first signal and the second signal, etc.) occurs in the first signal and/or the second signal input to the frequency multiplication unit 171A, and accurate time measurement cannot be performed.

In the present embodiment, since the first signal and the second signal are input to the multiplier unit groups (171A to 171H, 171I to 171P) that generate the multiplied sampling clocks of the same phase with the same wiring length, there is no error in hardware, and the absolute accuracy of time can be ensured. More specifically, by performing the equal-length wiring, the time measurement of the length of 1 cycle or less of the reference clock can be performed, and the error in the time delay (time measurement) can be suppressed to the minimum resolution or less. Specifically, although the error varies depending on the reference clock frequency and/or the frequency multiplication number, in the present embodiment, the measurement error can be suppressed to 125ps or less (in the case of 1 cycle 8 ns) which is the minimum resolution by performing the equal-length wiring.

Further, since the phase shift section 172 and the count/conversion section 19 are shared (use the same section (circuit)) between the first signal generation section 13 and the second signal generation section 14, the device can be miniaturized and reduced in cost, and performance variations in the circuit can be avoided, thereby enabling high-precision measurement.

While the time-to-digital converter 10 of the present embodiment has been described above, the signal generation unit may be single. That is, the time between the rising edge and the falling edge of the signal (first signal) of one signal generating means may be measured as a trigger. The number of signal generating units may be 3 or more (for example, 4).

In the above embodiment, the case where one input waveform is illustrated, but a plurality of input waveforms may be used. For example, the first signal may be a signal for determining a certain time point of the input waveform a (for example, a first time point T1 which is 50% of the input voltage a), and the second signal may be a signal for determining a certain time point of the input waveform b (for example, a second time point T2 which is 50% of the input voltage b), and the time interval T between the first time point T1 and the second time point T2 may be measured.

The first signal and/or the second signal may be signals triggered by a rising edge or signals triggered by a falling edge. As described above, the present embodiment can be applied independently of a time-dependent measurement method.

In the above example, the phase shift unit 172 and the count/conversion unit 19 and the like connected to the first signal generation unit 13 and the second signal generation unit 14 are shown as being shared, but the phase shift unit 172 may be provided to the first signal generation unit 13 and the second signal generation unit 14, respectively.

In the above embodiment, the counting means 15 has the reference counting means 16 and the zero-number counting means 17, and the zero-number counting means 17 counts the zero-number time interval TF as the margin or the shortage of the main time interval TM counted by the reference counting means 16. However, the present invention is not limited to this, and the count in all the periods of the time interval T to be measured (the count in all the periods with high resolution) may be performed by the zero-number counting means 17. In this case, in order to prevent malfunction caused by noise in the vicinity of the first reference voltage Vref1 of the first signal generating unit 13 (the same applies to the second signal generating unit 14) due to high sensitivity (high resolution) measurement by the zero number counting unit 17, it is preferable to adjust the sensitivity of the first signal generating unit 13. On the other hand, as in the above embodiment, the reference counter 16 and the zero-number counter 17 are used together as the counter 15, whereby the capacity of the FPGA can be saved.

For example, the frequency between a certain point in time when the input voltage increases from 0% (for example, a timing of 50%) and a certain point in time when the input voltage decreases from 100% (for example, a timing of 50%) may be counted (used as a frequency counter).

In the above embodiment, the case where the frequency multiplication unit group (frequency multiplication units 171A to 171H) connected to the first signal generation unit 13 and the frequency multiplication unit group (frequency multiplication units 171I to 171P) connected to the second signal generation unit 14 are different frequency multiplication unit groups has been exemplified, but one frequency multiplication unit group may be shared.

The time-to-digital converter 10 of the present invention is not limited to the above embodiment, and it is obvious that various modifications can be made without departing from the scope of the present invention.

Industrial applicability

The time-to-digital converter of the present invention can be used in the field of semiconductor inspection devices, for example.

Claims (22)

1. A time-to-digital converter for measuring a time interval between a first point in time and a second point in time in an input waveform, the time-to-digital converter comprising:

a reference counting unit that counts a main time interval with respect to the time interval as an integer multiple of a period of a reference clock;

a zero number counting unit that counts a zero number time interval as a margin or a shortage of the master time interval with respect to the time interval;

a counting/converting unit that calculates the time interval based on the main time interval and the zero-number time interval, and converts it into a digital value;

a first signal generation unit that generates a first signal that becomes a trigger of the first time point; and

a second signal generation unit that generates a second signal that becomes a trigger at the second time point,

the zero-number counting unit has:

a plurality of frequency doubling unit sets; and

a phase shift unit for shifting the phase of the optical signal,

the plurality of frequency multiplication unit groups are respectively composed of n (n is an integer more than 2) frequency multiplication units, the n frequency multiplication units respectively generate signals which sample signals corresponding to the zero time interval by m frequency multiplication (m is an integer more than 2) of the reference clock,

the phase shifting unit shifts the respective phases of the signals generated by the n frequency doubling units by 360 DEG/n,

the first signal generating unit is connected to one of the frequency multiplying unit groups (hereinafter, referred to as a "first frequency multiplying unit group"),

the second signal generating unit is connected to another one of the frequency multiplying unit groups (hereinafter, referred to as "second frequency multiplying unit group").

2. The time-to-digital converter of claim 1, wherein,

the first signal generating unit is connected with a first frequency doubling unit in the n frequency doubling units of the first frequency doubling unit group through a first wiring,

the second signal generating unit is connected with a second frequency doubling unit in the n frequency doubling units of the second frequency doubling unit group through a second wiring,

the first wiring is equal in length to the second wiring.

3. A time-to-digital converter according to claim 1 or 2, characterized in that,

the first signal generating unit is connected with a third frequency doubling unit of the n frequency doubling units of the first frequency doubling unit group through a third wiring,

the second signal generating unit is connected with a fourth frequency multiplying unit of the n frequency multiplying units of the second frequency multiplying unit group through a fourth wiring,

the third wiring is equal in length to the fourth wiring.

4. A time-to-digital converter according to any of claims 1 to 3, characterized in that,

the first signal generating unit and the second signal generating unit are comparators, respectively.

5. A time-to-digital converter according to any of claims 1 to 4,

the input waveform is a voltage waveform output from the device under measurement.

6. A time-to-digital converter according to any of claims 1 to 5,

and m is 8.

7. A time-to-digital converter according to any one of claims 1 to 6,

and n is 8.

8. A time-to-digital converter for measuring a time interval between a first point in time and a second point in time in an input waveform, the time-to-digital converter comprising:

a reference counting unit that counts a main time interval with respect to the time interval as an integer multiple of a period of a reference clock; and

a zero number counting unit that counts a zero number time interval as a margin, a shortage of the main time interval with respect to the time interval,

the zero-number counting unit has:

a first frequency multiplication unit group that receives a first signal that becomes a trigger of the first time point;

a second frequency multiplication unit group that receives a second signal that becomes a trigger at the second time point; and

a phase shift unit for shifting the phase of the optical signal,

the first frequency multiplication unit group and the second frequency multiplication unit group are respectively composed of n (n is an integer more than 2) frequency multiplication units, the n frequency multiplication units respectively generate signals for sampling signals corresponding to the zero time interval by m frequency multiplication (m is an integer more than 2) of the reference clock,

the phase shifting unit shifts the respective phases of the signals generated by the n frequency doubling units by 360 DEG/n one by one.

9. The time-to-digital converter of claim 8, wherein,

the first signal is input to a first frequency doubling unit of the n frequency doubling units of the first frequency doubling unit group via a first wiring,

the second signal is input to a first frequency doubling unit of the n frequency doubling units of the second frequency doubling unit group via a second wiring,

the first wiring is equal in length to the second wiring.

10. A time-to-digital converter according to claim 8 or 9, characterized in that,

the first signal is input to a second frequency doubling unit of the n frequency doubling units of the first frequency doubling unit group via a third wiring,

the second signal is input to a second frequency doubling unit of the n frequency doubling units of the second frequency doubling unit group via a fourth wiring,

the third wiring is equal in length to the fourth wiring.

11. The time-to-digital converter of claim 8, wherein,

the n frequency multiplication units of the first frequency multiplication unit group and the n frequency multiplication units of the second frequency multiplication unit group are respectively equal in phase offset based on the phase offset units.

12. The time-to-digital converter of claim 11, wherein,

the frequency multiplication units with equal phase offsets are respectively wired with the signal generation units of the first signal and the signal generation units of the second signal in an equal-length mode.

13. A time-to-digital converter according to claim 11 or 12, characterized in that,

the phase shift unit is shared in the first frequency multiplication unit group and the second frequency multiplication unit group.

14. A time-to-digital converter according to any of claims 8 to 13,

and m is 8.

15. The time-to-digital converter according to any of claims 8 to 14, wherein,

and n is 8.

16. A time-to-digital converter for measuring a time interval between a first point in time and a second point in time in an input waveform, the time-to-digital converter comprising:

a reference counting unit that counts a main time interval with respect to the time interval as an integer multiple of a period of a reference clock;

a zero number counting unit that counts a zero number time interval as a margin or a shortage of the master time interval with respect to the time interval;

a first signal generation unit that generates a first signal that becomes a trigger of the first time point; and

a second signal generation unit that generates a second signal that becomes a trigger at the second time point,

the zero-number counting unit has:

a frequency multiplication unit group connected to the first signal generation unit and the second signal generation unit; and

a phase shift unit for shifting the phase of the optical signal,

the frequency multiplication unit group is composed of n (n is an integer of 2 or more) frequency multiplication units which generate signals for sampling signals corresponding to the zero-number time interval with m frequency multiplication (m is an integer of 2 or more) of the reference clock,

the phase shifting unit shifts the respective phases of the signals generated by the n frequency doubling units by 360 DEG/n one by one.

17. The time-to-digital converter of claim 16, wherein,

the phase shift units are provided in plural in correspondence with the n frequency multiplication units, and at least one of the phase shift units includes an inverting circuit and is shared in at least two frequency multiplication units.

18. The time-to-digital converter of claim 17, wherein,

the number of the phase shift units is n/2.

19. The time-to-digital converter according to any of claims 16 to 18, wherein,

the first signal generating unit and the second signal generating unit are comparators, respectively.

20. The time-to-digital converter according to any of claims 16 to 19, wherein,

the input waveform is a voltage waveform output from the device under measurement.

21. The time-to-digital converter according to any of claims 16 to 20, wherein,

and m is 8.

22. The time-to-digital converter according to any of claims 16 to 21, wherein,

and n is 8.

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