JP7171004B1 - time to digital converter - Google Patents

Abstract

A time-to-digital converter capable of achieving high accuracy, high resolution, and high speed without requiring an ASIC or analog circuit design. SOLUTION: A time-to-digital converter 10 for measuring a time interval T between a first time point t1 and a second time point t2 in an input waveform is a reference for counting a main time interval TM as an integral multiple of the period of an input reference clock. A counting means 16 and a fractional counting means 17 for counting the fractional time interval TF as an excess or deficiency of the main time interval TM with respect to the time interval T, the fractional counting means 17 counting a first a first multiplication means group for receiving a signal; a second multiplication means group for receiving a second signal that triggers a second time point t2; Each multiplication unit group has n multiplications (n is an integer of 2 or more) that respectively generate signals for sampling the signals corresponding to the fractional time intervals TF by m multiplications of the reference clock (m is an integer of 2 or more). means 171; [Selection drawing] Fig. 3

Description

The present invention relates to a time-to-digital converter, and more particularly to a time-to-digital converter suitable for use in a semiconductor tester (semiconductor tester).

2. Description of the Related Art Conventionally, semiconductor inspection apparatuses for inspecting objects to be inspected, such as ICs and LSIs, are known to measure the time of signals (see, for example, Patent Document 1).

By the way, various methods have been proposed as methods for measuring time and frequency, and representative methods include the universal count method, the time expansion method, the time-voltage conversion method, and the time vernier method. .

For example, in the universal count method, the time is measured by measuring the specified time of the built-in reference clock input signal. In addition, the time expansion method is a method of converting time into voltage for measurement, in which the pulse width of a fractional time is charged and discharged by an integrating circuit to expand the pulse width.

JP-A-2003-139817

However, when time measurement is performed as a function of a semiconductor inspection device, the conventional method has limitations.

That is, in a semiconductor inspection device, time measurement becomes possible by providing a time-to-digital converter. Time-to-digital converters using -programmable gate arrays have become commonplace. Here, in a normal FPGA, the clock frequency is several 100 MHz, and the minimum measurable amount is limited to nsec order.

On the other hand, for time-to-digital converters used in semiconductor inspection equipment, high measurement (measurement) resolution, wide measurement dynamic range, and high speed measurement are important. is desired. In this case, 10 GHz is required as a reference clock, and in order to achieve high precision, high resolution, and high speed, it is necessary to create an ASIC or design an analog circuit separately. There is a problem of high cost. This applies not only to the universal counting method, but also to time-to-digital converters that employ other conventionally known methods.

Also, although it is possible to perform high-precision and high-resolution measurements using an oscilloscope and a PC (personal computer), there is a limit to high-speed processing in this case.

SUMMARY OF THE INVENTION In view of such circumstances, it is an object of the present invention to provide a time-to-digital converter capable of achieving high precision, high resolution, and high speed without requiring ASIC or analog circuit design.

The present invention is a time-to-digital converter for measuring a time interval between a first time point and a second time point in an input waveform, the reference counter counting a main time interval for said time interval as an integer multiple of the period of a reference clock. and fractional counting means for counting fractional time intervals as an excess or deficiency of said main time interval relative to said time interval, said fractional counting means receiving a first signal that triggers said first time point. a first multiplication means group, a second multiplication means group for receiving a second signal that triggers the second time point, and a phase shift means, wherein the first multiplication means group and the second multiplication means group n (n is an integer of 2 or more) multiplying means for respectively generating signals for sampling the signals corresponding to the fractional time intervals by multiplying the reference clock by m (m is an integer of 2 or more). and the phase shifter shifts the phase of each of the signals generated by the n multipliers by 360°/n .

According to the present invention, it is possible to provide a time-to-digital converter capable of achieving high precision, high resolution, and high speed without requiring ASIC or analog circuit design.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the time-to-digital converter of this embodiment, (A) It is the schematic block diagram which shows an example of a circuit configuration of a time-to-digital converter, (B) It is the schematic diagram of the time measurement in a time-to-digital converter. Moreover, FIG. 2 is a partially enlarged view of FIG. 1(C). It is a schematic diagram of the time measurement in the time-to-digital converter of this embodiment, and is a partially enlarged view of FIG.1(C). It is a circuit block schematic diagram which shows an example of the calculating means of this embodiment. It is a circuit block schematic diagram which shows an example of the fraction counting means of this embodiment. 1 is a circuit block schematic diagram showing an example of a sampling circuit of this embodiment; FIG. It is an example of a sampling clock in the fraction counting means of the present embodiment. It is the image which image|photographed the state of the wiring from the signal generation means in this embodiment to the multiplication means. It is the image which image|photographed the state of the wiring from the signal generation means in this embodiment to the multiplication means.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In each drawing of this embodiment, the same reference numerals denote the same parts.

FIG. 1 is a diagram showing an outline of a time-to-digital converter 10 of this embodiment, FIG. 1A is a schematic block diagram showing an example of the circuit configuration of the time-to-digital converter 10, and FIG. is a schematic diagram of time measurement in the time-to-digital converter 10 of the present embodiment. Moreover, FIG. 2 is a partially enlarged view of FIG. 1(C).

Referring to FIG. 1A, the time-to-digital converter 10 of this embodiment includes, for example, an attenuator 11, a filter circuit (for example, a low-pass filter) 12, a first signal generating means 13, a second signal It has generating means 14 and computing means 20 . The calculating means 20 has a counting means 15 (a reference counting means 16 and a fraction counting means 17), a counting/converting means 19, and the like.

Referring to FIG. 1B, time-to-digital converter 10 converts time interval T between first time point t1 and second time point t2 in the input waveform input via attenuator 11 and filter circuit 12 to It is to measure. For example, the time-to-digital converter 10 of the present embodiment is connected upstream of the attenuator 11 to a DUT (object to be measured, eg, a semiconductor device) (not shown) (via a buffer circuit as necessary). In other words, the input waveform is, for example, a voltage waveform output by the semiconductor device to be measured in this example. As an example of time measurement in this case, between the first time point t1 at which va% (eg, 20%) of the voltage (waveform) output by the DUT is reached and the second time point t2 at which vb% (eg, 80%) is reached , and so on. The time-to-digital converter 10 constitutes a semiconductor inspection device, for example, together with another information processing device (for example, a PC, etc.).

Each of the first time point t1 and the second time point t2 is a time point triggered by the generation of a predetermined signal (timing signal, trigger signal). The time-to-digital converter 10 has, as an example, a first signal generating means 13 and a second signal generating means 14, and the predetermined signal is a signal generated by the two signal generating means 13,14. That is, the first signal generating means 13 is means for generating a first signal (timing signal, trigger signal) that triggers the first time point t1, and the second signal generating means 14 serves as the trigger for the second time point t2. means for generating a second signal (timing signal, trigger signal). The first signal generating means 13 and the second signal generating means 14 are, for example, a comparator (comparator) A and a comparator (comparator) B, respectively.

As an example, the first signal generating means 13 compares the first reference voltage Vref1 and the voltage Vin of the input waveform, and outputs "L" (turns off) when the voltage Vin of the input waveform is lower than the first reference voltage Vref1. ), and when the voltage Vin of the input waveform becomes higher than the first reference voltage Vref1, the first signal “H” is output (turned on). The second signal generating means 14 compares the second reference voltage Vref2 with the voltage Vin of the input waveform, and outputs "L" (turns off) when the voltage Vin of the input waveform is lower than the second reference voltage Vref2. When the waveform voltage Vin becomes higher than the second reference voltage Vref2, the second signal "H" is output (turned on). That is, the output timing of the first signal (“H”) is the first time point t1, and the output timing of the second signal (“H”) is the second time point t2.

In the example of FIG. 2C, the timing (first time point t1) at which the first signal generating means becomes "H" is the timing to start measurement, and the timing (second time point t1) at which the second signal generating means becomes "H". Time t2) is the timing of the end of the measurement, and the time interval T to be measured is from the first time t1 to the second time t2.

The counting means 15 is means for counting the time interval T based on the reference clock, and has reference counting means 16 and fraction counting means 17 . Here, the reference clock is, for example, an internal clock generated by a phase locked loop (PLL circuit) or the like based on an external clock input from a crystal oscillator or the like. The reference counting means 16 is means for counting the time interval T as an integral multiple of one period of the generated reference clock as the main sampling clock Main CLK. Specifically, referring to FIG. 2, the reference counting means 16 uses a reference clock (internal clock) with a frequency of 125 MHz (one cycle of 8 ns) as a sampling clock Main CLK, and the number of clocks included in the time interval T (integer ) are counted. Here, the arbitrary time interval T is not necessarily an integral multiple of one cycle of the sampling clock Main CLK (reference clock).

For example, when the start time of the time interval T and the sampling clock Main CLK are synchronized, the reference counting means 16 uses the sampling clock Main CLK as a start clock (first clock), and determines the start time of the time interval T and When the sampling clock Main CLK is asynchronous, the sampling clock Main CLK that arrives first after the start time is taken as the start clock (first clock). Further, when the end point of the time interval T and the sampling clock Main CLK are synchronized, the sampling clock Main CLK is set as the end clock (Nth clock, N is an integer), and the end point of the time interval T and the sampling clock When the Main CLK is asynchronous, the first sampling clock Main CLK that arrives after the end time is taken as the end clock (Nth clock, N is an integer). Then, the number of clocks (N-1 clocks) included in the time interval T is counted, and the time corresponding to the number of clocks is measured as the main time interval TM.

In the example shown in FIG. 2, both the first time point t1 and the second time point t2 are in the middle of one cycle of the sampling clock Main CLK, that is, the time interval T starts (t1) and ends (t2). are asynchronous with the sampling clock Main CLK. In this case, the reference counting means 16 counts from the start clock (sampling clock Main CLK ("1"th clock) that arrives first after the start time point to the end clock (sampling clock Main CLK that comes first after the end time point) (" The number of clocks (11=12-1) included up to the 12th clock) is counted as the sampling clock Main CLK included in the time interval T (corresponding to the main time interval TM).

The fractional counting means 17 counts the fractional time interval TF as an excess or deficiency of the main time interval TM with respect to the time interval T. That is, the time less than one cycle of the sampling clock Main CLK (fractional time interval TF indicated by hatching in FIG. 1C) is counted in a cycle (high resolution) shorter than one cycle of the sampling clock Main CLK.

In the example shown in FIG. 4C, when the time interval T to be measured and the main time interval TM are compared, the time interval (measurement start There are a fractional time interval on the measurement end side) TF1 and a time interval (fractional time interval on the measurement end side) TF2 from the second time point t2 to the rising timing of the end clock (twelfth sampling clock Main CLK). The fraction counting means 17 counts the number of clocks corresponding to the fractional time interval TF1 and the fractional time interval TF2. In this case, one cycle of the clock is shorter than one cycle of the sampling clock Main CLK. will be described later.

The counting/converting means 19 calculates a time interval based on the counting result of the reference counting means and the counting result of the fractional counting means, and converts it into a digital value. Specifically, the time interval T is calculated by adding or subtracting the fractional time interval TF1 and subtracting or adding (basically subtracting) the fractional time interval TF2 from the main time interval TM. In this example, time interval T=major time interval TM+fractional time interval TF1−fractional time interval TF2. The counting/converting means 19 digitally converts the calculated time interval T and outputs it.

The fraction counting means 17 will be described with reference to FIGS. 3 to 6. FIG. FIG. 3 is a circuit block diagram schematically showing an example of the computing means 20, FIG. 4 is a circuit block diagram schematically showing an example of the fraction counting means 17, and FIG. FIG. 6 is a schematic circuit block diagram, and FIG. 6 is an example of the sampling clock Main CLK in the fraction counting means 17. As shown in FIG.

As shown in FIG. 3, the computing means 20 of this embodiment includes a reference counting means 16, a fraction counting means 17, and a counting/converting means 19, and is configured by an FPGA (field-programmable gate array) application as an example. . Data from the first signal generating means 13 and the second signal generating means 14 are input to the fraction counting means 17 . The fraction counting means 17 is, for example, one element of the FPGA application, and can execute processes such as clock frequency division, multiplication, and phase shift. Note that these processes may be configured by a digital clock manager (DCM).

In this embodiment, the fraction counting means 17 has a multiplication means group consisting of n (n is an integer equal to or greater than 2) multiplication means 171 and a phase shift means 172 . Further, in this embodiment, the first signal generating means 13 and the second signal generating means 14 are each connected to the multiplication means group. Since the configuration of the multiplication means group is the same, the multiplication means group (multiplication means 171A to 171H) connected to the first signal generation means 13 will be described below as an example, but the multiplication means connected to the second signal generation means 14 will be described. The same applies to groups (multiplication means 171I to 171P).

The multiplication means group is composed of a plurality of multiplication means 171 (for example, multiplication means 171A to 171H), and each of the multiplication means 171 is composed of, for example, a SERDES circuit (SERializer/DESerializer: serial-parallel mutual conversion circuit). The multiplier 171 multiplies the signal (data corresponding to the fractional time intervals TF1 and TF2) input from the first signal generator 13 (second signal generator 14) by m (m is an integer greater than or equal to 2).

The n phase shift means 172 shift the phase of the multiplied sampling clock MCLK generated by the n multiplication means 171 by 360°/n (the number of multiplication means 171). It is a means including a circuit (PLL circuit).

Here, as an example, n is 8 and m is also 8 (n and m may not be the same number). That is, in the example shown in FIG. 3, the fraction counting means 17 is composed of a multiplication means group consisting of eight multiplication means (SERDES circuits) 171A to 171H and eight multiplication means (SERDES circuits) 171I to 171P. and a multiplication means group. Each of the multipliers 171A to 171P generates a signal (multiplied sampling clock MCLK (see FIG. 2)) for sampling data corresponding to the fractional time intervals TF1 and TF2 by multiplying the reference clock (sampling clock Main CLK) by 8. .

The phase shifter 172 shifts the phase of the multiplied sampling clock MCLK respectively generated by one group of multipliers (multipliers 171A to 171H) by 45° (=360/8°). The phase shift means 172 are provided corresponding to the multiplication means 171A to 171H. In the present embodiment, as an example, four phase shift means (PLL circuits) 172 (172A to 172D) each include an inverting circuit (not shown). ) are provided as phase inverting circuits (phase shift means) 172E to 172H to shift the phase of the multiplied sampling clock MCLK generated by the multiplication means 171A to 171H. It is also possible to provide eight phase shift means (PLL circuits) 172A to 172H corresponding to the multiplication means 171A to 171H without using the phase inverting circuit.

Further, in the circuit diagram shown in FIG. 3, as an example, a multiplication means group (multiplication means 171A to 171H) connected to the first signal generation means 13 and a multiplication means group (multiplication means 171I) connected to the second signal generation means 14 171P) share the phase shift means 172A to 172H, the reference counting means 16 and the counting/converting means 19. FIG. However, the configuration is not limited to this, and the phase shift means 172, the reference counting means 16 and the counting/converting means 19 may be provided corresponding to the multiplication means groups.

A specific description will be given with reference to FIG. This figure is a circuit block diagram showing the fractional counting means 17 (the multiplication means group connected to the first signal generating means 13) extracted from FIG.

The phase shift means 172A shifts the multiplied sampling clock MCLK generated by the multiplication means 171A to the same phase (phase 0°) as the rising timing (hereinafter referred to as reference timing) of one cycle of the reference clock (sampling clock Main CLK). and generate (generate and output) the multiplied sampling clock MCLK1.

The phase shift means 172C shifts the phase of the multiplied sampling clock MCLK generated by the multiplication means 171C by 45° from the reference timing to generate the multiplied sampling clock MCLK3.

The phase shift means 172E shifts the phase of the multiplied sampling clock MCLK generated by the multiplication means 171E by 90° from the reference timing to generate the multiplied sampling clock MCLK5.

The phase shift means 172G shifts the phase of the multiplied sampling clock MCLK generated by the multiplication means 171G by 135° from the reference timing to generate the multiplied sampling clock MCLK7.

The phase shifter 172B shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171B. In this example, the phase shift means 172B inverts the output of the phase shift means 172A by 180° using an inverting circuit (not shown), thereby generating the multiplied sampling clock MCLK2 whose phase is shifted by 180° from the reference timing. .

The phase shifter 172D shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171D. In this example, the phase shift means 172D inverts the output of the phase shift means 172C by 180° using an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK4 whose phase is shifted by 225° from the reference timing. .

The phase shifter 172F shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171F. In this example, the phase shifter 172F inverts the output of the phase shifter 172E by 180° using an inverter circuit (not shown), thereby generating a multiplied sampling clock MCLK6 whose phase is shifted by 270° from the reference timing. .

The phase shifter 172H shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171H. In this example, the phase shift means 172H inverts the output of the phase shift means 172G by 180° using an inverting circuit (not shown), thereby generating a multiplied sampling clock MCLK8 whose phase is shifted by 315° from the reference timing. .

In this manner, a set of multiplier means 171 and phase shift means 172 constitute sampling circuit 170, and fraction counting means 17 has a plurality (here, eight) of sampling circuits 170A to 170H.

FIG. 5 is a schematic block diagram showing an example of the configuration of a sampling circuit 170 (for example, a sampling circuit 170A comprising a multiplier 171A and a phase shifter 172A).

The multiplier 171 (for example, the multiplier 171A) has a receiving circuit (for example, a flip-flop circuit) 201, a 1/m frequency divider 202, and a 1:m demultiplexer (Demux) 203. m is the multiplication number (multiplication rate, m=8 as an example here) as described above. Also, the phase shift means 172 (for example, phase shift means 172A) has a PLL circuit 204 that multiplies the input signal and a phase adjuster 15 .

The phase shift means 172 receives an input of an external clock CLK (here, a 50 MHz crystal oscillator clock, for example) and multiplies it by, for example, 20 times in the PLL path 204 to generate a 1 GHz clock RCLK. Phase adjuster 205 also generates multiplied sampling clock MCLK by shifting (delaying) the phase of clock RCLK by 360°/n (here, n=8) from the reference timing. Output.

Here, the phase shifter 172A sets the phase shift amount from the reference timing to 0°, and the other phase shifters 172B to 172H shift the reference timing by 45° (=360°/8).

The receiving circuit 201 of the multiplying means 171 receives the input data Din (data corresponding to the fractional time interval TF based on the first signal or the second signal) from the comparator (comparator A or comparator B), A serial data signal having a number of bits (here, 8 bits) corresponding to the multiplication rate (here, 8) is transmitted to the Demux 203 bit by bit in synchronization with the multiplied sampling clock MCLK. That is, in this case, the input data Din is sampled at a cycle of 1 GHz.

A 1/n (hereinafter referred to as 1/8) frequency divider 202 divides the frequency of the multiplied sampling clock MCLK (1 GHz) generated by the phase adjuster 205 by the reciprocal of the multiplication rate (1/8) to obtain a frequency-divided clock (125 MHz). ). This frequency (125 MHz) becomes an internal clock (sampling clock Main CLK).

The demux 203 converts the serial data signal into an 8-bit parallel data signal based on the serial data signal output from the receiving circuit 201 and the frequency-divided clock (125 MHz), and generates 8-bit parallel data in synchronization with the frequency-divided clock. output as a signal Dout. That is, the output from the Demux 203 is the number of data multiplied (eight times) with respect to one input of Din.

In each sampling circuit 170, the multiplied sampling clock MCLK whose phase is shifted by the phase adjuster 205, the parallel data signal Dout which is the output of the Demux 203, and the 125 MHz frequency-divided clock (sampling clock Main CLK) divided by 8 Both are generated from the clock RCLK of 1 GHz and have the same phase.

In each sampling circuit 170 (170A to 170H), the phase shift amount (phase change rate) by the phase adjuster 205 is 360°/n, where n is the number of inputs to the receiving circuit 201. . The phase adjuster 205 requires this number of inputs or a number corresponding to this number of inputs/2 (if an inverting circuit is used).

With such a configuration, the fraction counting means 17 of the present embodiment can obtain the sampling number (resolution) represented by the following equation 1.

Number of samples (resolution) =
Reciprocal of reference clock (sampling clock Main CLK)/(number of multiplication means 171 (number of inputs) x multiplication number) (Equation 1)

Specifically, in the example of this embodiment, resolution=(1/125 MHz)/(8×8)=125 ps.

As a result, as shown in FIG. 6, in the fraction counting means 17, the sampling clock Main CLK (125 MHz, resolution 1 cycle 8 ns) is pseudo-multiplied by 64 (1 GHz, resolution 1 cycle 125 ps). A fractional time interval TF (a signal based on the first signal and the second signal) input by the sampling clocks MCLK1 to MCLK8 can be measured, and high-resolution sampling is possible.

That is, (the number of clocks corresponding to) the fractional time interval TF1 based on the generation of the first signal shown in FIG. ) are counted by the multiplied sampling clocks MCLK1 to MCLK8 of the fraction counting means 17 in the same manner.

The counting/converting means 19 calculates the time interval T by calculating the number of clocks corresponding to the main time interval TM and the number of clocks corresponding to the fractional time intervals TF1 and TF2. In this example, time interval T=major time interval TM+fractional time interval TF1−fractional time interval TF2 (see FIG. 2). The counting/converting means 19 digitally converts the calculated time interval T and outputs it.

Although detailed illustration is omitted, for example, the data sampled by shifting the phase (data acquired by the multiplied sampling clocks MCLK1 to MCLK8 with phases of 45° to 315°) is, for example, a counting/converting means. 19, based on the sampling clock Main CLK (125 MHz), they are all arranged (restored) to have the same phase (phase 0°), aligned (order rearranged), and then operated.

Thus, in this embodiment, n (in this example, 8) multiplication means 171 capable of generating a multiplied sampling clock that multiplies the reference clock (sampling clock Main CLK) by m (for example, multiplies by 8) are provided. As a result, for example, the sampling clock Main CLK of 125 MHz (one cycle of 8 ns) can be apparently multiplied by 64 to obtain a multiplied sampling clock of 125 ps. As a result, the fractional time intervals TF1 and TF2 can be counted with high resolution (with high accuracy), and the time-to-digital converter 10 suitable for use in a semiconductor inspection device that measures the time of a DUT can be provided.

In addition, since the calculation means 20 (the multiplication means 171, the phase shift means 172, the counting/conversion means 19, etc.) can be configured by FPGA, the cost can be reduced and the resolution (high resolution) can be achieved without requiring ASIC analog circuit design. high precision) can be realized. Conventionally, by using an oscilloscope and a PC (personal computer), high-precision and high-resolution measurements were possible, but there was a limit to high-speed processing. According to this embodiment, since the computing means 20 can be configured by FPGA, high-speed processing can be achieved in addition to high resolution (high accuracy).

Here, the multiplication means group (multiplication means 171A to 171H) connected to the first signal generation means 13 and the multiplication means group (171I to 171P) connected to the second signal generation means 14 have the same configuration. In the group of means, when connecting to the multiplication means 171 for generating the multiplied sampling clock MCLK of the same phase, each wiring has the same length.

Specifically, the first signal generating means 13 is connected to the multiplying means 171A (0° phase shift) by the first wiring WA1, and the second signal generating means 14 is connected to the multiplying means 171I (0° phase shift) to the second signal generating means 171I (0° phase shift). They are connected by wiring WA2. The first wiring WA1 and the second wiring WA2 have the same length. Here, in the present embodiment, the “equal length” of the wiring means that a plurality of wirings (for example, the first wiring WA1 and the second wiring WA2) are equal in design length and substantially (approximately) equal in length. (It may contain design errors, but the length is not intentionally changed.)

Similarly, the first signal generation means 13 is connected to the multiplication means 171B (phase shift 180°) by the first wiring WB1, and the second signal generation means 14 is connected to the multiplication means 171J (phase shift 180°B and the second wiring). WB2, and the first wiring WB1 and the second wiring WB2 have the same length.

The first signal generation means 13 is connected to the multiplication means 171C (45° phase shift) by the first wiring WC1, and the second signal generation means 14 is connected to the multiplication means 171K (45° phase shift)C and the second wiring. Connect by WC2. The first wiring WC1 and the second wiring WC2 have the same length.

Further, the first signal generation means 13 is connected to the multiplication means 171D (phase shift 225°) and the first wiring WD1, and the second signal generation means 14 is connected to the multiplication means 171L (phase shift 225°) and the second wiring WD2. Connect by The first wiring WD1 and the second wiring WD2 have the same length.

The first signal generating means 13 is connected to the multiplying means 171E (90° phase shift) by the first wiring WE1, and the second signal generating means 14 is connected to the multiplying means 171M (90° phase shift) to the second wiring WE2. Connect by The first wiring WE1 and the second wiring WE2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171F (270° phase shift) by the first wiring WF1, and the second signal generating means 14 is connected to the multiplying means 171N (270° phase shift) F and the second wiring. Connect by WF2. The first wiring WF1 and the second wiring WF2 have the same length.

The first signal generation means 13 is connected to the multiplication means 171G (135° phase shift) and the first wiring WG1, and the second signal generation means 14 is connected to the multiplication means 171O (135° phase shift) and the second wiring WG2. Connect by The first wiring WG1 and the second wiring WG2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171H (315° phase shift) and the first wiring WH1, and the second signal generating means 14 is connected to the multiplying means 171P (315° phase shift) and the second wiring WH2. Connect by The first wiring WH1 and the second wiring WH2 have the same length.

7 and 8 are images of actual wiring from the first signal generating means 13 and the second signal generating means 14 to the multiplying means 171. For example, FIG. First wiring WA1 and second wiring WA2 near 171I, FIG. 8B shows first wiring WB1 and second wiring WB2 near multiplying means 171B and 171J, and FIG. 1 wiring WC1 and the second wiring WC2, and FIG. (B) is an image showing the first wiring WD1 and the second wiring WD2 near the multipliers 171D and 171L. As described above, the multipliers 171A to 171D and 171I to 171L are incorporated in FPGA, for example.

By doing so, when counting the fractional time interval TF1 on the measurement start side and the fractional time interval TF2 on the measurement end side, the wiring lengths to the multiplication sampling clock generating means (multiplication means 171) having the same phase become equal. In other words, signal delay due to the difference in wiring length can be avoided in time measurement triggered by the first signal output by the first signal generating means 13 and the second signal output by the second signal generating means 14 .

In the present embodiment, the sampling clock Main CLK is apparently multiplied by 64, thereby making it possible to perform sampling at a cycle of 125 ps. On the other hand, the time interval T to be measured is the time between the timing triggered by the first signal and the timing triggered by the second signal (because two signals are used), the first signal and/or the second signal. The input delay of two signals becomes a fatal problem in picosecond-order measurements.

Specifically, for example, if the wiring lengths of the first wiring WA1 and the second wiring WA2 are different, an unintended timing shift occurs in the first signal and/or the second signal input to the multiplier 171A (extreme For example, the arrival timings of the first signal and the second signal are reversed, etc.), making accurate time measurement impossible.

In this embodiment, since the first signal and the second signal are input with the same wiring length to the multiplication means group (171A to 171H, 171I to 171P) for generating the multiplied sample clocks of the same phase, hardware Absolute accuracy of time can be guaranteed without error. More specifically, the equal-length wiring makes it possible to measure the time of one period or less of the reference clock, and to suppress the time delay (time measurement) error to the minimum resolution or less. Specifically, although it varies depending on the reference clock frequency and the multiplication factor, the measurement error can be suppressed to the minimum resolution of 125 ps or less (in the case of one cycle of 8 ns) by using equal-length wiring in this embodiment.

In addition, since the phase shift means 172 and the counting/converting means 19 are shared by the first signal generating means 13 and the second signal generating means 14 (same means (circuits) are used), the size and cost of the device can be reduced. This contributes to the avoidance of variations in circuit performance, enabling highly accurate measurement.

Although the time-to-digital converter 10 of this embodiment has been described above, the number of signal generating means may be singular. That is, the timing between the rise and fall of the signal (first signal) of one signal generating means may be used as a trigger to measure the time between the two timings. Also, the number of signal generation means may be three or more (for example, four).

Further, although the above embodiment exemplifies the case where there is one input waveform, the number of input waveforms may be plural. For example, the first signal is a signal specifying a certain timing of the input waveform a (for example, the first time point t1 at which the input voltage a becomes 50%), and the second signal is a timing of the input waveform b (for example, the input t2, at which voltage b is 50%), and may measure the time interval T between the first time t1 and the second time t2.

Also, the first signal and/or the second signal may be triggered by rising or may be triggered by falling. Thus, this embodiment can be applied regardless of the time measurement method.

In the above example, the phase shift means 172 and the counting/converting means 19 connected to the first signal generating means 13 and the second signal generating means 14 are shared. It may be provided in each of the 1 signal generating means 13 and the second signal generating means 14 .

In the above-described embodiment, the counting means 15 has the reference counting means 16 and the fraction counting means 17, and the fraction counting means 17 counts the excess or deficiency of the main time interval TM counted by the reference counting means 16. A configuration for counting time intervals TF is illustrated. However, the present invention is not limited to this, and the fraction counting means 17 may perform counting during the entire period of the time interval T to be measured (perform high-resolution counting during the entire period). In that case, in order to prevent malfunction due to noise in the vicinity of the first reference voltage Vref1 of the first signal generating means 13 (same for the second signal generating means 14) due to high sensitivity (high resolution) measurement by the fraction counting means 17, It is desirable to adjust the sensitivity of the 1 signal generating means 13 . On the other hand, by using both the reference counting means 16 and the fraction counting means 17 as the counting means 15 as in the above embodiment, the capacity of the FPGA can be saved.

Also, for example, it counts the frequency between a timing when the input voltage rises from 0% (for example, when it reaches 50%) and a certain timing when it falls from 100% (for example, when it reaches 50%) (used as a frequency counter). to do).

Further, in the above embodiment, the multiplication means group (multiplication means 171A to 171H) connected to the first signal generation means 13 and the multiplication means group (multiplication means 171I to 171P) connected to the second signal generation means 14 have different multiplication rates. Although the case of the group of means has been exemplified, these may share one multiplication means group.

Incidentally, the time-to-digital converter 10 of the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

The time-to-digital converter of the present invention can be used, for example, in the field of semiconductor inspection equipment.

10 Time-to-Digital Converter 11 Attenuator 12 Filter Circuit 13 First Signal Generating Means 14 Second Signal Generating Means 15 Counting Means 16 Reference Counting Means 17 Fraction Counting Means 19 Computing Means 171, 171A to 171H Multiplier Means 172, 172A to 172H Phase shift means TF, TF1, TF2 fractional time interval TM main time interval

Claims (8)

A time-to-digital converter that measures the time interval between a first time point and a second time point in an input waveform,
reference counting means for counting a main time interval relative to said time interval as an integer multiple of the period of a reference clock;
fractional counting means for counting fractional time intervals as an excess or deficiency of the main time interval with respect to the time interval;
with
The fraction counting means
a first multiplication means group for receiving a first signal that triggers the first time point;
a second multiplier group for receiving a second signal that triggers the second point in time;
phase shift means;
The first multiplication unit group and the second multiplication unit group each generate n signals for sampling the signal corresponding to the fractional time interval by multiplying the reference clock by m (m is an integer equal to or greater than 2). (n is an integer of 2 or more) multiplication means ,
The phase shift means shifts the phase of each of the signals generated by the n multiplication means by 360°/n.
A time-to-digital converter characterized by: the first signal is input to the first multiplication means of the n multiplication means of the first multiplication means group through a first wiring;
the second signal is input to the first multiplication means of the n multiplication means of the second multiplication means group via a second wiring;
The first wiring and the second wiring have equal lengths,
A time-to-digital converter according to claim 1, characterized in that: the first signal is input to the second multiplication means of the n multiplication means of the first multiplication means group through a third wiring;
the second signal is input to the second multiplication means of the n multiplication means of the second multiplication means group via a fourth wiring;
The third wiring and the fourth wiring have equal lengths,
3. A time-to-digital converter according to claim 1 or 2, characterized in that: The n multiplication means of the first multiplication means group and the n multiplication means of the second multiplication means group have the same phase shift amount by the phase shift means,
A time-to-digital converter according to claim 1, characterized in that: The multiplication means having the same phase shift amount are wired with the same length as the signal generating means for the first signal and the second signal.
5. Time-to-digital converter according to claim 4, characterized in that: The phase shift means is shared by the first multiplication means group and the second multiplication means group,
6. A time-to-digital converter according to claim 4 or 5, characterized in that: said m is 8;
The time-to-digital converter according to any one of claims 1 to 6, characterized in that: wherein said n is 8;
The time-to-digital converter according to any one of claims 1 to 7, characterized in that:

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