CN102623291A - Data acquisition and parallel storage device and method - Google Patents
Data acquisition and parallel storage device and method Download PDFInfo
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- CN102623291A CN102623291A CN2012100142997A CN201210014299A CN102623291A CN 102623291 A CN102623291 A CN 102623291A CN 2012100142997 A CN2012100142997 A CN 2012100142997A CN 201210014299 A CN201210014299 A CN 201210014299A CN 102623291 A CN102623291 A CN 102623291A
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Abstract
The invention discloses a data acquisition and parallel storage device and the method thereof, which are used for ensuring the effective storage of data. The device comprises a clock generating module, a data buffering module and a data storage module which are mutually connected; the data buffering module comprises first to fourth first-in first-out buffers which are provided with write clock signals of the same frequency and different phases; the first to fourth first-in first-out buffers are respectively connected with the clock generating module; the first to fourth first-in first-out buffers are also respectively connected with the data storage module; and the data storage module is used for splicing four paths of data signals of the data buffering module into one path of signal according to a sequence of sampled signals.
Description
Technical field
The present invention relates to the time-of-flight mass spectrometer detection technique, particularly parallel storage device of time-of-flight mass spectrometer high speed data acquisition and method.
Background technology
Time-of-flight mass spectrometer (time-of-flight mass spectrometer, TOFMS) according to different ions in a vacuum the size of flight time judge its mass-to-charge ratio, analysis speed is fast, and can carry out the detection of single electric charge.In the middle of practical application, the flight time that the measurement of flight time mass spectrum not only relies on the primary ions pulse generator to send ion beam, but lean on the accumulative total of ion pulse signal many times.It is a subtransient (transient) that each ion pulse generator is triggered to, next group spectral line of the each transient recording of the data-acquisition system of time-of-flight mass spectrometer.The quantity that the spectral line of at every turn noting is added to and expects obtains a complete collection of illustrative plates.We use ADC (analog-to-digital converter; Analog to digital converter); At interval the ion detector of process amplification is exported signal with regular time and carry out record; And continuous transformation results deposited in the memory, last computer reads its data with PCI or USB and shows in real time with spectrogram.Because the ADC analog input bandwidth of time-of-flight mass spectrometer has only 10M, so its measuring range is very limited; In addition, sampling precision is also lower.
Summary of the invention
Primary and foremost purpose of the present invention is in order to solve the prior art sampling precision low, and the inaccurate technical problem of resulting Information Monitoring provides a kind of data acquisition storage device that walks abreast, thereby guarantees effective storage of data.
Another object of the present invention provides the parallel storage method of a kind of data acquisition.
Primary and foremost purpose of the present invention realizes through following technical proposals: notebook data is gathered parallel memory device, comprises the clock generating module, data buffering module and the data memory module that are connected; Said data buffering module comprises first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer that has with the out of phase write clock signal of frequency; First first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer respectively with the clock generating module, first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer also are connected with data memory module respectively; Said data memory module is used for 4 circuit-switched data signals of data buffering module are spliced into one road signal by the order of sampled signal.
Said data memory module adopts on-chip memory storage RAM.
Another object of the present invention realizes through following technical proposals: based on the parallel storage means of the data acquisition of above-mentioned data acquisition parallel memory device, comprise the steps:
S1, sample carry out ionization through ion source, form charged ion;
S2, charged ion are introduced electrode through pulse, obtain kinetic energy;
S3, the ion that in step S2, obtains kinetic energy get into electrostatic lens and obtain focusing on;
S4, the ion in step S3 after the focusing continue to get into postpones electrode acquisition acceleration and reflexes to ion detector;
S5, ion detector output signal to data acquisition system after ion is doubled;
S6, analog signal form differential signal through the simulated modulation circuit, and differential signal becomes digital signal through the ADC sampling A by analog signal conversion, through the parallel storage device stores of data acquisition, handle the back through data processing circuit and are read by computer;
Specifically may further comprise the steps among the step S6:
S61, analog signal conditioner circuit carry out impedance matching to the transmission line of input, and the amplitude of adjustment analog signal makes it to meet the full amplitude range of ADC sampling A, and converts single-ended signal to differential signal;
S62, differential signal get into the ADC sampling A, become digital signal by analog signal conversion;
S63, digital signal get into the data acquisition parallel memory device, and the data acquisition parallel memory device is realized the buffer memory and intersection output to the data flow of ADC sampling A output;
S64, read and carried out the analysis on time domain and the frequency domain through data in buffer stream;
S65, last being read by computer are again passed through the data of analyzing, and are carried out Filtering Processing.
Action principle of the present invention is: data acquisition system makes full use of the advantage of FPGA at parallel processing and sequential logic design aspect, utilizes the ping-pong operation mode to reach the effect with low-speed module processing high-speed data stream.Data acquisition module comprises data buffering and storage two parts, and the present invention has following advantage and effect with respect to prior art:
(1) effectively improved the analog input bandwidth, brought up to 300M, increased the time-of-flight mass spectrometer measuring range by 10M.
(2) improved the sampling precision of time-of-flight mass spectrometer in a big way.
(3) owing to strengthened the memory property of data acquisition system, the sensitivity of time-of-flight mass spectrometer has had raising by a relatively large margin.
(4) high-speed data effectively being reduced to low speed data can be received and the quick real-time processing by rear end MCU (FPGA), effectively raises the accuracy of time-of-flight mass spectrometer test sample.
Description of drawings
Fig. 1 is an electrical block diagram of the present invention;
Fig. 2 is a data time sequence emulation sketch map.
Embodiment
Below in conjunction with embodiment and accompanying drawing the present invention is described in further detail, but execution mode of the present invention is not limited thereto.
Embodiment
Time-of-flight mass spectrometer comprises that ion source, ion are drawn pulsed electrode, ion extraction lens, vertically introduction-type flying time mass spectrum analysis device, ion are selected repulsion electrode, MCP (Microchannel Plate) ion detector.Sample gets into high-speed data acquistion system through separation signal behind the time-of-flight mass spectrometer, through the parallel storage device stores of the present invention, is read by computer through data processing at last.Said high-speed data acquistion system comprises front end simulated modulation circuit, ADC sample circuit, the present invention parallel storage device, data processing circuit and data reading circuit.Said ion is drawn pulsed electrode, and the ion that ion source is produced obtains kinetic energy down at this to the electrode effect, and this has determined that to electrode institute making alive amplitude the kinetic energy of ion is big or small; Said ion is drawn pulsed electrode can be different to different ion source forms.Said vertical introduction-type flying time mass spectrum analysis device can be conventional vertical introduction-type flying time mass spectrum analysis device; Ion selects repulsion electrode and MCP ion detector to be arranged at wherein.Said MCP ion detector is the ion detector that conventional biplate MCP forms.
Fig. 1 shows circuit structure of the present invention.Visible by Fig. 1, the present invention includes the clock generating module, data buffering module and the data memory module that are connected.
Bit wide is that 8 first to fourth first in first out (FIFO) buffer is formed the data buffering module, and they have with the out of phase write clock signal of frequency.First to fourth first-in first-out buffer is connected with clock generating module, data memory module respectively.The effect of data buffering module is that high-speed data signal is divided into 4 road low speed datas, and writes in 4 fifo buffers.At first make up 4 first-in first-out buffer FIFO1-FIFO4, the output signal of data acquisition module is stored into respectively in 4 first-in first-out buffers.Two data buffering areas that wherein PortA is corresponding are respectively the first first-in first-out buffer FIFO1 and the 3rd first-in first-out buffer FIFO3, and two data buffering areas that PortB is corresponding are respectively the second first-in first-out buffer FIFO2 and the 4th first-in first-out buffer FIFO4.
Data memory module adopts on-chip memory storage RAM, and its effect is 4 tunnel 8 bit data signals with the front end data buffer module, is spliced into one tunnel 32 signal by the order of sampled signal, and keeps its correct order.
A concrete instance of using is following: during for example according to concrete the realization, have the ADC sampling A of 8bit conversion accuracy, the sample rate of single passage can reach 1Gsps.Through after the digital-to-analogue conversion, single channel output 1G data flow.Store data after data acquisition starts among four first-in first-out buffer FIFO1-FIFO4 of data buffering module and be respectively N, N+1, N+2, N+3 ...After time-sequence control module defined each startup, data all were to deposit since the first first-in first-out buffer FIFO1, to satisfy the requirement that order reads.Bit to data carries out layout again at last, obtains the parallel data of arranging by sampling order.
After data memory module starts; Rising edge at the read-write clock signal FIFO-Rdclk of each first-in first-out buffer; From four first-in first-out buffer FIFO1-FIFO4, read 4 tunnel 8 bit data simultaneously; And 4 tunnel 8 bit data that read are spliced into one tunnel 32 bit data, deposit in the doubleclocking two-port RAM of 32 bit wides.The clock FIFO-Rclk that writes that writes clock RAM-Wrclk and first-in first-out buffer of RAM is a homogenous frequency signal.Owing to have delay (tco) between the read-write clock of first-in first-out buffer and the output; So in design, adopted the read-write clock FIFO-Rdclk phase place of the first-in first-out buffer mode of writing clock RAM-Wrclk of certain clock signals that squint backward as RAM; To avoid the risk (used FIFO1 shown in Figure 2 to make FIFO-Rdclk in the design, FIFO2 is as RAM-WrcIk) of competing.When the storage data, RAM adopts little end structure.When whenever writing the data of a word length (4 bytes), only need the output of FIFO1-4 is linked respectively first to the 4th byte of RAM.As shown in Figure 1, FIFO1 stores the least-significant byte of a word into, and FIFO4 has then stored the most-significant byte of same word into, makes the order of data among the RAM identical with the data order of gathering.The storage control module adopts interrupt mode to carry out data flow con-trol; The data of in fifo buffer, storing reach a threshold value, and (this threshold value can be set; The native system threshold value is 32 bytes, and the capacity of FIFO is 64 bytes) time, control module is from the buffering area sense data and store into the RAM.(native system RAM capacity is the 4K byte when the data volume among the data storage RAM reaches a threshold value.Threshold value is set to 4K, also can be set to other value less than the RAM capacity), control module is sent the data processing interrupt requests to CPU, and CPU directly visits RAM through bus.
When FIFO-Rdclk=CLK/4 (CLK is a sampling clock) in theory, the storage speed of signal equate that with picking rate this moment, fifo buffer institute data quantity stored was constant.If can cause buffering area to overflow during FIFO-Rdclk＜CLK/4, on the contrary then can cause during FIFO-RdcIk＞CLK/4 buffering area frequent send aerial disconnected, so system design FIFO-Rdclk=CLK/4 in season.Simultaneously for the ease of observing low-frequency data, design has also realized the programmable sample frequency, and the value of the clock generating module register through software setting FPGA can be carried out the write clock signal of FIFO 2n frequency division (0＜n＜8), thereby realized the 2n frequency division of data sampling.Shown in Figure 2 is 8 frequency divisions and the clock signal frequency division the time not, and its principle is through reducing the clock frequency of writing of FIFO, arrive the frequency that reduces storage, thereby realizes changing the function of sample frequency.Wherein clkin is the data output clock of data acquisition chip, and coutA1, coutB1, coutA2, coutB2, represents the data input clock of FIFO1-FIFO4 respectively, and clkA and clkB are intermediate variable.
Utilize the parallel storage device of the present invention to the method that data store, comprise the steps:
S1, sample carry out ionization through ion source, form charged ion.
S2, charged ion are introduced electrode through pulse, obtain kinetic energy.
S3, the ion that in step S2, obtains kinetic energy get into electrostatic lens and obtain focusing on.
S4, the ion in step S3 after the focusing continue to get into postpones electrode acquisition acceleration and reflexes to ion detector.
S5, ion detector output signal to high-speed data acquistion system after ion is doubled.
S6, analog signal form differential signal through the simulated modulation circuit; Differential signal becomes digital signal through the ADC sampling A by analog signal conversion; Through string of the present invention and change storage device stores, handle the back through data processing circuit and reads by computer through USB or PCI.
Specifically may further comprise the steps among the step S6:
The effect of S61, analog signal conditioner circuit comprises that the transmission line to input carries out impedance matching, and the amplitude of adjustment analog signal makes it to meet the full amplitude range of ADC sampling A, and converts single-ended signal to differential signal.The conditioning of analog signal generally selects preamplifier or transformer to realize.
S62, differential signal get into the ADC sampling A, become digital signal by analog signal conversion.The ADC sampling A has the conversion accuracy of 8bit, and the sample rate of single passage can reach 1Gsps.Parallel sampling can equivalent reach the sample frequency of 2Gsps under alternate mode.
S63, digital signal get into the data acquisition parallel memory device, and the data acquisition parallel memory device is realized on FPGA.It can realize the buffer memory of the high-speed data-flow of ADC sampling A output is exported with intersecting reliably.
S64, can read and carry out rapid data and handle by other a slice FPGA through data in buffer.The data that FPGA reads in storage need not to carry out data recombination, directly this array are carried out the analysis on time domain and the frequency domain.
S65, last being read by computer are again passed through the data of analyzing, and are carried out Filtering Processing.
The foregoing description is a preferred implementation of the present invention; But execution mode of the present invention is not restricted to the described embodiments; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (3)
1. a data acquisition parallel memory device is characterized in that, comprises the clock generating module, data buffering module and the data memory module that are connected; Said data buffering module comprises first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer that has with the out of phase write clock signal of frequency; First first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer respectively with the clock generating module, first first-in first-out buffer, second first-in first-out buffer, the 3rd first-in first-out buffer and the 4th first-in first-out buffer also are connected with data memory module respectively; Said data memory module is used for 4 circuit-switched data signals of data buffering module are spliced into one road signal by the order of sampled signal.
2. data acquisition parallel memory device according to claim 1 is characterized in that, said data memory module adopts on-chip memory storage RAM.
3. based on the parallel storage means of the data acquisition of the said data acquisition parallel memory device of claim 1, it is characterized in that, comprise the steps:
S1, sample carry out ionization through ion source, form charged ion;
S2, charged ion are introduced electrode through pulse, obtain kinetic energy;
S3, the ion that in step S2, obtains kinetic energy get into electrostatic lens and obtain focusing on;
S4, the ion in step S3 after the focusing continue to get into postpones electrode acquisition acceleration and reflexes to ion detector;
S5, ion detector output signal to data acquisition system after ion is doubled;
S6, analog signal form differential signal through the simulated modulation circuit, and differential signal becomes digital signal through the ADC sampling A by analog signal conversion, store through the data acquisition parallel memory device, handle the back through data processing circuit and are read by computer;
Specifically may further comprise the steps among the step S6:
S61, analog signal conditioner circuit carry out impedance matching to the transmission line of input, and the amplitude of adjustment analog signal makes it to meet the full amplitude range of ADC sampling A, and converts single-ended signal to differential signal;
S62, differential signal get into the ADC sampling A, become digital signal by analog signal conversion;
S63, digital signal get into the data acquisition parallel memory device, and the data acquisition parallel memory device is realized the buffer memory and intersection output to the data flow of ADC sampling A output;
S64, read and carried out the analysis on time domain and the frequency domain through data in buffer stream;
S65, last being read by computer are again passed through the data of analyzing, and are carried out Filtering Processing.
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| CN103699702A (en) * | 2013-12-25 | 2014-04-02 | 北京航天测控技术有限公司 | Ultrahigh-speed data collecting and processing method and ultrahigh-speed data collecting and processing device |
| CN105843133A (en) * | 2016-05-27 | 2016-08-10 | 安图实验仪器(郑州)有限公司 | Matrix-assisted laser desorption/ionization time-of-flight mass spectrometer XY platform control system |
| CN105895495A (en) * | 2016-06-15 | 2016-08-24 | 安图实验仪器(郑州)有限公司 | Ion detection system applicable to laser desorption ionization time-of-flight mass spectrometer |
| CN111220846A (en) * | 2020-03-10 | 2020-06-02 | 星汉时空科技(北京)有限公司 | High-speed sampling full-digitalization frequency stability testing equipment and method |
| CN111797117A (en) * | 2020-07-02 | 2020-10-20 | 北京润科通用技术有限公司 | Data processing method and device |
| CN112069768A (en) * | 2020-09-08 | 2020-12-11 | 天津飞腾信息技术有限公司 | Method for optimizing input and output delay of dual-port SRAM (static random Access memory) |
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Cited By (7)
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| CN103699702A (en) * | 2013-12-25 | 2014-04-02 | 北京航天测控技术有限公司 | Ultrahigh-speed data collecting and processing method and ultrahigh-speed data collecting and processing device |
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| CN111220846A (en) * | 2020-03-10 | 2020-06-02 | 星汉时空科技(北京)有限公司 | High-speed sampling full-digitalization frequency stability testing equipment and method |
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| CN111797117A (en) * | 2020-07-02 | 2020-10-20 | 北京润科通用技术有限公司 | Data processing method and device |
| CN112069768A (en) * | 2020-09-08 | 2020-12-11 | 天津飞腾信息技术有限公司 | Method for optimizing input and output delay of dual-port SRAM (static random Access memory) |
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Application publication date: 20120801 |