CN102298143A - Multifunctional radar data acquisition card - Google Patents
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Abstract
The invention provides a multifunctional radar data acquisition card comprising a radar signal interface, a radar signal conditioning module, an analog to digital conversion module, a card storage, a global clock module, a high-speed communication interface and a digital control logic module, wherein the radar signal interface is used for outputting a signal received from outside to the radar signal conditioning module; a radar analog echo signal is subjected to the analog to digital conversion so as to form radar echo data, and the radar echo data is input to the digital control logic module; and the digital control logic module is used for respectively selecting the radar echo data with display, detection, enrolling and identification usages according to different requirements, and is in charge of transmitting the radar echo data with the display, detection, enrolling and identification usages to an external application system through the high-speed communication interface. By utilizing the multifunctional radar data acquisition card provided by the invention, digitization, intellectualization, integration and microminiaturization on a surface surveillance radar rear-end signal and a data processing system can be realized.
Description
Technical field
The present invention relates to signals collecting and data handling system in the radar system, especially handle relevant with data presentation, detection, admission and the identification of Radar Display and Control Terminal.
Background technology
Along with the develop rapidly of technology such as military affairs, Aeronautics and Astronautics, design has proposed modularization, digitizing, multi-functional and microminiaturized requirement to radar system.Have only each module of radar system to realize Highgrade integration, could be in limited volume and weight scope, for radar system provides more rich functions.Also have only after the echoed signal digitizing that radar front end is received, could adopt the multi-functional characteristic of various advanced persons' Digital Signal Processing realization radar system, therefore integrated design and digitized processing are the basic premise and the inevitable requirements of modern radar system development.
Radar data acquisition is converted to digital echo signal with regard to being to use analog/digital converter with the analog echo signal that the radar system front end receives, and sends to back end signal and data handling system offers processing procedures such as demonstration, detection, admission and identification.Modern radar system comprises maritime patrol is looked radar, all is to adopt the digital processing mode, Targets Dots demonstration, target range demonstration, objective contour is shown be integrated on the display, has realized integrated design.Target detection/tracking and echo data record then are to adopt distributed design, and using independently, the data acquisition and processing (DAP) passage carries out mould/transformation of variables and digital processing to the radar return data.Need so at least that three road moulds/the transformation of variables passage is respectively demonstration, detection and admission provides the radar return data.The benefit of this distributed design pattern is the independence that has strengthened demonstration, detection and admission module, make each module to work alone, do not disturb mutually, it is big that but its shortcoming is a volume, resource repeats, and is unfavorable for that radar system uses carrying a car, aircraft, naval vessel, space platform etc. volume and weight is had on the platform of strict demand.
Along with the development of maritime patrol being looked Technology of Radar Target Identification, progressively solved the problems such as feature extraction, Classification and Identification and template training of marine Ship Target, to maritime patrol look the radar target recognition system begun maritime patrol is looked in the radar system on probation.This make to maritime patrol look radar system many again one road target identification data collection and treatment channel, both increased the volume and weight of radar system, cause the resource height to repeat again.
In fact, the data source of maritime patrol being looked purposes such as demonstration, detection, admission and the identification use of radar system all is digitized radar return, and just the sampling rate and the range gate of echo data are different.Along with VLSI (very large scale integrated circuit) and development of computer can be used a circuit-switched data acquisition channel fully, the Radar Analog Echo signal transformation that to look radar system to maritime patrol is radar data earlier, handle through digital sampling and delay again, the echo data of different sampling rates and different distance ripple door is sent to processing modules such as demonstration, detection, admission and identification respectively, reach digitizing, integrated, microminiaturized purpose of design.
Present disclosed technical documentation does not relate to the content of this respect as yet.
Summary of the invention
The technical problem to be solved in the present invention is to make full use of VLSI (very large scale integrated circuit) and computer technology, design multifunction radar data collecting card, use the individual data acquisition channel to provide the radar return data of different sampling rates and different distance ripple door for processing such as demonstration, detection, admission and identification of maritime patrol being looked radar, digitizing, intellectuality, the integrated and miniaturized design of radar back end signal and data handling system looked in realization to maritime patrol.
Technical scheme of the present invention has following characteristics:
(1) independently radar return data acquisition channel is used in active service demonstration, detection and admission that maritime patrol is looked radar back end signal and data handling system usually, and does not have the high-fidelity echo data acquisition capacity that Target Recognition needs.And the radar return data acquisition function that the present invention will show, detects, enrolls and discern integrates, and uses the individual data acquisition channel to finish all radar return data acquisition functions.
(2) the present invention is with " the hard sampling " and FPGA (Field Programmable GateArray of analogue-digital converter, field programmable gate array) " the soft sampling " of chip numeral control logic module combine, analogue-digital converter carries out digital sample with flank speed to the guinea pig echoed signal, in fpga chip according to show, detect, the different requirements of admission and identification, the radar return data are sampled as required, obtain the radar return data of different sampling rates and different distance ripple door.
(3) the Target Recognition function that maritime patrol is looked radar system back end signal and data handling system has specific (special) requirements to the radar return data, require target echo and ground unrest that tangible amplitude contrast is arranged, and the radar return data truncation can not occur and cut end phenomenon, and promptly radar target must be in the sub-saturated state.The present invention has designed programme-controlled gain control circuit and program control bias control circuit, is used for radar target is adjusted to the sub-saturated state, satisfies the needs of Target Recognition function.
(4) the admission function that maritime patrol is looked radar system back end signal and data handling system has specific (special) requirements to the radar return data, and requirement can be write down the unusual sea condition that process on duty takes place and the high-fidelity echo of special objective rapidly and accurately.The present invention has designed the acquisition controlling logic of " What You See Is What You Get ", is used for radar watch person's high-fidelity echo of observed unusual sea condition and special objective on the display of back end signal and data handling system is noted rapidly and accurately.
Multifunction radar data collecting card of the present invention comprises storer, global clock module, high-speed communication interface and digital control logic module on radar signal interface, radar signal conditioning module, mould/transformation of variables module, the card.The radar signal interface is from outside receiving radar analog echo signal, radar antenna signal and radar synchronizing signal, and above-mentioned three kinds of signals are exported to enters the radar signal conditioning module.The Radar Analog Echo signal enters the radar signal conditioning module after send into mould/transformation of variables module after buffering amplification, programme-controlled gain control and the program control biasing control and treatment, after analog-digital conversion, form radar return data, radar return data input digit control logic module; The digital control logic module is provided with the radar return data of picking out demonstration, detection, admission and identification purposes respectively according to different sampling rate settings and different range gates, keeps in card and goes up in the storer; The digital control logic module receives the reading of data order that sends over from high-speed communication interface, with show, detect, the radar return data of admission and identification purposes send to outer application system from high-speed communication interface respectively.The radar antenna signal is multistation digital signal (figure place is determined by concrete application), enter the radar signal conditioning module from the radar signal interface, after digital isolation processing, send into the digital control logic module, the digital control logic module is carried out sampling of data to the radar antenna signal, obtain the antenna bearingt data, be temporarily stored in card and go up in the storer; The antenna bearingt data send to outer application system with the radar return data of demonstration, detection, admission or identification purposes from high-speed communication interface.The radar synchronizing signal, also be the radar trigger pulse, enter the radar signal conditioning module from the radar signal interface, after digital isolation processing, send into the digital control logic module, the digital control logic module serves as to handle beat to carry out different sampling rate settings and different range gate settings with the radar synchronizing signal, and the sampling rate setting is determined by concrete application with different range gate settings.
The radar signal interface comprises the physical interface of Radar Analog Echo signal, radar antenna signal and radar synchronizing signal, satisfy the mechanical electric characteristic requirement of Radar Analog Echo signal, radar antenna signal and radar synchronizing signal respectively, be responsible for these signal incoming radar signal conditioning module.
The radar signal conditioning module is divided into radar antenna signal condition, the conditioning of radar synchronizing signal and three submodules of analog echo signal conditioning.Radar antenna signal condition submodule is made up of the not circuit of two-stage series connection.Radar synchronizing signal conditioning submodule is made up of the not circuit of two-stage series connection.Use the two-stage not circuit that signal is carried out digital isolation processing, send into the digital control logic module then.Analog echo signal conditioning submodule is responsible for the Radar Analog Echo signal is cushioned amplification, programme-controlled gain control and program control biasing control and treatment, the dynamic range and the DC biased level of Radar Analog Echo signal are fallen within the normal range of operation of mould/transformation of variables module, send into mould/transformation of variables module then.
Analog echo signal conditioning submodule is divided into buffering amplification, programme-controlled gain control and three grades of circuit of program control biasing control.The operational amplifier of buffer amplifier circuit applying unit gain realizes, be responsible for the Radar Analog Echo signal with external system is kept apart, make the signalling channel characteristic of the unlikely influence of access of multifunction radar data collecting card to external system itself.The programme-controlled gain control circuit comprises gain-programmed amplifier, D/A converter and operational amplifier, the programme-controlled gain control command of digital control logic module output is converted to the gain control simulating signal through D/A converter, after the gain control simulating signal is amplified filtration through operational amplifier, output to gain-programmed amplifier, gain-programmed amplifier carries out processing and amplifying to the Radar Analog Echo signal and exports to program control bias control circuit.Program control bias control circuit comprises totalizer, D/A converter and operational amplifier, the program control biasing control command of digital control logic module output is converted to biasing control simulating signal through D/A converter, after biasing control simulating signal is amplified filtration through operational amplifier, output to totalizer, to setover control simulating signal and the Radar Analog Echo signal after the programme-controlled gain control circuit is handled of totalizer stacks up, and exports mould/transformation of variables module to.
Storer is divided into two groups on the card, constitutes the ping-pong operation pattern, and when first group of storer was in the write access state, second group of storer then was in the read access state; When first group of storer was in the read access state, second group of storer then was in the write access state.So both avoid the read and write access conflict, also guaranteed the real-time storage of radar return data.
The global clock module comprises crystal oscillator and timer manager.Crystal oscillator produces the reference signal of fixed frequency and exports to timer manager, timer manager carries out frequency multiplication, frequency division and delay successively to reference signal to be handled, according to the sampling rate requirement of demonstration, detection, admission and identification purposes to the radar return data, use least common multiple counting method (Lease Common Multiple, LCM) form overall sampling clock, export to mould/transformation of variables module and digital control logic module.
If show, detect, the sampling rate of admission and identification purposes is respectively fm, fd, fs and fr, so ff=LCM (fm, fd, fs, fr), i.e. the frequency of the overall sampling clock of mould/transformation of variables module.Mould/transformation of variables module is that sampling rate is carried out analog-digital conversion to the Radar Analog Echo signal with overall sampling clock, obtains the radar return data, sends into the digital control logic module.
High-speed communication interface uses PCI (Peripheral Controller Interface) bus, is made up of the pci interface control chip.
The digital control logic module utilizes fpga chip to realize, comprises aerial signal sampling logic, programme-controlled gain steering logic, program control biasing steering logic, storage operation logic, integrated state machine sampling logic and pci interface communication logic.
Aerial signal sampling logic, programme-controlled gain steering logic, program control biasing steering logic and storage operation logic are formed by register.The pci interface communication logic comprises register and code translator, under the effect of global clock signal, receives control command from high-speed communication interface and is stored to register, exports respective logic after decoder for decoding to.Control command comprises that digital control logic module reset command, programme-controlled gain control command, program control biasing control command, acquisition parameter are provided with order, start acquisition, remove acquisition and reading of data order.The pci interface communication logic receives digital control logic module reset command from high-speed communication interface digital control logic module is carried out Global reset, and all registers and code translator that the digital control logic module is comprised are got back to original state.The pci interface communication logic receives acquisition parameter from high-speed communication interface order is set, export integrated state machine sampling logic to, acquisition parameter is provided with order and is used for being provided with demonstration in integrated state machine sampling logic, detect, the extraction controlled variable of admission and identification purposes, comprise display delay count (M_DN), show counting step (M_LN), show sampling rate (M_SN) parameter, detect and postpone to count (D_DN), detect counting step (D_LN), detect sampling rate (D_SN) parameter, admission postpones to count (S_DN), admission counting step (S_LN), admission sampling rate (S_SN) parameter, identification postpones to count (R_DN), identification counting step (R_LN), identification sampling rate (R_SN) parameter.The pci interface communication logic receives from high-speed communication interface and starts acquisition, exports integrated state machine sampling logic to, starts the radar return data pick-up process that acquisition is used for controlling in integrated state machine sampling logic.The pci interface communication logic receives from high-speed communication interface and removes acquisition, exports integrated state machine sampling logic to, removes " What You See Is What You Get " radar return data pick-up process that acquisition is used for controlling in integrated state machine sampling logic." What You See Is What You Get " is meant the radar controller when the radar return data of back end signal and observed unusual sea condition of data handling system or special objective, the ability that the multifunction radar data collecting card is accurately enrolled and discerned.The radar controller is when back end signal and data handling system are observed unusual sea condition or special objective, and the multifunction radar data collecting card can receive the removing acquisition, removes data cached in the storer, continues to carry out its workflow.The pci interface communication logic receives the reading of data order from high-speed communication interface, export integrated state machine sampling logic to, the reading of data order is used for the echo data of from SRAM reading displayed, detection, admission and identification purposes in integrated state machine sampling logic.
Integrated state machine sampling logic comprises some counters, register, code translator, comparer, under the effect of global clock signal, according to demonstration, detect, admission and identification purposes are to the sampling rate requirement of echo data, the delay of the relative radar synchronizing signal of use radar return data rising edge is counted and is represented the position, forward position of range gate, use radar return data relative distance ripple in front of the door the counting step on edge represent the width of range gate, calculate the position, forward position and the length of the range gate of every kind of purposes data respectively, according to demonstration, detect, the radar return data pick-up of admission and identification purposes at interval, overall sampled clock signal is carried out the interval counting, generate correct address, extract correct data, be cached to card and go up in the storer.
In integrated state machine sampling logic, show, detect, the radar return data pick-up of admission and identification purposes is respectively M_SN=ff/fm at interval, D_SN=ff/fd, S_SN=ff/fs, R_SN=ff/fr, show, detect, the position, forward position and the length of the range gate of the radar return data of admission and identification purposes are respectively M_DN, M_LN, D_DN, D_LN, S_DN, S_LN, R_DN, R_LN, promptly the rising edge position with the radar synchronizing signal is a starting point, postpone M_DN global clock after the cycle, every (M_SN-1) individual radar return data, store 1 radar return data as the data that show purposes, up to having stored M_LN the data that show purposes; Rising edge position with the radar synchronizing signal is a starting point, postpones D_DN global clock after the cycle, every (D_SN-1) individual radar return data, stores the data of 1 radar return data as detection applications, up to the data of having stored D_LN detection applications; Rising edge position with the radar synchronizing signal is a starting point, postpones S_DN global clock after the cycle, every (S_SN-1) individual radar return data, stores the data of 1 radar return data as the admission purposes, up to the data of having stored S_LN detection applications; Rising edge position with the radar synchronizing signal is a starting point, postpones R_DN global clock after the cycle, every (R_SN-1) individual radar return data, stores the data of 1 radar return data as the identification purposes, up to the data of having stored R_LN identification purposes.
In integrated state machine sampling logic, divide the radar return sampling of data course of work into 12 kinds of states, be respectively:
(1) starting state.This state representation digital control logic module powers up for the first time, receives that perhaps the pci interface communication logic sends over digital control logic module reset command, and the counter of inside, register, code translator are set to the process of original value.This state need experience a period of time, just can make inner counter, register, code translator enter stable virgin state.
(2) init state.This state representation receives the outside acquisition parameter that sends over order is set, this order comprises display delay count (M_DN), show counting step (M_LN), show sampling rate (M_SN) parameter, detect and postpone to count (D_DN), detect counting step (D_LN), detect sampling rate (D_SN) parameter, admission postpones to count (S_DN), admission counting step (S_LN), admission sampling rate (S_SN) parameter, identification postpones to count (R_DN), identification counting step (R_LN), identification sampling rate (R_SN) parameter, various registers are carried out initialization operation, and integrated state machine steering logic is carried out parameter and is prepared.
In integrated state machine sampling logic, the specific implementation of init state is: in init state, receive acquisition parameter from the outside order is set, carry out various parameters for the subsequent control state and prepare.The word length that the outside sends to the control command state parameter of integrated state machine sampling logic is (M+N) position, wherein low N position is an address bit, the type and the attribute of expression state of a control parameter, such as belonging to still identification control parameter of demonstration, detection, admission, belong to postpone to count, sample length still is the sampling rate parameter, high M position is only concrete state parameter.Outside (M+N) state of a control parameter that sends is buffered in the N bit register respectively and the M bit register, and N bit address code translator deciphers to N bit address data that to control M again be that the state of a control parameter specifically is latched in the corresponding parameters register.
(3) idle condition.This state representation initial work is finished, and can start working.Integrated state machine sampling logic whenever receives the primary radar synchronizing signal and finishes after controlling of sampling, all can enter this state and wait for the arrival of radar synchronizing signal next time.
(4-7) display delay, detection postpone, admission postpones, the identification delay.These 4 states are executed in parallel in integrated state machine sampling logic, be in the integrated state machine sampling logic of idle condition, receive earlier maritime patrol is looked radar back end signal and data handling system from the startup acquisition that high-speed communication interface sends over, wait for the radar synchronizing signal then.In case detect the rising edge of radar synchronizing signal, then enter this 4 parallel delaying states synchronously.In delaying state, 4 delay counters carry out delay counter to the global clock signal respectively, compare with respective delay point number register, when the delay counter result equals to postpone the value (M_DN, D_DN, S_DN and R_DN) of a number register, finish delaying state, enter sample mode.
In integrated state machine sampling logic, the specific implementation of delaying state is: integrated state machine sampling logic has 4 parallel delaying states, control the sample delay that shows, detects, enrolls and discern respectively and count, obtain corresponding position, range gate forward position.Integrated state machine sampling logic is provided with 4 M digit counters and simultaneously sampled clock signal is counted, count results output to respectively the display delay that is provided with in 4 M bit comparators and the init state count (M_DN), detect postpone to count (D_DN), enroll postpone to count (T_DN), discern delay count (R_DN) compare, if the count results of which counter equals corresponding delay point value, then the position, forward position of corresponding range gate has been found in expression, stop counting, enter corresponding sample mode.Because the position, range gate forward position of admission, demonstration, detection and Identification may be inconsistent, the concluding time of delay counter is also nonsynchronous, can not enter sample mode simultaneously, so integrated state machine sampling logic does not use single delaying state to carry out the conversion of state of a control.
(8-11) admission sampling, demonstration sampling, detection sampling, identification are sampled.These 4 states also are executed in parallel in integrated state machine sampling logic, but because show, detect, the delay of admission and identification is counted and is had nothing in common with each other, and is not to enter this 4 parallel sample modes synchronously therefore.In sample mode, show, detect, enroll and discern and use 2 counters to count respectively; First order counter carries out plus coujnt to sampling clock, and compare with the sampling rate register, when counting step equals the value (M_SN, D_SN, S_SN and R_SN) of sampling rate register, self-zero clearing, export 1 count pulse, make second level counter plus coujnt 1 time; If the count results of second level counter is less than the value (M_LN, D_LN, S_LN and R_LN) of counting step register, the 1st length counter is with regard to periodic duty, when the count results of second level counter equals the value (M_LN, D_LN, R_LN and R_LN) of counting step register, just finish sample mode, enter completion status.
In integrated state machine sampling logic, the specific implementation of sample mode is: integrated state machine sampling logic has 4 parallel sample modes, control the sample length that shows, detects, enrolls and discern respectively and count, obtain the echo data of corresponding length, generate correct memory address.Showing, detect, enroll and discerning is not to enter sample mode synchronously, and sampling is also inequality the finish time, but before trigger pulse arrives next time, all can finish sampling.Each sample mode has been used 2 grades of counters, comparer steering logic, first order comparer is counted sampled clock signal earlier, when count results equates with the numerical value of sampling rate register, a secondary data is extracted in expression from sampled data stream, the pulse of output single sample, first order counter O reset restarts counting.Second level counter is counted the sampling pulse of first order comparer output, when count results when numerical value in the sample length register equates, expression has obtained the data from the sample survey of corresponding length, makes first order counter and second level counter stop counting simultaneously, enters the sampling completion status.In sample mode, the count results of second level counter also is simultaneously the memory address of the data after the sampling.
(12) sampling is finished.Have only 4 sample modes when concurrent working (admission sampling, show sampling, detect sampling, identification sampling) when all finishing sample mode, represent just that integrated state machine is sampled to finish 1 sampling, the idle condition of returning in the logic.
The workflow of multifunction radar data collecting card is as follows:
1. the multifunction radar data collecting card is installed in maritime patrol is looked in the PCI slot of radar back end signal and data handling system, and Radar Analog Echo signal, radar antenna signal and the radar synchronizing signal of maritime patrol being looked radar are connected on the respective signal interface of multifunction radar data collecting card.
2. the multifunction radar data collecting card receives maritime patrol is looked the digital control logic module reset command that radar back end signal and data handling system send over from high-speed communication interface, the multifunction radar data collecting card is carried out Global reset, and integrated state machine sampling logic is in starting state; Maritime patrol is looked the radar back end signal to the reception of multifunction radar data collecting card and data handling system is provided with order from the acquisition parameter that high-speed communication interface sends over, the extraction controlled variable of demonstration, detection, admission and identification purposes in the integrated state machine sampling logic is set, and integrated state machine sampling logic is in init state.
3. the multifunction radar data collecting card receives maritime patrol is looked radar back end signal and data handling system from the programme-controlled gain control command that high-speed communication interface sends over, and the programme-controlled gain control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set; The multifunction radar data collecting card receives looks radar back end signal and data handling system from the program control biasing control command that high-speed communication interface sends over to maritime patrol, and the program control bias control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set.
4. the multifunction radar data collecting card receives maritime patrol is looked radar back end signal and data handling system from the startup acquisition that high-speed communication interface sends over, and controls the sample radar return data pick-up process of logic of integrated state machine.If integrated state machine sampling logic receives the removing acquisition, then judge it is to withdraw to gather or the next acquisition that starts of wait; If do not receive the removing acquisition, then wait for the radar synchronizing signal, integrated state machine sampling logic is in idle condition.If integrated state machine sampling logic receives the radar synchronizing signal, then be in display delay, detection delay, admission delay, identification delay.After delaying state finishes, enter the admission sampling, show sampling, detect sampling, the identification sampling, generate storage address, extract show, detect, the radar return data of admission and identification purposes, store card into upward in the storer.After sample mode finished, integrated state machine sampling logic was in idle condition, and the multifunction radar data collecting card is by finishing notice to high-speed communication interface to maritime patrol being looked radar back end signal and data handling system transmission data acquisition.
5. the multifunction radar data collecting card receives maritime patrol is looked the reading of data order that radar back end signal and data handling system send over from high-speed communication interface, the radar return data of control SRAM operation logic reading displayed, detection, admission and identification purposes from block storer send to maritime patrol by high-speed communication interface and look radar back end signal and data handling system.
6. 3.～5. multifunction radar data collecting card circulation is carried out, and maritime patrol is looked the radar return data that the radar back end signal is obtained demonstrations, detection continuously with data handling system, enrolled and discern purposes.
Adopt the present invention can reach following technique effect:
The multifunction radar data collecting card uses one road analogue-digital converter " hard sampling ", multidiameter delay " soft sampling " replaces original multichannel analogue-digital converter " hard sampling ", can effectively reduce the complicacy of radar back end signal and data handling system,, the occupation rate and the production cost of reduction hardware resource.Use integrated state machine steering logic to realize various conversion of operation state in multidiameter delay in the digital control logic module " soft sampling " process, can improve the stability of control timing, avoid the generation of metastable condition, steady operation when helping radar back end signal and data handling system long.Be in particular in:
(1) complicacy of minimizing radar back end signal and data handling system, the occupation rate and the production cost of reduction hardware resource.The data source that the radar back end signal shows, detects, enrolls with data handling system and the identification processing is used is the same, all is the Radar Analog Echo that the radar system front end receives.Classic method uses a plurality of independently acquisition channels that the data of different sampling rates are provided, and for showing, detect, enroll and discerning to handle and use, uses the multichannel analogue-digital converter respectively, and steering logic designs complexity.The present invention is reduced to one the tunnel with traditional multi-channel data acquisition, is aided with multidiameter delay " soft sampling ", and the acquisition channel number is reduced to original 1/X (X represents original port number), and the hardware resource that the digital control logic module takies is also than significantly reducing originally.
(2) integrated state machine steering logic can improve the stability of control timing.Integrated state machine steering logic is used the global clock signal, the course of work is divided into 12 kinds of states, state exchange has clear and definite definition, except a spot of interface signal, the all working signal all is limited in each local state, the signal that has reduced between the different conditions is mutual, has improved the stability of control timing.
The application that the multifunction radar data acquisition is stuck in the comprehensively apparent control system of radar shows that the present invention can effectively reduce the complicacy of radar back end signal and data handling system, reduces the occupation rate of hardware resource, improves the stability of control timing simultaneously.
Description of drawings
Fig. 1 is the composition frame chart of multifunction radar data collecting card;
Fig. 2 is the composition frame chart of analog echo signal conditioning submodule in the multifunction radar data collecting card radar signal conditioning module;
Fig. 3 is the composition frame chart of multifunction radar data collecting card digital control logic module;
Fig. 4 is the state transitions block diagram of the integrated state machine steering logic of multifunction radar data collecting card;
Fig. 5 is the principle of work block diagram of the init state of the integrated state machine steering logic of multifunction radar data collecting card;
Fig. 6 is the principle of work block diagram of the delaying state of the integrated state machine steering logic of multifunction radar data collecting card;
Fig. 7 is the principle of work block diagram of the sample mode of the integrated state machine steering logic of multifunction radar data collecting card;
Fig. 8 is the workflow diagram of multifunction radar data collecting card.
Embodiment
Fig. 1 is the composition frame chart of multifunction radar data collecting card, is made up of storer, global clock module, high-speed communication interface and digital control logic module on radar signal interface, radar signal conditioning module, mould/transformation of variables module, the card.Multifunction radar data acquisition calorie requirement comprises Radar Analog Echo signal, radar antenna signal and radar synchronizing signal from the signal of maritime patrol being looked radar system and being obtained.Demonstration, the radar return data that detect, enroll and discern purposes and antenna bearingt data are transferred to by high-speed communication interface looks radar back end signal and data handling system to maritime patrol, and the control command of multifunction radar data collecting card also sends by high-speed communication interface.
Fig. 2 is the composition frame chart of analog echo signal conditioning submodule in the multifunction radar data collecting card radar signal conditioning module, and analog echo signal conditioning submodule is divided into buffering amplification, programme-controlled gain control and three grades of circuit of program control biasing control.The operational amplifier of buffer amplifier circuit applying unit gain is realized.The programme-controlled gain control circuit uses gain-programmed amplifier, D/A converter and operational amplifier to realize, the programme-controlled gain control circuit carries out processing and amplifying according to the gain of maritime patrol being looked the setting of radar back end signal and data handling system to the Radar Analog Echo signal.Program control bias control circuit uses totalizer, D/A converter and operational amplifier to realize, program control bias control circuit carries out the direct current biasing adjustment according to the direct current biasing of maritime patrol being looked the setting of radar back end signal and data handling system to the Radar Analog Echo signal.
Fig. 3 is the composition frame chart of multifunction radar data collecting card digital control logic module, is divided into aerial signal sampling logic, programme-controlled gain steering logic, program control biasing steering logic, the sampling of integrated state machine logic, storage operation logic and pci interface communication logic.
Fig. 4 is the state transitions block diagram of the integrated state machine steering logic of multifunction radar data collecting card.The course of work of integrated state machine steering logic divides 12 kinds of states into: startup, initialization, free time, admission delay, display delay, detection postpone, identification postpones, admission is sampled, show sampling, detect sampling, discern sampling, sampling is finished, wherein enrolling delay, display delay, detection delay, discerning these 4 kinds of delaying states of delay is executed in parallel, constitute parallel delaying state, admission is sampled, shown sampling, detects sampling, discerns these 4 kinds of states of sampling also is executed in parallel, constitutes parallel sample mode.In the practical work process, mainly carry out state transitions between finishing in idle, walk abreast delay and line sampling and sampling.
Integrated state machine steering logic powers up for the first time, receives that perhaps the outside sends over (Reset) signal that resets, and just enters starting state, and this state is set to original value with the signal of integrated state machine steering logic inside, register sum counter etc.This state need experience a period of time, just can make resources such as inner signal, register sum counter enter stable virgin state.
Starting state finishes to change over to automatically init state, and integrated state machine steering logic receives the outside various parameters that send in init state, and inner various registers are set, and integrated state machine is carried out parameter and prepared.Init state finishes to change idle condition automatically over to, represents that integrated state machine steering logic can receive start pulse signal, has carried out sampling work.Integrated state machine steering logic whenever receives a start pulse signal (SYNC PULSE) and finishes after controlling of sampling, all can enter this state and wait for the arrival of start pulse signal (SYNC PULSE) next time.
Integrated state machine steering logic detects the rising edge of start pulse signal, just enters parallel delaying state, and admission delay, display delay, detection postpone, identification postpones to start working simultaneously.In delaying state, 4 delay counters carry out delay counter to sampling clock respectively, compare with respective delay point number register, when the delay counter result equals to postpone the value (T_DN, M_DN, D_DN and R_DN) of a number register, the position, forward position of respective distances ripple door has been found in expression, finish delaying state, enter sample mode.
Because the delay of admission, demonstration, detection and Identification is counted and had nothing in common with each other, therefore not to enter 4 parallel delaying states (admission is sampled, shown sampling, detects sampling, discerns sampling) synchronously.In sample mode, admission, demonstration, detection and Identification use 2 length counters to count respectively, generate correct memory address, sampling obtains correct demonstration echo data, when the count results of the 2nd length counter equals the value (T_LN, M_LN, D_LN and R_LN) of counting step register, just finish sampling, enter completion status.
When 4 sample modes of concurrent working all finish sample mode, represent that integrated state machine steering logic finishes 1 sampling, the idle condition of returning.
Fig. 5 is the principle of work block diagram of the init state of the integrated state machine steering logic of multifunction radar data collecting card.The word length that the outside sends to the state of a control parameter of integrated state machine steering logic is (M+N) position, wherein low N position is an address bit, the type and the attribute of expression state of a control parameter, such as belonging to admission, demonstration, detecting still identification control parameter, belong to postpone to count, sample length still is the sampling rate parameter, high M position is only concrete state parameter.Outside (M+N) state of a control parameter that sends is buffered in the N bit register respectively and the M bit register, controlling M after N bit address code translator is deciphered N bit address data again is that the state of a control parameter specifically is latched in the corresponding parameters register, mainly is that admission postpones to count (T_DN), admission counting step (T_LN), admission sampling rate (T_SN), display delay count (M_DN), show counting step (M_LN), show sampling rate (M_SN), detect and postpone to count (D_DN), detect counting step (D_LN), detect sampling rate (D_SN), identification postpones to count (R_DN), identification counting step (R_LN), identification sampling rate (R_SN) parameter.
Fig. 6 is the principle of work block diagram of the delaying state of the integrated state machine steering logic of multifunction radar data collecting card.Integrated state machine steering logic has 4 parallel delaying states, and the control mode of each delaying state all is identical, uses 1 register, 1 counter and 1 comparer to carry out work control respectively.The M position postpones to store in the some number register is to postpone to count parameter (admission postpones to count (T_DN), display delay is counted (M_DN), detects postpone to count (D_DN) and discern delay count (R_DN)), M position up counter carries out plus coujnt to sampled clock signal, the M bit comparator compares the value of plus coujnt result and register, if count results equals corresponding delay point value, then the position, forward position of corresponding range gate has been found in expression, produce delayed pulse signal END_D, control M position up counter stops counting, enters sample mode.
Fig. 7 is the principle of work block diagram of the sample mode of the integrated state machine steering logic of multifunction radar data collecting card.Integrated state machine steering logic has 4 parallel sample modes, and the control mode of each sample mode all is identical, uses 2 registers, 2 counters and 2 comparers to carry out work control respectively.What store in the sampling rate register of first order M position is sampling rate parameter (admission sampling rate (T_SN), show sampling rate (M_SN), detect sampling rate (D_SN), identification sampling rate (R_SN)), first order M position up counter carries out plus coujnt to sampled clock signal, first order M bit comparator compares the value of first order plus coujnt result and first order register, if count results equals corresponding sampling rate numerical value, then correct echo data position has been found in expression, produce sampling rate pulse signal END_S, control first order M position up counter zero clearing, cycle count, M position, second level up counter is counted the sampling rate pulse signal END_S of first order comparer output, when count results when numerical value in the sample length register of M position, the second level equates, expression has obtained the data from the sample survey of corresponding length, make first order M position up counter and M position, second level up counter stop counting simultaneously, enter the sampling completion status.In sample mode, the count results of second level counter also is simultaneously the memory address of the data after the sampling.
Fig. 8 is the workflow diagram of multifunction radar data collecting card, and idiographic flow is as follows:
1. the multifunction radar data collecting card is installed in maritime patrol is looked in the PCI slot of radar back end signal and data handling system, and Radar Analog Echo signal, radar antenna signal and the radar synchronizing signal of maritime patrol being looked radar are connected on the respective signal interface of multifunction radar data collecting card.
2. the multifunction radar data collecting card receives maritime patrol is looked the digital control logic module reset command that radar back end signal and data handling system send over from high-speed communication interface, the multifunction radar data collecting card is carried out Global reset,, integrated state machine sampling logic is in starting state; Maritime patrol is looked the radar back end signal to the reception of multifunction radar data collecting card and data handling system is provided with order from the acquisition parameter that high-speed communication interface sends over, the extraction controlled variable of demonstration, detection, admission and identification purposes in the integrated state machine sampling logic is set, and integrated state machine sampling logic is in init state.
3. the multifunction radar data collecting card receives maritime patrol is looked radar back end signal and data handling system from the programme-controlled gain control command that high-speed communication interface sends over, and the programme-controlled gain control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set; The multifunction radar data collecting card receives looks radar back end signal and data handling system from the program control biasing control command that high-speed communication interface sends over to maritime patrol, and the program control bias control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set.
4. the multifunction radar data collecting card receives maritime patrol is looked radar back end signal and data handling system from the startup acquisition that high-speed communication interface sends over, and controls the sample radar return data pick-up process of logic of integrated state machine.If integrated state machine sampling logic receives the removing acquisition, then judge it is to withdraw to gather or the next acquisition that starts of wait; If do not receive the removing acquisition, then wait for the radar synchronizing signal, integrated state machine sampling logic is in idle condition.If integrated state machine sampling logic receives the radar synchronizing signal, then be in display delay, detection delay, admission delay, identification delay.After delaying state finishes, enter the admission sampling, show sampling, detect sampling, the identification sampling, generate storage address, extract show, detect, the radar return data of admission and identification purposes, store card into upward in the storer.After sample mode finished, integrated state machine sampling logic was in idle condition, and the multifunction radar data collecting card is by finishing notice to high-speed communication interface to maritime patrol being looked radar back end signal and data handling system transmission data acquisition.
5. the multifunction radar data collecting card receives maritime patrol is looked the reading of data order that radar back end signal and data handling system send over from high-speed communication interface, the radar return data of control SRAM operation logic reading displayed, detection, admission and identification purposes from block storer send to maritime patrol by high-speed communication interface and look radar back end signal and data handling system.
6. 3.～5. multifunction radar data collecting card circulation is carried out, and maritime patrol is looked the radar return data that the radar back end signal is obtained demonstrations, detection continuously with data handling system, enrolled and discern purposes.
The present invention's successful Application comprehensively shows in the control system at the radar that maritime patrol is looked that the National University of Defense Technology develops voluntarily.This system uses a multifunction radar data collecting card, in the SPARTANXLFPGA of XILINX company chip, use integrated state machine steering logic to realize that single analogue-digital converter provides the ability of target echo data simultaneously as data recording, synthesis display, detection and Identification, simplified the structure of radar terminal, reduce the volume of radar terminal, strengthened the reliability of radar terminal.
Claims (1)
1. multifunction radar data collecting card, comprise storer, global clock module, high-speed communication interface and digital control logic module on radar signal interface, radar signal conditioning module, mould/transformation of variables module, the card, it is characterized in that, the radar signal interface is from outside receiving radar analog echo signal, radar antenna signal and radar synchronizing signal, and above-mentioned three kinds of signals are exported to enters the radar signal conditioning module; The Radar Analog Echo signal enters the radar signal conditioning module after send into mould/transformation of variables module after buffering amplification, programme-controlled gain control and the program control biasing control and treatment, after analog-digital conversion, form radar return data, radar return data input digit control logic module; The digital control logic module is provided with the radar return data of picking out demonstration, detection, admission and identification purposes respectively according to different sampling rate settings and different range gates, keeps in card and goes up in the storer; The digital control logic module receives the reading of data order that sends over from high-speed communication interface, with show, detect, the radar return data of admission and identification purposes send to outer application system from high-speed communication interface respectively; The radar antenna signal is a multistation digital signal, enter the radar signal conditioning module from the radar signal interface, send into the digital control logic module after digital isolation processing, the digital control logic module is carried out sampling of data to the radar antenna signal, obtain the antenna bearingt data, be temporarily stored in card and go up in the storer; The antenna bearingt data send to outer application system with the radar return data of demonstration, detection, admission or identification purposes from high-speed communication interface; The radar synchronizing signal, also be the radar trigger pulse, enter the radar signal conditioning module from the radar signal interface, send into the digital control logic module after digital isolation processing, the digital control logic module serves as to handle beat to carry out different sampling rate settings and different range gate settings with the radar synchronizing signal;
The radar signal interface comprises the physical interface of Radar Analog Echo signal, radar antenna signal and radar synchronizing signal, satisfy the mechanical electric characteristic requirement of Radar Analog Echo signal, radar antenna signal and radar synchronizing signal respectively, be responsible for these signal incoming radar signal conditioning module;
The radar signal conditioning module is divided into radar antenna signal condition, the conditioning of radar synchronizing signal and three submodules of analog echo signal conditioning; Radar antenna signal condition submodule is made up of the not circuit of two-stage series connection; Radar synchronizing signal conditioning submodule is made up of the not circuit of two-stage series connection; Use the two-stage not circuit that signal is carried out digital isolation processing, send into the digital control logic module then; Analog echo signal conditioning submodule is responsible for the Radar Analog Echo signal is cushioned amplification, programme-controlled gain control and program control biasing control and treatment, the dynamic range and the DC biased level of Radar Analog Echo signal are fallen within the normal range of operation of mould/transformation of variables module, send into mould/transformation of variables module then;
Analog echo signal conditioning submodule is divided into buffering amplification, programme-controlled gain control and three grades of circuit of program control biasing control; The operational amplifier of buffer amplifier circuit applying unit gain realizes, be responsible for the Radar Analog Echo signal with external system is kept apart, make the signalling channel characteristic of the unlikely influence of access of multifunction radar data collecting card to external system itself; The programme-controlled gain control circuit comprises gain-programmed amplifier, D/A converter and operational amplifier, the programme-controlled gain control command of digital control logic module output is converted to the gain control simulating signal through D/A converter, after the gain control simulating signal is amplified filtration through operational amplifier, output to gain-programmed amplifier, gain-programmed amplifier carries out processing and amplifying to the Radar Analog Echo signal and exports to program control bias control circuit; Program control bias control circuit comprises totalizer, D/A converter and operational amplifier, the program control biasing control command of digital control logic module output is converted to biasing control simulating signal through D/A converter, after biasing control simulating signal is amplified filtration through operational amplifier, output to totalizer, to setover control simulating signal and the Radar Analog Echo signal after the programme-controlled gain control circuit is handled of totalizer stacks up, and exports mould/transformation of variables module to;
Storer is divided into two groups on the card, constitutes the ping-pong operation pattern, and when first group of storer was in the write access state, second group of storer then was in the read access state; When first group of storer was in the read access state, second group of storer then was in the write access state;
The global clock module comprises crystal oscillator and timer manager; Crystal oscillator produces the reference signal of fixed frequency and exports to timer manager, timer manager carries out frequency multiplication, frequency division and delay successively to reference signal to be handled, according to the sampling rate requirement of demonstration, detection, admission and identification purposes to the radar return data, use least common multiple counting method (Lease Common Multiple, LCM) form overall sampling clock, export to mould/transformation of variables module and digital control logic module;
If show, detect, the sampling rate of admission and identification purposes is respectively fm, fd, fs and fr, so ff=LCM (fm, fd, fs, fr), i.e. the frequency of the overall sampling clock of mould/transformation of variables module; Mould/transformation of variables module is that sampling rate is carried out analog-digital conversion to the Radar Analog Echo signal with overall sampling clock, obtains the radar return data, sends into the digital control logic module;
High-speed communication interface uses PCI (Peripheral Component Interface, Peripheral Component Interconnect) bus mode, is made up of the pci interface control chip;
The digital control logic module is utilized FPGA (Field Programmable Gate Array, field programmable gate array) chip is realized, comprises aerial signal sampling logic, programme-controlled gain steering logic, program control biasing steering logic, storage operation logic, integrated state machine sampling logic and pci interface communication logic;
Aerial signal sampling logic, programme-controlled gain steering logic, program control biasing steering logic and storage operation logic are formed by register; The pci interface communication logic comprises register and code translator, under the effect of global clock signal, receives control command from high-speed communication interface and is stored to register, exports respective logic after decoder for decoding to; Control command comprises that digital control logic module reset command, programme-controlled gain control command, program control biasing control command, acquisition parameter are provided with order, start acquisition, remove acquisition and reading of data order; The pci interface communication logic receives digital control logic module reset command from high-speed communication interface digital control logic module is carried out Global reset, and all registers and code translator that the digital control logic module is comprised are got back to original state; The pci interface communication logic receives acquisition parameter from high-speed communication interface order is set, export integrated state machine sampling logic to, acquisition parameter is provided with order and is used for being provided with demonstration in integrated state machine sampling logic, detect, the extraction controlled variable of admission and identification purposes, comprise the display delay M_DN that counts, show counting step M_LN, show sampling rate parameter M_SN, detect and postpone to count D_DN, detect counting step D_LN, detect sampling rate parameter D_SN, admission postpones to count S_DN, admission counting step S_LN, admission sampling rate parameter S _ SN, identification postpones to count R_DN, identification counting step R_LN, identification sampling rate R_SN parameter; The pci interface communication logic receives from high-speed communication interface and starts acquisition, exports integrated state machine sampling logic to, starts the radar return data pick-up process that acquisition is used for controlling in integrated state machine sampling logic; The pci interface communication logic receives from high-speed communication interface and removes acquisition, export integrated state machine sampling logic to, remove acquisition is used for controlling What You See Is What You Get in integrated state machine sampling logic radar return data pick-up process, What You See Is What You Get is meant that the radar controller is when back end signal and data handling system are observed unusual sea condition or special objective, the multifunction radar data collecting card can receive the removing acquisition, remove data cached in the storer, continue to carry out its workflow; The pci interface communication logic receives the reading of data order from high-speed communication interface, export integrated state machine sampling logic to, the reading of data order is used for the echo data of from SRAM reading displayed, detection, admission and identification purposes in integrated state machine sampling logic;
Integrated state machine sampling logic comprises some counters, register, code translator, comparer, under the effect of global clock signal, according to demonstration, detect, admission and identification purposes are to the sampling rate requirement of echo data, the delay of the relative radar synchronizing signal of use radar return data rising edge is counted and is represented the position, forward position of range gate, use radar return data relative distance ripple in front of the door the counting step on edge represent the width of range gate, calculate the position, forward position and the length of the range gate of every kind of purposes data respectively, according to demonstration, detect, the radar return data pick-up of admission and identification purposes at interval, overall sampled clock signal is carried out the interval counting, generate correct address, extract correct data, be cached to card and go up in the storer;
In integrated state machine sampling logic, show, detect, the radar return data pick-up of admission and identification purposes is respectively M_SN=ff/fm at interval, D_SN=ff/fd, S_SN=ff/fs, R_SN=ff/fr, show, detect, the position, forward position and the length of the range gate of the radar return data of admission and identification purposes are respectively M_DN, M_LN, D_DN, D_LN, S_DN, S_LN, R_DN, R_LN, promptly the rising edge position with the radar synchronizing signal is a starting point, postpone M_DN global clock after the cycle, every M_SN-1 radar return data, store 1 radar return data as the data that show purposes, up to having stored M_LN the data that show purposes; Rising edge position with the radar synchronizing signal is a starting point, postpones D_DN global clock after the cycle, every D_SN-1 radar return data, stores the data of 1 radar return data as detection applications, up to the data of having stored D_LN detection applications; Rising edge position with the radar synchronizing signal is a starting point, postpones S_DN global clock after the cycle, every S_SN-1 radar return data, stores the data of 1 radar return data as the admission purposes, up to the data of having stored S_LN detection applications; Rising edge position with the radar synchronizing signal is a starting point, postpones R_DN global clock after the cycle, every R_SN-1 radar return data, stores the data of 1 radar return data as the identification purposes, up to the data of having stored R_LN identification purposes;
In integrated state machine sampling logic, divide the radar return sampling of data course of work into 12 kinds of states, be respectively:
First kind, starting state; This state representation digital control logic module powers up for the first time, receives that perhaps the pci interface communication logic sends over digital control logic module reset command, and the counter of inside, register, code translator are set to the process of original value;
Second kind, init state; This state representation receives the outside acquisition parameter that sends over order is set, this order comprise display delay count M_DN, show counting step M_LN, show sampling rate parameter M_SN, detect the D_DN that postpones to count, detect counting step D_LN, detect sampling rate parameter D_SN, enroll the S_DN that postpones to count, admission counting step S_LN, admission sampling rate parameter S _ SN, discern the R_DN that postpones to count, identification counting step R_LN, identification sampling rate R_SN parameter, various registers are carried out initialization operation, and integrated state machine steering logic is carried out parameter and is prepared;
In integrated state machine sampling logic, the specific implementation of init state is: in init state, receive acquisition parameter from the outside order is set, carry out various parameters for the subsequent control state and prepare; The word length that the outside sends to the control command state parameter of integrated state machine sampling logic is the M+N position, wherein low N position is an address bit, the type and the attribute of expression state of a control parameter, such as belonging to still identification control parameter of demonstration, detection, admission, belong to postpone to count, sample length still is the sampling rate parameter, high M position is only concrete state parameter; The outside M+N state of a control parameter that sends is buffered in the N bit register respectively and the M bit register, and N bit address code translator deciphers to N bit address data that to control M again be that the state of a control parameter specifically is latched in the corresponding parameters register;
The third, idle condition; This state representation initial work is finished; Integrated state machine sampling logic whenever receives the primary radar synchronizing signal and finishes after controlling of sampling, all can enter this state and wait for the arrival of radar synchronizing signal next time;
The 4th kind to the 7th kind, display delay, detection postpone, admission postpones, the identification delaying state; These 4 states are executed in parallel in integrated state machine sampling logic, be in the integrated state machine sampling logic of idle condition, receive earlier maritime patrol is looked radar back end signal and data handling system from the startup acquisition that high-speed communication interface sends over, wait for the radar synchronizing signal then; In case detect the rising edge of radar synchronizing signal, then enter this 4 parallel delaying states synchronously; In delaying state, 4 delay counters carry out delay counter to the global clock signal respectively, compare with respective delay point number register, when the delay counter result equals to postpone the value (M_DN, D_DN, S_DN and R_DN) of a number register, finish delaying state, enter sample mode;
In integrated state machine sampling logic, the specific implementation of delaying state is: integrated state machine sampling logic has 4 parallel delaying states, control the sample delay that shows, detects, enrolls and discern respectively and count, obtain corresponding position, range gate forward position; Integrated state machine sampling logic is provided with 4 M digit counters and simultaneously sampled clock signal is counted, count results output to respectively the display delay that is provided with in 4 M bit comparators and the init state count (M_DN), detect postpone to count (D_DN), enroll postpone to count (T_DN), discern delay count (R_DN) compare, if the count results of which counter equals corresponding delay point value, then the position, forward position of corresponding range gate has been found in expression, stop counting, enter corresponding sample mode; Because the position, range gate forward position of admission, demonstration, detection and Identification may be inconsistent, the concluding time of delay counter is also nonsynchronous, can not enter sample mode simultaneously, so integrated state machine sampling logic does not use single delaying state to carry out the conversion of state of a control;
The 8th kind to the 11 kind, admission sampling, demonstration sampling, detection sampling, identification sample mode; These 4 states also are executed in parallel in integrated state machine sampling logic, but because show, detect, the delay of admission and identification is counted and is had nothing in common with each other, and is not to enter this 4 parallel sample modes synchronously therefore; In sample mode, show, detect, enroll and discern and use 2 counters to count respectively; First order counter carries out plus coujnt to sampling clock, and compare with the sampling rate register, when counting step equals the value (M_SN, D_SN, S_SN and R_SN) of sampling rate register, self-zero clearing, export 1 count pulse, make second level counter plus coujnt 1 time; If the count results of second level counter is less than the value (M_LN, D_LN, S_LN and R_LN) of counting step register, the 1st length counter is with regard to periodic duty, when the count results of second level counter equals the value (M_LN, D_LN, R_LN and R_LN) of counting step register, just finish sample mode, enter completion status;
In integrated state machine sampling logic, the specific implementation of sample mode is: integrated state machine sampling logic has 4 parallel sample modes, control the sample length that shows, detects, enrolls and discern respectively and count, obtain the echo data of corresponding length, generate correct memory address; Showing, detect, enroll and discerning is not to enter sample mode synchronously, and sampling is also inequality the finish time, but before trigger pulse arrives next time, all can finish sampling; Each sample mode has been used 2 grades of counters, comparer steering logic, first order comparer is counted sampled clock signal earlier, when count results equates with the numerical value of sampling rate register, a secondary data is extracted in expression from sampled data stream, the pulse of output single sample, first order counter O reset restarts counting; Second level counter is counted the sampling pulse of first order comparer output, when count results when numerical value in the sample length register equates, expression has obtained the data from the sample survey of corresponding length, makes first order counter and second level counter stop counting simultaneously, enters the sampling completion status; In sample mode, the count results of second level counter also is simultaneously the memory address of the data after the sampling;
The 12 kind, the sampling completion status; Have only 4 sample modes when concurrent working (i.e. admission sampling, show sampling, detect sampling, identification sampling) when all finishing sample mode, represent just that integrated state machine is sampled to finish 1 sampling, the idle condition of returning in the logic;
The workflow of multifunction radar data collecting card is as follows:
The 1. step, the multifunction radar data collecting card is installed in to be looked in the PCI slot of radar back end signal and data handling system maritime patrol, and Radar Analog Echo signal, radar antenna signal and the radar synchronizing signal of maritime patrol being looked radar are connected on the respective signal interface of multifunction radar data collecting card;
The 2. step, the multifunction radar data collecting card receives looks the digital control logic module reset command that radar back end signal and data handling system send over from high-speed communication interface to maritime patrol, the multifunction radar data collecting card is carried out Global reset, and integrated state machine sampling logic is in starting state; Maritime patrol is looked the radar back end signal to the reception of multifunction radar data collecting card and data handling system is provided with order from the acquisition parameter that high-speed communication interface sends over, the extraction controlled variable of demonstration, detection, admission and identification purposes in the integrated state machine sampling logic is set, and integrated state machine sampling logic is in init state;
The 3. step, the multifunction radar data collecting card receives looks radar back end signal and data handling system from the programme-controlled gain control command that high-speed communication interface sends over to maritime patrol, and the programme-controlled gain control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set; The multifunction radar data collecting card receives looks radar back end signal and data handling system from the program control biasing control command that high-speed communication interface sends over to maritime patrol, and the program control bias control circuit that analog echo signal in the radar signal conditioning module is nursed one's health submodule is set;
In the 4. step, the multifunction radar data collecting card receives looks radar back end signal and the startup acquisition that data handling system sends over from high-speed communication interface to maritime patrol, controls the sample radar return data pick-up process of logic of integrated state machine; If integrated state machine sampling logic receives the removing acquisition, then judge it is to withdraw to gather or the next acquisition that starts of wait; If do not receive the removing acquisition, then wait for the radar synchronizing signal, integrated state machine sampling logic is in idle condition; If integrated state machine sampling logic receives the radar synchronizing signal, then be in display delay, detection delay, admission delay, identification delay; After delaying state finishes, enter the admission sampling, show sampling, detect sampling, the identification sampling, generate storage address, extract show, detect, the radar return data of admission and identification purposes, store card into upward in the storer; After sample mode finished, integrated state machine sampling logic was in idle condition, and the multifunction radar data collecting card is by finishing notice to high-speed communication interface to maritime patrol being looked radar back end signal and data handling system transmission data acquisition;
The 5. step, the multifunction radar data collecting card receives looks the reading of data order that radar back end signal and data handling system send over from high-speed communication interface to maritime patrol, the radar return data of control SRAM operation logic reading displayed, detection, admission and identification purposes from block storer send to maritime patrol by high-speed communication interface and look radar back end signal and data handling system;
In the 6. step, the circulation of multifunction radar data collecting card is carried out the and is 3. gone on foot to the 5. step, and maritime patrol is looked the radar return data that the radar back end signal is obtained demonstrations, detection continuously with data handling system, enrolled and discern purposes.
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