CN114201276A - FIFO interrupt management based method - Google Patents

FIFO interrupt management based method Download PDF

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Publication number
CN114201276A
CN114201276A CN202111410430.7A CN202111410430A CN114201276A CN 114201276 A CN114201276 A CN 114201276A CN 202111410430 A CN202111410430 A CN 202111410430A CN 114201276 A CN114201276 A CN 114201276A
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interrupt
fifo
priority
interrupt request
request
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王东
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Tianjin Jinhang Institute of Technical Physics
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Tianjin Jinhang Institute of Technical Physics
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/484—Precedence

Abstract

The application provides a method based on FIFO interrupt management, which comprises the following steps: acquiring interrupt requests sent from the interior or the exterior of a plurality of FPGAs, wherein the interrupt requests comprise priority information and port number information; determining an FIFO corresponding to the priority information and a synchronization module corresponding to the port number information; each interrupt request is configured with an independent synchronization module; each synchronization module of the FIFO with the same priority adopts the same interrupt synchronization clock; synchronizing the interrupt request by the interrupt synchronization clock; writing the interrupt request into a FIFO with corresponding priority; and reading the interrupt vector corresponding to the interrupt request stored in each FIFO according to the priority by an interrupt enabling module. The invention can realize the management function of multiple priorities and multiple interrupts inside or outside the FPGA, and overcomes the problems of interrupt loss and interrupt coverage of common integrated circuits.

Description

FIFO interrupt management based method
Technical Field
The present application relates to the field of interrupt management methods, and in particular, to a method for interrupt management based on FIFO.
Background
Interrupt technology is an important technology commonly used in integrated circuits, and mainly improves the real-time response requirement of the integrated circuits. In practical applications, the number of interrupt ports is often more than one, interrupt requests may come from the inside or outside of the integrated circuit, interrupt response priorities have different requirements, and synchronization relationships among interrupts and between interrupts and the integrated circuit are not clear, which puts high requirements on interrupt management inside the integrated circuit.
Special interrupt managers are designed in an existing Application Specific Integrated Circuit (ASIC), an advanced reduced instruction set processor (ARM) and a Digital Signal Processor (DSP), the number of interrupt processing ports is generally less than 32, the priority is generally less than 3, the number and the priority can be configured only within the range of the maximum value, and expansion cannot be performed. For the same interrupt port, if the current interrupt request waits for the response period, the ASIC, the ARM and the DSP generate one or more interrupt requests again, and the special interrupt manager only responds once and cannot store the generated interrupt request times. Interrupt loss and interrupt coverage are unacceptable for high accuracy systems. To this end, the present application proposes a method based on FIFO interrupt management.
Disclosure of Invention
The present application aims to address the above problems and provide a method based on FIFO interrupt management.
The application provides a method based on FIFO interrupt management, which comprises the following steps:
acquiring interrupt requests sent from the interior or the exterior of a plurality of FPGAs, wherein the interrupt requests comprise priority information and port number information;
determining an FIFO corresponding to the priority information and a synchronization module corresponding to the port number information; each interrupt request is configured with an independent synchronization module; each synchronization module of the FIFO with the same priority adopts the same interrupt synchronization clock;
synchronizing the interrupt request by the interrupt synchronization clock;
writing the interrupt request into a FIFO with corresponding priority;
and reading the interrupt vector corresponding to the interrupt request stored in each FIFO according to the priority by an interrupt enabling module.
According to the technical solutions provided by some embodiments of the present application, synchronizing the interrupt request by the interrupt synchronization clock specifically includes:
caching the interrupt request for two times;
collecting double edges of the interrupt request to determine the interrupt type of the interrupt request; the interrupt types comprise high level trigger interrupt, low level trigger interrupt, rising edge trigger interrupt and falling edge trigger interrupt;
and converting the interrupt request into a rising edge triggered interrupt type, wherein the high level of the interrupt request is changed into the low level after lasting for one interrupt synchronous clock width.
According to the technical solutions provided by some embodiments of the present application, writing the interrupt request into the FIFO with the corresponding priority specifically includes:
outputting an interrupt request signal with a high level and effective interrupt synchronous clock pulse width to a corresponding bit of the corresponding priority FIFO; the bit width of the write data and the read data of the FIFO with the same priority is the same and is equal to the number of the interrupt ports of the FIFO with the same priority.
According to the technical solution provided by some embodiments of the present application, each FIFO has a flag bit, and the flag bit is used for characterizing whether a valid interrupt request is stored in the corresponding FIFO.
According to the technical scheme provided by some embodiments of the present application, the method further comprises:
and when the bit-wise OR result of the interrupt request signals output by all the synchronization modules in the FIFO with the same priority is 1, setting the flag signal position of the corresponding FIFO to be a high level, otherwise, setting the flag signal position to be a low level.
According to the technical scheme provided by some embodiments of the present application, reading, by the interrupt enabling module, the interrupt vector corresponding to the interrupt request stored in each FIFO according to priority includes:
reading FIFO data with the current flag signal bit being high level and highest priority;
summing up each data bit in the read data to obtain the number of the effective interrupt requests in the current priority FIFO at the moment;
outputting the interrupt vector of each effective interrupt request to an interrupt response program according to the size of the port number represented by the port number information; the smaller the port number is, the higher the priority is;
and after receiving an interrupt response completion signal sent by the interrupt response program, setting the data position corresponding to the interrupt request to be 0.
According to some embodiments of the present invention, when all valid interrupt requests in the same priority FIFO complete an interrupt response, the flag signal of the FIFO is set to low.
Compared with the prior art, the beneficial effect of this application: the invention adopts an interrupt synchronous clock to synchronize internal or external interrupt requests, writes the synchronized interrupt requests into corresponding priority FIFOs, the FIFOs with different priorities have different flag signal bits, an interrupt enabling module firstly reads the highest priority FIFO data with the high level of the flag signal bits, outputs interrupt vectors in sequence when an interrupt response completion signal is high, and a CPU calls corresponding interrupt service programs according to the interrupt vectors; the FIFO interrupt management-based method can realize the interrupt management function in the FPGA and overcome the problems of interrupt loss and interrupt coverage of common integrated circuits.
Drawings
Fig. 1 is a schematic diagram of a FIFO interrupt management-based system applied to an FPGA according to an embodiment of the present disclosure.
Detailed Description
The following detailed description of the present application is given for the purpose of enabling those skilled in the art to better understand the technical solutions of the present application, and the description in this section is only exemplary and explanatory, and should not be taken as limiting the scope of the present application in any way.
As shown in fig. 1, the present embodiment provides a FIFO interrupt management-based system applied to an FPGA, which includes an interrupt enabling module, several FIFOs with different priorities, and several synchronizing modules.
Each FIFO is provided with a plurality of synchronizing modules, all the synchronizing modules corresponding to one FIFO adopt the same interrupt synchronous clock, and the synchronizing modules of FIFOs with different priorities can adopt the same or different interrupt synchronous clocks.
The number of the synchronization modules of each FIFO configuration is the same as the number of the interrupt requests which can be received by the FIFO, namely, each interrupt request is configured with an independent synchronization module.
The number of the priority levels set in the system is consistent with the number of the priority levels FIFO, the priority levels are set to be higher when the priority level numbers are smaller, the priority levels FIFO with the same priority level are not allowed to appear, and when an interrupt port of a certain priority level is insufficient, the problem can be solved by increasing the data bit width of the corresponding priority level FIFO.
The priority FIFOs adopt write-in and read-out independent clocks, the write-in clock is an interrupt synchronous clock of the synchronization module, and the read-out clock is a system clock of the interrupt enabling module. The bit width of the write-in data and the read-out data of the FIFO is the same and is equal to the number of the interrupt ports of the priority FIFO.
In fig. 1, the priority 1FIFO has four interrupt ports, which means that the priority FIFO can receive four interrupt requests of priority 1 level, and the four interrupt requests of priority 1 level correspond to four synchronization modules using the same interrupt synchronization clock, and the bit width of the write data and the read data of the priority 1FIFO is four. The priority NFIFO has six interrupt ports, which means that the priority FIFO can receive six priority N-level interrupt requests, and the six priority N-level interrupt requests correspond to six synchronization modules using the same interrupt synchronization clock, and the bit width of the write data and the read data of the priority NFIFO is six.
Each priority FIFO is provided with a flag signal bit, the flag signal bit is used for representing whether the corresponding priority FIFO stores effective interrupt requests or not, when the effective interrupt requests are stored, the flag signal bit is at a high level, otherwise, the flag signal bit is at a low level.
The interrupt enabling module is used for reading the interrupt vectors corresponding to the effective interrupt requests stored in the FIFO of each priority level in sequence from high to low according to the priority level, transmitting the interrupt vectors to the CPU interrupt response program, and sending corresponding completion signals to the interrupt enabling module when the CPU completes the interrupt response.
The present embodiment further provides a method for FIFO interrupt management, where the method is based on the above system for FPGA based on FIFO interrupt management, and the method includes the following steps:
s1, obtaining interrupt requests sent by the interior or exterior of the FPGAs, wherein the interrupt requests comprise priority information and port number information.
The priority information represents the priority of the FIFO to which the current interrupt request belongs, the port number information represents the number of the port numbers of the current interrupt request in the priority FIFO, and the port numbers generally start numbering from 1.
S2, determining a FIFO corresponding to the priority information and a synchronization module corresponding to the port number information; each interrupt request is configured with an independent synchronization module; and the synchronizing modules of the FIFO with the same priority adopt the same interrupt synchronizing clock.
S3, synchronizing the interrupt request through the interrupt synchronization clock.
Specifically, the synchronization module synchronizes each interrupt request by using an interrupt synchronization clock, and the interrupt request can be from the outside of the FPGA or from the inside of the FPGA; the synchronization module performs two-beat cache and two-edge acquisition on the interrupt request at the same time, wherein the two-beat cache is used for determining and converting types of different interrupt requests and uniformly converting the types of the different interrupt requests into a rising edge triggered interrupt type, and the receivable interrupt types of the interrupt request can be high-level triggered interrupt, low-level triggered interrupt, rising edge triggered interrupt and falling edge triggered interrupt.
And S4, writing the interrupt request into the FIFO with the corresponding priority.
Specifically, after the synchronization module synchronizes the interrupt request, it will output a high-level effective interrupt request signal of the interrupt synchronization clock pulse width to the corresponding bit of the corresponding priority FIFO; the bit width of the write data and the read data of the FIFO with the same priority is the same and is equal to the number of the interrupt ports of the FIFO with the same priority.
The write-in enable of each priority FIFO outputs the result of bit-wise OR of the interrupt request signals for all the synchronization modules, and the write-in data outputs the result of bit-wise splicing of the interrupt request signals output by all the synchronization modules.
Specifically, it is determined that when the bitwise or result of the interrupt request signals output by all the synchronization modules in the same priority FIFO is 1, it means that at least one valid interrupt request is stored in the priority FIFO, and therefore, the flag signal position of the corresponding priority FIFO is set to a high level, and conversely, when the bitwise or result of the interrupt request signals output by all the synchronization modules in the same priority FIFO is 0, it means that there is no valid interrupt request in the priority FIFO, it is set to a low level.
If a certain priority FIFO has four interrupt ports in total, and can receive interrupt request 1, interrupt request 2, interrupt request 3, and interrupt request 4 of that priority, respectively, and simultaneously receive interrupt request 1 and interrupt request 4 at the same time, the result of bit-wise splicing of the data written in the current priority FIFO, that is, the interrupt request signals output by all the synchronization modules, is: 1001.
and S5, reading the interrupt vector corresponding to the interrupt request stored in each FIFO according to the priority through the interrupt enabling module. The method specifically comprises the following steps:
reading FIFO data with the current flag signal bit being high level and highest priority;
summing up each data bit in the read data to obtain the number of the effective interrupt requests in the current priority FIFO at the moment;
outputting the interrupt vector of each effective interrupt request to an interrupt response program according to the size of the port number represented by the port number information; the smaller the port number is, the higher the priority is;
and after receiving an interrupt response completion signal sent by the interrupt response program, setting the data position corresponding to the interrupt request to be 0.
Specifically, the interrupt enabling module receives data of different priority FIFOs with high levels of current flag signal bits, when the last interrupt processing is finished, the highest priority FIFO data is read from all different priority FIFOs with high levels of current flag signal bits, and in the highest priority FIFO data, the sum of the bits of the data is the number of effective interrupt requests to be processed in the current priority FIFO; according to the principle that the smaller the port number is, the higher the priority level is, firstly outputting the interrupt vector of the interrupt request with the small port number to an interrupt response program, after the interrupt response program completes the interrupt response, returning a completion signal to an interrupt enabling module, at the moment, setting the data position corresponding to the interrupt request to be 0, repeating the steps, and when all the effective interrupt requests in the FIFO with the highest priority level complete the interrupt response, setting the flag signal position of the FIFO with the priority level to be low level, and completing the interrupt processing of the time.
After the interrupt processing is completed on the highest priority FIFO in the system, the highest priority FIFO data whose flag signal bit is high level is read for processing continuously in a similar manner, and specific steps are not described herein again.
Next, the above-mentioned FIFO interrupt management-based method is further explained by way of example:
the method comprises the steps that a certain system applied to FPGA and based on FIFO interrupt management is assumed to have two priority FIFOs which are marked as a first priority FIFO and a second priority FIFO, the number of the first priority FIFO is 1, the number of the second priority FIFO is 2, the first priority FIFO is provided with four interrupt ports which correspond to four synchronization modules, and the second priority FIFO is provided with six interrupt ports which correspond to six synchronization modules; interrupt synchronization clocks adopted by four synchronization modules corresponding to the first priority FIFO are 200MHz (clock period is 5ns), a write-in clock of the first priority FIFO is 200MHz, and the bit width of write-in and read-out data is 4; the interrupt synchronization clock adopted by the six synchronization modules corresponding to the second priority FIFO is 100MHz (clock period is 10ns), the write-in clock of the second priority FIFO is 100MHz, and the bit width of the write-in and read-out data is 6; the clock of the interrupt enabling module is 160MHz (clock period 6.25 ns); the reading clocks of the first priority FIFO and the second priority FIFO are respectively 160 MHz.
When the interrupt request 1 and the interrupt request 4 of the first priority FIFO simultaneously generate rising edges, namely, the interrupt request occurs, the corresponding synchronization module synchronizes the interrupt request 1 and the interrupt request 4 of the first priority by using a 200MHz clock, and outputs two high-level effective interrupt request signals with the width of 5ns to the 1 st bit and the 4 th bit of the written data of the first priority FIFO, meanwhile, the writing of the first priority FIFO enables the high level with the width of 5ns, and the mark signal position of the first priority FIFO is the high level.
When the interrupt response completion signal is high, namely when the last interrupt processing is completed, the interrupt enabling module reads out the data (4' b1001) stored in the first priority FIFO, adds and sums all bits of the data, judges that the number of the current effective interrupt requests is 2, and outputs the interrupt vector of the interrupt request 1 of the first priority FIFO to an interrupt response program according to the principle that the smaller the port number is, the higher the priority is, the lower the interrupt response completion signal becomes, when the interrupt response program completes the interrupt response, the higher the interrupt response completion signal becomes again, and the interrupt enabling module outputs the interrupt vector of the interrupt request 4 of the first priority FIFO again.
When the interrupt request 1 of the first priority FIFO occurs to the interrupt vector output thereof, the time consumption is as follows: (2+1) × 5+ (1+1) × 6.25 ═ 27.5 ns; the interrupt request 4 of the first priority FIFO takes time to occur to its interrupt vector output: (2+1) × 5+ (1+1) × 6.25+ interrupt request 1 interrupt response time, i.e. the sum of interrupt request 1 response time and interrupt request 1 processing time.
Therefore, the method based on FIFO interrupt management can save interrupt processing time and ensure the reliability and efficiency of the system.
According to the method based on the FIFO interrupt management, the interrupt management function in the FPGA is achieved through the FIFO, and the problems of interrupt loss and interrupt coverage of common integrated circuits are solved. The number of interrupt ports and the number of priorities of the interrupt management method can be flexibly increased or decreased, and all interrupt requests are all stored for response processing to be interrupted. The method can be applied to interrupt management of an infrared search and tracking high-accuracy system.
The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. The foregoing is only a preferred embodiment of the present application, and it should be noted that there are no specific structures which are objectively limitless due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes can be made without departing from the principle of the present invention, and the technical features mentioned above can be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention in other instances, which may or may not be practiced, are intended to be within the scope of the present application.

Claims (7)

1. A method for FIFO interrupt management, the method comprising the steps of:
acquiring interrupt requests sent from the interior or the exterior of a plurality of FPGAs, wherein the interrupt requests comprise priority information and port number information;
determining an FIFO corresponding to the priority information and a synchronization module corresponding to the port number information; each interrupt request is configured with an independent synchronization module; each synchronization module of the FIFO with the same priority adopts the same interrupt synchronization clock;
synchronizing the interrupt request by the interrupt synchronization clock;
writing the interrupt request into a FIFO with corresponding priority;
and reading the interrupt vector corresponding to the interrupt request stored in each FIFO according to the priority by an interrupt enabling module.
2. The FIFO interrupt management-based method of claim 1, wherein synchronizing the interrupt request via the interrupt-synchronous clock specifically comprises:
caching the interrupt request for two times;
collecting double edges of the interrupt request to determine the interrupt type of the interrupt request; the interrupt types comprise high level trigger interrupt, low level trigger interrupt, rising edge trigger interrupt and falling edge trigger interrupt;
and converting the interrupt request into a rising edge triggered interrupt type, wherein the high level of the interrupt request is changed into the low level after lasting for one interrupt synchronous clock width.
3. The FIFO interrupt management-based method of claim 1, wherein writing the interrupt request into a FIFO of corresponding priority comprises:
outputting an interrupt request signal with a high level and effective interrupt synchronous clock pulse width to a corresponding bit of the corresponding priority FIFO; the bit width of the write data and the read data of the FIFO with the same priority is the same and is equal to the number of the interrupt ports of the FIFO with the same priority.
4. The method according to claim 3, wherein each FIFO has a flag bit indicating whether a valid interrupt request is stored in the corresponding FIFO.
5. The FIFO interrupt management based method of claim 4, further comprising:
and when the bit-wise OR result of the interrupt request signals output by all the synchronization modules in the FIFO with the same priority is 1, setting the flag signal position of the corresponding FIFO to be a high level, otherwise, setting the flag signal position to be a low level.
6. The method according to claim 5, wherein reading the interrupt vector corresponding to the interrupt request stored in each FIFO by the interrupt enable module according to priority comprises:
reading FIFO data with the current flag signal bit being high level and highest priority;
summing up each data bit in the read data to obtain the number of the effective interrupt requests in the current priority FIFO at the moment;
outputting the interrupt vector of each effective interrupt request to an interrupt response program according to the size of the port number represented by the port number information; the smaller the port number is, the higher the priority is;
and after receiving an interrupt response completion signal sent by the interrupt response program, setting the data position corresponding to the interrupt request to be 0.
7. The method according to claim 6, wherein the flag signal position of the FIFO is low when all valid interrupt requests in the same priority FIFO complete an interrupt response.
CN202111410430.7A 2021-11-25 2021-11-25 FIFO interrupt management based method Pending CN114201276A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117472637A (en) * 2023-12-27 2024-01-30 苏州元脑智能科技有限公司 Interrupt management method, system, equipment and medium
CN117667466A (en) * 2024-02-01 2024-03-08 井芯微电子技术(天津)有限公司 Interrupt processing method and device, electronic equipment and storage medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117472637A (en) * 2023-12-27 2024-01-30 苏州元脑智能科技有限公司 Interrupt management method, system, equipment and medium
CN117472637B (en) * 2023-12-27 2024-02-23 苏州元脑智能科技有限公司 Interrupt management method, system, equipment and medium
CN117667466A (en) * 2024-02-01 2024-03-08 井芯微电子技术(天津)有限公司 Interrupt processing method and device, electronic equipment and storage medium

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