CN117667466A - Interrupt processing method and device, electronic equipment and storage medium - Google Patents
Interrupt processing method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention discloses an interrupt processing method, an interrupt processing device, electronic equipment and a storage medium, wherein the interrupt processing method comprises the following steps: determining a current port to be processed according to the port interrupt signal; acquiring all interrupt events of a current port to be processed, generating an interrupt event set, and determining the current interrupt event to be processed; acquiring event information corresponding to an interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of an interrupt event set; repeating the operation until the interrupt event set is empty. The interrupt processing method disclosed by the invention can make timely response when a plurality of ports simultaneously generate interrupts and a plurality of interrupt events simultaneously occur in the same port by determining the ports to be processed according to the interrupt signals and generating the interrupt event set, can ensure that all interrupt events are processed in sequence when a plurality of interrupt events occur in the same port, avoids the condition of bus congestion, and overcomes the defect that the multi-port and multi-event simultaneous interrupts cannot be processed in the prior art.
Description
Technical Field
The present invention relates to the field of PCIe bus communications technologies, and in particular, to an interrupt processing method, an interrupt processing device, an electronic device, and a storage medium.
Background
The high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe) has the characteristics of high bandwidth and strong anti-interference performance. In the PCIe architecture, a Root Complex (RC) receives an instruction from a CPU to generate a corresponding PCIe packet, or parses data after receiving the packet and transmits the parsed data to the CPU or the memory. The translator device is mainly used in PCIe network architecture to increase fan-out. Each partition of the PCIe translator device includes 1 upstream port and at least one downstream port. The upstream port of the converter device is connected to the RC or downstream of the other converter device, and the downstream port is connected to the terminal device or upstream of the converter device for cascading.
PCIe interrupts are a mechanism for informing computer software about the status of devices, and may send a message to inform the CPU to respond when an important event occurs. Three interrupt formats are specified in the PCIe protocol, namely INT, MSI or MSI-X. The INT format mainly supports traditional old equipment, and the two MSI formats and MSI-X format are main stream interrupt methods of the current PCIe equipment. The transmission direction of the interrupt message is from the downstream of the link to the upstream of the link, i.e. the terminal equipment to the CPU side. The existing MSI packet scheme is that each port contains an IP controller. When the downstream port generates an interrupt event source, signals are transferred from the downstream port to the upstream port. The uplink port sends a request signal to the controller IP module for requesting the controller to carry out packet grouping, and after the packet grouping is completed, the controller replies the uplink port signal and the request signal as handshake operation to indicate that the event is processed. When the uplink port generates an interrupt event, an MSI message is directly generated to the CPU. When an interrupt is generated on an uplink port, the current implementation method structure can normally enable a CPU to process, but in a PCIe system, a scene that a plurality of downlink ports simultaneously generate the interrupt possibly exists, because the request signal and the reply signal of the uplink port only have single bit, only can process a group of data at a time, and when a plurality of downlink ports or a plurality of events exist, the source cannot be judged. In summary, the prior art has the defect that the multi-port and multi-event interrupt cannot be processed.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that the multi-port and multi-event interrupt cannot be processed in the prior art, so as to provide an interrupt processing method, an interrupt processing device, electronic equipment and a storage medium.
According to a first aspect, the invention discloses an interrupt processing method, comprising the following steps: determining a current port to be processed according to the port interrupt signal; acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set, and determining the current to-be-processed interrupt event; acquiring event information corresponding to the interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of the interrupt event set; repeating the operation until the interrupt event set is empty.
Optionally, the determining the current port to be processed according to the port interrupt signal includes: acquiring a port interrupt signal; performing polling arbitration on the port interrupt signal to generate an arbitration result; and taking the port corresponding to the arbitration result as the current port to be processed.
Optionally, the port interrupt signal is a binary code, the number of bits is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports.
Optionally, the performing polling arbitration on the port interrupt signal, generating an arbitration result includes: polling bits of the port interrupt signal in a fixed order according to the port interrupt signal; when any bit of the port interrupt signal is 0, polling the next bit according to a fixed sequence; when any bit of the port interrupt signal is 1, setting the bit as 1, and setting the rest bits as 0, so as to generate an arbitration result; the arbitration result is binary code, the bit number is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports.
Optionally, the taking the port corresponding to the arbitration result as the current port to be processed includes: according to the arbitration result, searching bits with binary codes of 1; and taking the port corresponding to the bit as the current port to be processed.
Optionally, the repeating the above operation until the interrupt event set is empty further includes: continuing to carry out polling arbitration on the port interrupt signal to generate a new arbitration result; and taking the port corresponding to the new arbitration result as a new current to-be-processed port.
Optionally, the obtaining all interrupt events of the current pending port, generating an interrupt event set, and determining the current pending interrupt event includes: acquiring all interrupt events of the current port to be processed and event types corresponding to the interrupt events; according to the event type, sequencing the priority of the interrupt events to generate an interrupt event set; and taking the interrupt event with the highest priority in the interrupt event set as the current interrupt event to be processed.
According to a second aspect, the present invention discloses an interrupt handling apparatus comprising: the port determining module is used for determining a current port to be processed according to the port interrupt signal; the event determining module is used for acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set and determining the current to-be-processed interrupt event; the event processing module is used for acquiring event information corresponding to the interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of the interrupt event set; and the circulation processing module is used for repeating the operation until the interrupt event set is empty.
According to a third aspect, the invention discloses an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the interrupt processing method according to any of the first aspect and the optional embodiments of the first aspect.
According to a fourth aspect, the present invention discloses a computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps of the interrupt handling method according to the first aspect and any optional implementation manner of the first aspect.
The technical scheme of the invention has the following advantages:
1. according to the interrupt processing method disclosed by the invention, the current port to be processed is determined according to the port interrupt signal, so that timely response can be made when a plurality of ports are interrupted at the same time, and the condition that the system response is not timely due to the fact that a plurality of ports send signals at the same time is avoided. By generating the interrupt event set and determining the current interrupt event to be processed, timely response can be made when a plurality of interrupt events occur at the same port, and the condition that the system response is not timely due to the fact that a plurality of events send interrupt request messages at the same time is avoided. By moving the current interrupt event to be processed out of the interrupt event set, the system resource can be ensured not to be wasted, and the reasonable utilization of the system resource can be realized. By repeating the operation until the interrupt event set is empty, when a plurality of interrupt events occur at the same port, all the interrupt events can be processed in sequence, and the condition of bus congestion caused by simultaneous processing is avoided. In summary, the interrupt processing method provided by the invention can overcome the defect that the multi-port and multi-event interrupt can not be processed and simultaneously generated in the prior art.
2. According to the interrupt processing method disclosed by the invention, the polling arbitration is carried out on the port interrupt signals to generate the arbitration result, so that when a plurality of ports are interrupted at the same time, all the ports can be sequentially processed, the condition that a single port occupies a bus for a long time is avoided, the polling arbitration mode is relatively simple and efficient, a complex algorithm is not needed, and the delay is low. By sequencing the priority of the interrupt events, the tasks with high priority can be ensured to be processed in time, the corresponding delay can be reduced to the maximum extent, the system can process the tasks more efficiently, the resource utilization rate and the system efficiency are improved, and the potential risk is reduced. The priority ranking is performed through the event types, different event priorities can be set, and the system can be flexibly adjusted according to specific requirements. The events can be classified according to actual conditions, and proper priority can be set for each event type so as to meet different service requirements.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a specific example of an interrupt handling method according to an embodiment of the present invention;
FIG. 2 is a flowchart of another specific example of an interrupt handling method according to an embodiment of the present invention;
FIG. 3 is a flowchart of another specific example of an interrupt handling method according to an embodiment of the present invention;
FIG. 4 is a flowchart of another specific example of an interrupt handling method according to an embodiment of the present invention;
FIG. 5 is a flowchart of another specific example of an interrupt handling method according to an embodiment of the present invention;
FIG. 6 is a flowchart of another specific example of an interrupt handling method in an embodiment of the present invention;
FIG. 7 is a schematic block diagram of a specific example of an interrupt handling apparatus in an embodiment of the present invention;
FIG. 8 is a diagram illustrating an embodiment of an electronic device according to the present invention;
fig. 9 is a diagram showing a specific example of a storage medium according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The embodiment of the invention discloses an interrupt processing method, as shown in fig. 1, comprising the following steps:
and S1, determining a current port to be processed according to the port interrupt signal.
Specifically, an interrupt signal is received from each downstream port, and a port interrupt signal may be generated according to the interrupt signals of all downstream ports. The port interrupt signal may represent an interrupt event occurrence of all downstream ports. Where downstream ports refer to ports of devices connected to converter devices or other converter devices. Each PCIe translator device has one or more downstream ports for connecting to other devices.
And S2, acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set, and determining the current to-be-processed interrupt event.
Illustratively, all interrupt events for a pending port may be obtained by reading an interrupt status register in the configuration space. Wherein the interrupt status register is typically a bit field register, each bit representing an interrupt event. By reading the value of the interrupt status register and parsing the bits therein, the interrupt event triggered in the pending port can be determined.
And step S3, obtaining event information corresponding to the interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of the interrupt event set.
The interrupt request message is generated according to the interrupt vector, the data and the flag bit and the requirement of the interrupt format. Wherein the interrupt vector is a unique identifier for indicating the interrupt source device and the interrupt type, typically an integer value, for indexing the interrupt service routine in the interrupt vector table of the host. Wherein the data may be information related to an interrupt event for use by an interrupt service routine. Wherein the flag bits are used to indicate the status of the interrupt or other specific information, and these flag bits may be used for control or processing of the interrupt service routine. In particular, the specific format and fields of the event information may vary according to the specifications of the system architecture, operating system, and devices, and different specifications may define different message formats and fields to accommodate different requirements and characteristics, which the present invention is not limited to.
And S4, repeating the operation until the interrupt event set is empty.
According to the interrupt processing method disclosed by the invention, the current port to be processed is determined according to the port interrupt signal, so that timely response can be made when a plurality of ports are interrupted at the same time, and the condition that the system response is not timely due to the fact that a plurality of ports send signals at the same time is avoided. By generating the interrupt event set and determining the current interrupt event to be processed, timely response can be made when a plurality of interrupt events occur at the same port, and the condition that the system response is not timely due to the fact that a plurality of events send interrupt request messages at the same time is avoided. By moving the current interrupt event to be processed out of the interrupt event set, the system resource can be ensured not to be wasted, and the reasonable utilization of the system resource can be realized. By repeating the operation until the interrupt event set is empty, when a plurality of interrupt events occur at the same port, all the interrupt events can be processed in sequence, and the condition of bus congestion caused by simultaneous processing is avoided. In summary, the interrupt processing method provided by the invention can overcome the defect that the multi-port and multi-event interrupt can not be processed and simultaneously generated in the prior art.
As an optional embodiment of the present invention, the determining the current port to be processed according to the port interrupt signal, as shown in fig. 2, includes the following steps:
step S11, obtaining a port interrupt signal;
the port interrupt signal is a binary code, the bit number is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports. For example, when the total number of downstream ports in the structure is m, the port interrupt signal is a binary number of m bits, each bit sequentially corresponds to one downstream port, when any port is interrupted, the bit corresponding to the port is 1, and when any port is not interrupted, the bit corresponding to the port is 0. In particular, the port interrupt condition and the value of the corresponding bit may be defined in other manners in the prior art, which is not limited by the present invention.
Step S12, carrying out polling arbitration on the port interrupt signal to generate an arbitration result;
specifically, as shown in fig. 3, the process of generating the arbitration result may include the steps of:
step S121, polling bits of the port interrupt signal according to the port interrupt signal in a fixed order.
In step S122, when any bit of the port interrupt signal is 0, the next bit is polled in a fixed order.
In step S123, when any bit of the port interrupt signal is 1, the bit is set to 1, and the remaining bits are set to 0, so as to generate an arbitration result.
The arbitration result is a binary single-hot code, the bit number is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports.
Illustratively, when the total number of downstream ports in the structure is 4, the port interrupt signal is a 4-bit binary number, and each bit corresponds to one downstream port in turn. When the port interrupt signal is 0101, the signal is subjected to polling arbitration in the order from left to right. Firstly, starting arbitration from the third bit, wherein the third bit is 0, and polling the next bit; then arbitrating the second bit, wherein the second bit is 1, the second bit is set to 1, and the rest bits are set to 0, so as to generate an arbitration result 0100.
In particular, the order of polling and the manner of arbitration may be set according to the actual situation, which is not limited by the present invention.
And S13, taking the port corresponding to the arbitration result as the current port to be processed.
Specifically, as shown in fig. 4, the process of taking the port corresponding to the arbitration result as the current port to be processed may include the following steps:
step S131, according to the arbitration result, searching the bit with binary code 1.
Illustratively, when the arbitration result is 0100, the bit whose binary code is 1 at this time is the second bit.
Step S132, the port corresponding to the bit is used as the current port to be processed.
Illustratively, when the bit of the binary code 1 is the second bit, the downstream port corresponding to the second bit is used as the current port to be processed.
As an optional implementation manner of the present invention, the obtaining all interrupt events of the current pending port, generating an interrupt event set, and determining the current pending interrupt event, as shown in fig. 5, includes the following steps:
step S21, all interrupt events of the current port to be processed and event types corresponding to the interrupt events are obtained;
in particular, event types may be classified into data transfer completion interrupts, configuration change interrupts, error interrupts, device state change interrupts, and clock interrupts, etc. The data transmission completion interrupt refers to a type corresponding to a generated interrupt event when the device completes a data transmission operation. The configuration change interrupt refers to a type corresponding to a generated interrupt event when the configuration of the equipment is changed. The error interrupt refers to the type corresponding to the generated interrupt event when the equipment generates an error or abnormal condition. The device state change interrupt refers to a type corresponding to a generated interrupt event when the device is in a state change. Wherein a clock interrupt refers to a type corresponding to an interrupt event for periodically triggering time management and scheduling operations of the system. In particular, interrupt events may also be determined in other classification manners, which the present invention is not limited to.
Illustratively, all interrupt events for a pending port may be obtained by reading an interrupt status register in the configuration space. Wherein the interrupt status register is typically a bit field register, each bit representing an interrupt event. By reading the value of the interrupt status register and parsing the bits therein, the interrupt event triggered in the pending port can be determined.
Step S22, according to the event type, the interrupt events are prioritized, and an interrupt event set is generated;
for example, when event types are classified into data transfer completion interrupt, configuration change interrupt, error interrupt, device state change interrupt, and clock interrupt, priority ranking may be performed according to the degree of urgency of each type of event. Among these, false interrupts are generally the most important and urgent type of interrupt. It indicates that an error or abnormal condition has occurred in the device and that immediate processing is required to avoid further problems or damage. Similarly, data transmission completion interrupts are typically of higher priority. When the device completes an important data transmission operation, it is critical to handle this interrupt event in time to ensure the integrity and consistency of the data. Further, device state change interrupts are typically of medium priority. It indicates that the state of the device has changed and that the host may be required to perform a corresponding configuration or process. Although it may be as urgent as there are no errors or data transfer completion interruptions, there is still a need for timely response to maintain proper operation of the devices and systems. Still further, a clock interrupt is typically a system-level interrupt event that is used to periodically trigger time management and scheduling operations of the system. It may be of lower priority than other interrupt types because it does not belong to a device-specific interrupt event. Still further, configuration change interrupts are typically the lowest priority interrupt type. It indicates that the configuration of the device has changed and that some settings may need to be reinitialized or updated. It is generally less urgent or important than this and can therefore be handled with a lower priority.
In particular, the specific prioritization may vary according to the system requirements, the device characteristics, and the application scenario, and other prioritization methods may be applied according to the requirements of the specific system and device, which is not limited in the present invention.
And S23, taking the interrupt event with the highest priority in the interrupt event set as the current interrupt event to be processed.
For example, the highest priority event may be extracted from the prioritized interrupt event set, and then the interrupt status register in the configuration space may be read, and according to the interrupt flag bit in the interrupt status register, an appropriate statement may be used to select the interrupt event to be processed.
As an alternative embodiment of the present invention, the above operation is repeated until the interrupt event set is empty, as shown in fig. 6, and further includes the following steps:
step S5, continuing to carry out polling arbitration on the port interrupt signal to generate a new arbitration result;
illustratively, when the port interrupt signal is 0101 and the current arbitration result is 0100, the polling arbitration is continued for that signal in the order from left to right. Continuing to arbitrate from the first bit, wherein the first bit is 0, and polling the next bit; then, the zeroth bit is arbitrated, the zeroth bit is 1, the zeroth bit is set to 1, and the rest bits are set to 0, so that a new arbitration result 0001 is generated.
And S6, taking the port corresponding to the new arbitration result as a new current to-be-processed port.
Illustratively, when the arbitration result is 0001, the bit with the binary code of 1 is found to be the zeroth bit, and the downstream port corresponding to the zeroth bit is used as the new current to-be-processed port.
According to the interrupt processing method disclosed by the invention, the polling arbitration is carried out on the port interrupt signals and the arbitration result is generated, so that when a plurality of ports are interrupted at the same time, all the ports can be sequentially processed, the condition that a single port occupies a bus for a long time is avoided, the polling arbitration mode is relatively simple and visual, a complex algorithm is not needed, and the delay is low. By sequencing the priority of the interrupt events, the task with high priority can be ensured to be processed in time, the corresponding delay can be reduced to the maximum extent, the system can process the task more efficiently, the resource utilization rate and the system efficiency are improved, and the potential risk is reduced. The priority ranking is performed through the event types, different event priorities can be set, and the system can be flexibly adjusted according to specific requirements. The events can be classified according to actual conditions, and proper priority can be set for each event type so as to meet different service requirements.
The embodiment of the invention also discloses an interrupt processing device, as shown in fig. 7, comprising:
the port determining module 1 is used for determining a current port to be processed according to the port interrupt signal; the specific details refer to the description related to step S1 in the method embodiment of the present invention, and are not repeated here.
The event determining module 2 is used for acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set and determining the current to-be-processed interrupt event; the details refer to the description related to step S2 in the method embodiment of the present invention, and will not be described herein.
The event processing module 3 is configured to obtain event information corresponding to the interrupt event to be processed, generate an interrupt request packet, and move the current interrupt event to be processed out of the interrupt event set; the details refer to the description related to step S3 in the method embodiment of the present invention, and will not be repeated here.
A loop processing module 4, configured to repeat the above operations until the interrupt event set is empty; the details are described in the related description of step S4 in the method embodiment of the present invention, and are not repeated here.
According to the interrupt processing device provided by the invention, the current port to be processed is determined according to the port interrupt signal, so that timely response can be made when a plurality of ports are interrupted at the same time, and the condition that the system response is not timely due to the fact that a plurality of ports send signals at the same time is avoided. By generating the interrupt event set and determining the current interrupt event to be processed, timely response can be made when a plurality of interrupt events occur at the same port, and the condition that the system response is not timely due to the fact that a plurality of events send interrupt request messages at the same time is avoided. By moving the current interrupt event to be processed out of the interrupt event set, the system resource can be ensured not to be wasted, and the reasonable utilization of the system resource can be realized. By repeating the operation until the interrupt event set is empty, when a plurality of interrupt events occur at the same port, all the interrupt events can be processed in sequence, and the condition of bus congestion caused by simultaneous processing is avoided. In summary, the interrupt processing method provided by the invention can overcome the defect that the multi-port and multi-event interrupt can not be processed and simultaneously generated in the prior art.
The embodiment of the present invention further provides an electronic device, as shown in fig. 8, where the electronic device may include a processor 201 and a memory 202, where the processor 201 and the memory 202 may be connected by a bus or other means, and in fig. 8, the connection is exemplified by a bus.
The processor 201 may be a central processing unit (Central Processing Unit, CPU). The processor 201 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), field programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above.
The memory 202 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the interrupt handling method in the embodiments of the present invention. The processor 201 executes various functional applications of the processor and data processing, i.e., implements the interrupt processing method in the above-described method embodiments, by running non-transitory software programs, instructions, and modules stored in the memory 202.
Memory 202 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created by the processor 201, etc. In addition, memory 202 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 202 may optionally include memory located remotely from processor 201, which may be connected to processor 201 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more modules are stored in memory 202 that, when executed by processor 201, perform the interrupt handling method in the embodiment shown in fig. 1.
Specific details of the electronic device may be understood in response to the corresponding relevant descriptions and effects in the embodiment shown in fig. 1, which are not described herein.
The embodiment of the present invention further provides a computer readable storage medium, as shown in fig. 9, on which a computer program 301 is stored, which when executed by a processor, implements the steps of an interrupt handling method in the above embodiment. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.
It will be appreciated by those skilled in the art that implementing all or part of the above-described embodiment method may be implemented by a computer program to instruct related hardware, where the program may be stored in a computer readable storage medium, and the program may include the above-described embodiment method when executed. Wherein the storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.
Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and alterations to these embodiments without departing from the spirit of the invention and the scope of protection as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of the present invention.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. From the present disclosure, it will be readily understood by those of ordinary skill in the art that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (10)
1. An interrupt handling method, comprising:
determining a current port to be processed according to the port interrupt signal;
acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set, and determining the current to-be-processed interrupt event;
acquiring event information corresponding to the interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of the interrupt event set;
repeating the operation until the interrupt event set is empty.
2. The interrupt processing method according to claim 1, wherein determining a current port to be processed according to a port interrupt signal comprises:
acquiring a port interrupt signal;
performing polling arbitration on the port interrupt signal to generate an arbitration result;
and taking the port corresponding to the arbitration result as the current port to be processed.
3. The interrupt processing method of claim 2, wherein,
the port interrupt signal is a binary code, the bit number is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports.
4. The interrupt processing method according to claim 3, wherein performing polling arbitration for the port interrupt signal, generating an arbitration result, comprises:
polling bits of the port interrupt signal in a fixed order according to the port interrupt signal;
when any bit of the port interrupt signal is 0, polling the next bit according to a fixed sequence;
when any bit of the port interrupt signal is 1, setting the bit as 1, and setting the rest bits as 0, so as to generate an arbitration result; the arbitration result is binary code, the bit number is the same as the total number of ports, and the bits of the binary code are in one-to-one correspondence with the ports.
5. The interrupt processing method according to claim 4, wherein the step of using the port corresponding to the arbitration result as the current port to be processed comprises:
according to the arbitration result, searching bits with binary codes of 1;
and taking the port corresponding to the bit as the current port to be processed.
6. The interrupt processing method of claim 2, wherein the repeating of the above operations until after the interrupt event set is empty further comprises:
continuing to carry out polling arbitration on the port interrupt signal to generate a new arbitration result;
and taking the port corresponding to the new arbitration result as a new current to-be-processed port.
7. The interrupt processing method according to claim 1, wherein the obtaining all interrupt events of the current pending port, generating an interrupt event set, and determining a current pending interrupt event, comprises:
acquiring all interrupt events of the current port to be processed and event types corresponding to the interrupt events;
according to the event type, sequencing the priority of the interrupt events to generate an interrupt event set;
and taking the interrupt event with the highest priority in the interrupt event set as the current interrupt event to be processed.
8. An interrupt handling apparatus, comprising:
the port determining module is used for determining a current port to be processed according to the port interrupt signal;
the event determining module is used for acquiring all interrupt events of the current to-be-processed port, generating an interrupt event set and determining the current to-be-processed interrupt event;
the event processing module is used for acquiring event information corresponding to the interrupt event to be processed, generating an interrupt request message, and moving the current interrupt event to be processed out of the interrupt event set;
and the circulation processing module is used for repeating the operation until the interrupt event set is empty.
9. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the interrupt processing method according to any one of claims 1-7.
10. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the steps of the interrupt handling method according to any of claims 1-7.
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