CN102799549A - Multi-source-port data processing method and device - Google Patents
Multi-source-port data processing method and device Download PDFInfo
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Abstract
The invention discloses a multi-source-port data processing method. The method comprises the steps of setting the priority level of each source port; judging the number of source ports for ports operated for the same aim; directly processing the commands of the source port when there is only one source port for ports operated for the same aim; and respectively processing the commands of the multiple source ports according to the priority levels of the source ports when there are more source ports for ports operated for the same aim. Furthermore, the method comprises the steps of unifying the data bit width, the address bit width, the address unit bit width of each source port; unifying the clock signals of each source port and a respective target port; and separating the read-write operation of source ports. The data processing problem of mixed source ports (including timeliness source ports and non-timeliness source ports) is solved. Meanwhile, the data processing efficiency is significantly improved. The design of the target ports is simplified. The invention further discloses a multi-source-port data processing device.
Description
Technical field
The present invention relates to data processing field, relate in particular to a kind of data processing method and device of multi-source port.
Background technology
Usually, there are 4 kinds of data exchange modes between source port and the destination interface: one to one, one-to-many, many-one, multi-to-multi.Wherein complicated with the corresponding a plurality of destination interfaces of multiple source port.
Source port requires to be divided into ageing source port and non-ageing source port according to its timeliness that data are handled.Ageing source port; Be meant when it initiates the read request operation, require destination to be ready to data to be read, and these data are sent on the read data bus at official hour; Like EMEF (external memory interface, External Memory Interface) is ageing interface.Non-ageing source port; Be meant when it initiates the read request operation, the DSR that destination can will be read in the time easily, and these data are sent on the read data bus; These data all can be followed a control signal usually; Representing that these data are effective, is non-ageing interface like AXI (Advanced Extensible Interface, high speed extensive interface).
Usually in the FPGA/ASIC interface; Ageing source port and non-ageing source port are simultaneously and deposit; They often are used to same (or a plurality of) destination is carried out exchanges data; And in the prior art owing to lack effective mechanism, the data processing of ageing source port and non-ageing source port be separate, independently carry out, be unfavorable for so very much improving the data-handling efficiency of system.Please refer to Fig. 1, is the synoptic diagram that the direct destination interface of multiple source port connects shown in Fig. 1, source port or be ageing source port wherein, or be non-ageing source port.
Summary of the invention
The technical matters that the present invention will solve is; Overcome and to realize in the prior art that ageing source port and non-ageing source port carry out the problem of data processing, data processing method and device when providing a kind of ageing source port to mix with non-ageing source port to destination in same mechanism.
For solving the problems of the technologies described above, the present invention provides a kind of data processing method of multi-source port, comprising: the priority that each source port is set; Judge that the corresponding source port quantity of destination is one or a plurality of, when source port quantity is one, then directly handle the order of this source port; In source port quantity when being a plurality of, then respectively the order of each source port is handled according to the priority of the multiple source port of this destination of operation.
Said multi-source port comprises ageing source port and non-ageing source port, and the priority of ageing source port is higher than the priority of non-ageing source port.
Said method comprises also whether the clock signal of the clock signal of judging source port and destination interface is synchronous, and if not, then the clock signal with source port is synchronized on the clock signal of destination interface.
Said method comprises also whether the data bit width of judging between each source port is consistent, if not, and with the unified maximal value of data bit width of each source port for data bit width in the source port.
Said method comprises that also data preceding according to unification and after reunification are provided with corresponding data bit width switch.
Said method comprises also whether address unit's bit wide of judging each source port is consistent, if not, and the address unit's bit wide between then unified each source port.
Said method comprises also whether the address bit wide of judging each source port is consistent, if not, and the address bit wide between then unified each source port.
Carry out data bit width when unifying, adopt a high position to add zero method or duplicate the legacy data method, or duplicate legacy data and a high position adds zero method or zero insertion method.
Said method also comprises separates the bus that reads and writes data of each source port.
The present invention also provides a kind of data processing equipment of multi-source port, comprising: processing unit is used to be provided with the priority of each source port; Arbitration unit is used for for same destination, is one if operate the source port of this destination, then directly handles the order of this source port; If it is a plurality of operating the source port of this destination, then respectively the order of each source port is handled according to the priority of the multiple source port of operating this destination.
And; Data processing unit is used for when the data bit width of each source port is inconsistent, the data bit width of unified each source port; When address unit's bit wide of each source port is inconsistent; Address unit's bit wide of unified each source port, when bit wide is inconsistent in the address of each source port, the address bit wide of unified each source port of coupling; The fabric interface unit is used for the order of each source port is outputed to corresponding destination interface with the form of matrix.
The number of said arbitration unit is identical with the number of destination.
The invention has the beneficial effects as follows: the priority that ageing source port and non-ageing source port are set according to the characteristics of ageing source port and non-ageing source port; For same destination; The interface that priority processing priority is high; For the different purpose end, directly the order of each source port is handled.Through priority is set, improved the data-handling efficiency of mixed sources port widely.
Description of drawings
Fig. 1 is multiple source end interface and the mutual synoptic diagram of a plurality of destination in the prior art;
Fig. 2 is multiple source end interface of the present invention and the mutual synoptic diagram of a plurality of destination;
Fig. 3 is the synoptic diagram of DEU data exchange unit in an embodiment of the present invention, wherein not shown destination interface;
Fig. 4 is the process flow diagram of matched data bit wide in an embodiment of the present invention;
Fig. 5 is for being provided with the process flow diagram of byte switch in an embodiment of the present invention;
Fig. 6 is the process flow diagram of unified address unit bit wide in an embodiment of the present invention;
Fig. 7 is the process flow diagram of unified address bit wide in an embodiment of the present invention;
Fig. 8 is the process flow diagram of read operation data processing method in an embodiment of the present invention.
Embodiment
Combine accompanying drawing that the present invention is done further explain through embodiment below.
Please refer to Fig. 4-8, wherein be depicted as the method for data processing of the present invention.At first need to prove the multi-source port that the present invention is directed to, especially mixed sources port, promptly ageing source port and non-ageing source port.Usually; The priority of ageing source port is higher than the priority of non-ageing source port; And between each ageing source port, and between each non-ageing source port, the priority of each ageing source port or non-ageing source port is relevant with its data traffic; Data traffic is more little, and priority is high more.Generally speaking, data processing method provided by the invention is: at first confirming the priority of each source port, for same destination, is one if operate the source port of this destination, then directly handles the order of this source port; If it is a plurality of operating the source port of this destination, then respectively the order of each source port is handled according to the priority of the multiple source port of operating this destination.Further, in order to improve treatment effeciency, the interface of handling is outputed to the destination interface of correspondence with the form of matrix.
In one embodiment, in order to improve the efficient of a plurality of mixed sources port deal with data, before carrying out data processing, at first carry out the unification of each port data form, comprising the unification of data bit width, address unit and address bit wide.Respectively its specific practice is made an explanation below:
1, uniform data bit wide: the data bit width of different source ports maybe be different, are unfavorable for improving data-handling efficiency like this, in order to improve data-handling efficiency, with the maximal value of the data bit width unification of each source port data bit width in all source ports.For example, 3 source ports are arranged, wherein the data bit width of source port 0 is 8bit, and the data bit width of source port 1 is 16bit, and the data bit width of source port 2 is 64bit.Need the data bit width of source port 0 and source port 1 be expanded to 64bit so.Concrete, can adopt following two kinds of ways, one of which is that a high position adds 0, it is two for duplicating original data.When the way of legacy data is duplicated in employing, comprise two kinds of situation: a kind of is that the data bit width of source port is 2
n* the situation of 8bit integral multiple in above-mentioned example, is duplicated the data of source port 08 times, the data of source port 1 is duplicated 4 times can obtain 64 data.Another kind of situation is: if the data bit width of source port is not 2
n* the integral multiple of 8bit, for example the data bit width in source 0 is 10, then needs add 60 in a high position, then the data that obtain is duplicated 4 times to obtain the data that bit wide is 64bit, is not 2 at data bit width promptly
n* during the integral multiple of 8bit, be immediate 2 through adding 0 mode
n* the data of 8bit integral multiple, and then realize the coupling of data bit width through duplicating its data.
Can also adopt the zero insertion method, promptly realize the coupling of data bit width, but slotting 0 mode be relevant with the value of the low 2bit of source port address through slotting 0 mode.The data of supposing source port are 0x1234, need it unified be the data of 64bit, adopt slotting 0 mode, and when the low 2bit of source port address was 00, then after reunification data were 0x0000000000001234; When the low 2bit of source port address was 01, data after reunification were 0x0000000012340000; When the low 2bit of source port address was 10, data after reunification were 0x0000123400000000; When the low 2bit of source port address was 11, data after reunification were 0x1234000000000000.
Data bit width has made things convenient for the processing operation of data, but need guarantee that at destination former data bit width is constant after reunification.We solve this problem through design data bit wide switch: for example; The 8bit data of source port 0 are synchronized to the 64bit data bit width; Then the value of its data bit width switch should be 00000001; 8 bits in the bits per inch value corresponding data in the data bit width switch wherein, i.e. the 0th of the data bit width switch the correspondence 0-7bit of data after reunification, the 1st correspondence of data bit width switch be the 8-15bit of data after reunification; The rest may be inferred, the 56-63bit of the data after reunification of the 7th correspondence of data bit width switch.When the value of direct switch is 00000001, represent that having only 0-7 in the data of this 64bit is valid data, promptly real data bit width is 8bit.
Be that 16bit data 0x1234 is an example below with the source port, explain with its unification to be that 64 bit data are inserted 0 method and the design of data bit width switch accordingly:
| The 2bit value is hanged down in the address | Source interface 16bit data | Coupling 64bit data | The data bit width switch |
| 00 | 0x1234 | 0x0000000000001234 | 00000011 |
| 01 | 0x1234 | 0x0000000012340000 | 00001100 |
| 10 | 0x1234 | 0x0000123400000000 | 00110000 |
| 11 | 0x1234 | 0x1234000000000000 | 11000000 |
2, unify source port address unit bit wide: for example, 3 source ports are arranged, wherein the address unit of source port 0 is 16bit, and the address unit of source port 1 is 32bit, and the address unit of source port 2 is 64bit, and the address unit of so unified 3 source ports is 2
n* the integral multiple of 8bit as the address unit of these 3 source ports is unified for 8bit, then need add one 0 at the address of source port 0 lowest order; Lowest order adds two 0 in the address of source port 1; Lowest order adds three 0 in the address of source port 2, if address unit's unification of these 3 source ports is 16bit, then need not change the address of source port 0; Lowest order adds one 0 to need in the address of source port 1, and lowest order adds two 0 in the address of source port 2.If with address unit's unified in bit width is 64bit, then need the 0-1 position of source port 0 address be removed, the 0th of source port 1 address removed, do not change the address of source port 2.
3, the address bit wide of unifying source port: in a kind of preferred implementation, the address bit wide of unified source port can improve source port process of commands efficient more effectively.Here the source port address bit wide of being mentioned refers to the bit wide of the exercisable address of source port.Unified standard has two, one of which be address unified in bit width with each source port on the maximum address bit wide, it two is that address unified in bit width with each source port is on maximum effective address bit wide.Unified address bit wide adopts slotting 0 mode, but the position of inserting is relevant with the number of destination, and this is because need the high position of address date be given over to the gating destination.For example, the address bit wide of source port 0 is 16bit, and the address bit wide of source port 1 is 20bit, and the address bit wide of source port 2 is 32bit.Adopt unified mode, then need insert 0 of 16bit and 12bit respectively and expand their address bit wide source port 0 and source port 1 to the maximum address bit wide.Here, slotting 0 position is relevant with the number of destination, and the hypothesis goal end has m, then need satisfy 2
n＞=m, wherein n inserts 0 position from a high position to low level counting, and if any 5 of destinations, the n value should be 3 so, and promptly inserting 0 position should be between 13 and 12 of address.
In another kind of embodiment, before carrying out data processing operation, relatively whether the clock signal of each source port is synchronous with the clock signal of destination interface, if asynchronous, then the clock signal with each source port is synchronized on the clock signal of destination interface.Doing like this, is for the operation that makes the back has higher efficient and accuracy, has avoided the problem of easy error in the asynchronous sequential.
In one embodiment, with the read-write operation independent design of source port, its specific practice is that the corresponding reading and writing channel address of source port and the data bus that adopt a cover common data-bus are parsed, thereby realizes the independence of read-write channel.
Handle the command request of ageing source port through the reading and writing interrupt mode.Suppose at certain a moment; Data processing equipment is responding the read or write of the lower source port of priority; If run into the read or write of the high source port of priority, the read or write of the source port that then interrupt priority level is lower changes the higher read or write of response priority into.And after handling the operation of priority higher ports, the operation of response interruption again.Through the Interrupt Process mode, can effectively solve the different ageing problem of many interfaces, improve data processing efficiency.
Please refer to Fig. 8, shown in the figure for the process flow diagram of read operation data processing.When source port had request of data, judgement was read request or writes request, selects corresponding passage to handle then.The process flow diagram of data processing when being read request shown in Fig. 8; After source port sends read request information; Enable the destination interface of selecting each source port to operate through the passage gating; The arbitration unit that then the read request information of each source port is sent a corresponding destination interface carries out arbitration process, the priority of each source port data manipulation promptly is set, the read request operation that priority processing priority is high; The result of each arbitration unit is sent to the fabric interface unit, each destination interface is handled read request respectively.Write solicit operation and handle after the same method, just write operation carries out in different passages respectively with read operation.
Please refer to Fig. 2-3, the present invention also provides a kind of data processing equipment of multi-source port, comprises processing unit, arbitration unit and fabric interface unit.Said processing unit, being used for according to source port is the priority that the data traffic of ageing port or non-ageing port and port is confirmed port; Also be used for the clock signal of synchronisation source port and destination interface, and mate data bit width, address unit's bit wide, address bit wide of each source port etc.Said arbitration unit; Be used for when the multiple source port is operated same destination interface simultaneously; Confirm the processing order of each source port according to the priority of each source port, and when the source port that higher priority is arranged sends request, interrupt the operation of lower priority source port.Said fabric interface unit is used for each source port is outputed to corresponding destination interface to the operational order of destination interface with the form of matrix, improves the efficient of exchanges data between destination interface and the source port.
The present invention at first through ageing source port and non-ageing priority are set, when the multiple source port sends request of data to same destination interface, handles its request according to its priority; And the present invention also unifies the address unit's bit wide and the address bit wide of data, to make things convenient for the addressing operation of source port to destination interface, has also unified data bit width, has made things convenient for the processing of data, has improved the source port data processing efficiency; And the read-write operation of source port separated, improved the source port data processing efficiency further.
Above content is to combine concrete embodiment to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (12)
1. the data processing method of a multi-source port is characterized in that, the priority of each source port is set, and said method comprises:
Judge that the corresponding source port quantity of destination is one or a plurality of, when source port quantity is one, then directly handle the order of this source port; In source port quantity when being a plurality of, then respectively the order of each source port is handled according to the priority of the multiple source port of this destination of operation.
2. the method for claim 1 is characterized in that, said multi-source port comprises ageing source port and non-ageing source port, and the priority of ageing source port is higher than the priority of non-ageing source port.
3. method as claimed in claim 2 is characterized in that, said method comprises also whether the clock signal of the clock signal of judging source port and destination interface is synchronous, and if not, then the clock signal with source port is synchronized on the clock signal of destination interface.
4. method as claimed in claim 3 is characterized in that, said method comprises also whether the data bit width of judging between each source port is consistent, and if not, then the data bit width unification with each source port is the maximal value of data bit width in the source port.
5. method as claimed in claim 4 is characterized in that, said method comprises that also data preceding according to unification and after reunification are provided with corresponding data bit width switch.
6. like claim 4 or 5 described methods, it is characterized in that said method comprises also whether address unit's bit wide of judging each source port is consistent, if not, the address unit's bit wide between then unified each source port.
7. method as claimed in claim 6 is characterized in that, said method comprises also whether the address bit wide of judging each source port is consistent, if not, is the maximal value of source port address bit wide with the address unified in bit width between each source port then.
8. like claim 4 or 5 described methods, it is characterized in that, carry out data bit width when coupling, adopt a high position to add zero method or duplicate the legacy data method, or duplicate legacy data and a high position adds zero method or zero insertion method.
9. the method for claim 1 is characterized in that, said method also comprises separates the bus that reads and writes data of each source port.
10. the data processing equipment of a multi-source port is characterized in that, comprising:
Processing unit is used to be provided with the priority of each source port;
Arbitration unit is used for for same destination, is one if operate the source port of this destination, then directly handles the order of this source port; If it is a plurality of operating the source port of this destination, then respectively the order of each source port is handled according to the priority of the multiple source port of operating this destination.
11. data processing equipment as claimed in claim 10 is characterized in that, also comprises:
Data processing unit; Be used for when the data bit width of each source port is inconsistent; The data bit width of unified each source port, when address unit's bit wide of each source port is inconsistent, address unit's bit wide of unified each source port; When bit wide is inconsistent in the address of each source port, the address bit wide of unified each source port;
The fabric interface unit is used for the order of each source port is outputed to corresponding destination interface with the form of matrix.
12. data processing equipment as claimed in claim 10 is characterized in that, the number of said arbitration unit is identical with the number of destination.
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| CN2011101336783A CN102799549A (en) | 2011-05-23 | 2011-05-23 | Multi-source-port data processing method and device |
| PCT/CN2011/080663 WO2012159405A1 (en) | 2011-05-23 | 2011-10-11 | Data processing method and device for multiple source ports |
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| WO2015149329A1 (en) * | 2014-04-03 | 2015-10-08 | 华为技术有限公司 | Field programmable gate array and communication method |
| CN106911599A (en) * | 2015-12-23 | 2017-06-30 | 大唐半导体设计有限公司 | A kind of method and apparatus for processing baseband signal |
| CN107943727A (en) * | 2017-12-08 | 2018-04-20 | 深圳市德赛微电子技术有限公司 | A kind of high efficient DMA controller |
| CN117667466A (en) * | 2024-02-01 | 2024-03-08 | 井芯微电子技术(天津)有限公司 | Interrupt processing method and device, electronic equipment and storage medium |
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| CN107943727A (en) * | 2017-12-08 | 2018-04-20 | 深圳市德赛微电子技术有限公司 | A kind of high efficient DMA controller |
| CN107943727B (en) * | 2017-12-08 | 2021-02-09 | 深圳市德赛微电子技术有限公司 | High-efficient DMA controller |
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| WO2012159405A1 (en) | 2012-11-29 |
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