CN108153686B - Multi-interface CPU module - Google Patents
Multi-interface CPU module Download PDFInfo
- Publication number
- CN108153686B CN108153686B CN201810111319.XA CN201810111319A CN108153686B CN 108153686 B CN108153686 B CN 108153686B CN 201810111319 A CN201810111319 A CN 201810111319A CN 108153686 B CN108153686 B CN 108153686B
- Authority
- CN
- China
- Prior art keywords
- interface
- isa
- connector
- fpga
- interfaces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003745 diagnosis Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 101100513046 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) eth-1 gene Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention provides a multi-interface CPU module, comprising: the system comprises an SOC part, a first power supply part and a second power supply part, wherein the SOC part comprises at least two PCIE interfaces, two USB interfaces, a LPC interface, a SATA interface, two UART interfaces, a SPI interface, a VGA interface, a storage control interface and a memory control interface; the memory chip of the memory part is connected with the SOC part through a memory control interface, and the memory chip of the memory part is connected with the SOC part through a group of SATA interfaces; the PCIE part is characterized in that two PCIE interfaces are respectively connected to an Ethernet interface through an Ethernet bridge piece, and the Ethernet interface is connected to a connector; an ISA part, wherein an ISA bridge chip is connected to the SOC part through an LPC interface, and ISA signals obtained by the SIA bridge chip from the SOC part are simultaneously transmitted to the connector and the I/O pins of the FPGA through an ISA bus; the FPGA leads out I/O to the connector according to the time sequence requirement; the FPGA is connected to the CAN controller and connected to the connector through the CAN bus. The invention can solve the problem that the CPU can not directly communicate with the ISA bus in the prior art and the problem that interface resources are not abundant.
Description
Technical Field
The present invention relates to field bus communication technology, and more particularly, to a multi-interface CPU module.
Background
ISA bus (Industry Standard Architecture ) is a bus standard established by IBM corporation for PCs, allowing multiple CPUs to share system resources, and has good compatibility, it was the most widely used system bus in the last 80 th century, the clock frequency of ISA bus was 8MHZ, and the highest transmission rate of data transmission was 16M/S. It can be seen that ISA bus transmission rate is too low, CPU occupancy is high, and hardware interrupt resources are occupied. In addition, many CPU chips or modules currently in industry no longer support ISA buses, and thus employ buses (e.g., PCI, LPC) that communicate faster and more efficiently.
Because of the technical advantages of ISA buses themselves, there are still a number of peripheral devices still in use with standard ISA buses, but protocol conversion is necessary to achieve communication with the CPU. In addition, many devices currently under industrial control simply use the local functionality of the ISA bus, and a standard bus cannot be directly connected to such devices, which is not flexible.
In industrial control, the CPU board card of the control device often needs to communicate with devices with different interfaces, such as an ethernet interface, a serial port, a CAN bus interface, etc., if the corresponding CPU board card is designed separately according to different requirements each time, the cost and risk increase are unavoidable due to the high requirements of the CPU board card design and manufacturing process.
Disclosure of Invention
The embodiment of the invention provides a multi-interface CPU module, which can solve the problems that a CPU cannot directly communicate with an ISA bus and interface resources are not abundant in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a multi-interface CPU module, including: the system comprises an SOC part, a storage part, a PCIE part, an ISA part and a connector;
the SOC part comprises at least two PCIE interfaces, two USB interfaces, a LPC interface, a SATA interface, two UART interfaces, a SPI interface, a VGA interface, a storage control interface and a memory control interface;
the storage part consists of a memory chip and a storage chip, the memory chip is connected with the SOC part through the memory control interface, and the storage chip is connected with the SOC part through a group of SATA interfaces;
the PCIE part comprises two Ethernet bridge pieces, wherein two PCIE interfaces are respectively connected to the Ethernet interfaces through one Ethernet bridge piece, and the Ethernet interfaces are connected to the connector;
the ISA part comprises an ISA bridge chip, an FPGA and a CAN controller; the ISA bridge chip is connected to the SOC part through the LPC interface, ISA signals obtained by the SIA bridge chip from the SOC part are simultaneously transmitted to the connector and the I/O pin of the FPGA through an ISA bus, and are led out to the connector to serve as auxiliary output chip selection signals or input interrupt signals; the FPGA is connected to the CAN controller, and the CAN controller is connected to the connector through a CAN bus;
the connector is connected to the SOC part through two groups of USB interfaces, two groups of UART interfaces, one group of SPI interfaces and one group of VGA interfaces.
In one embodiment, the SOC portion is connected to a BIOS through the SPI interface.
In an embodiment, the SOC part further includes a third PCIE interface, and the SOC part is connected to the connector through the third PCIE interface.
In one embodiment, the signals transmitted between the local ISA bus and the FPGA include: address lines SA [19:0], address lines LA [23:17], data lines DA [7:0], ior# signal, iow# signal, memr# signal, memw# signal, iocs16#, MEMCS16# and interrupt request signal IRQ [15:3].
In one embodiment, the FPGA comprises:
the address decoding module outputs different chip selection signals to different address segments according to planning requirements of the ISA equipment and enables the chip selection signals to the connector;
and the auxiliary diagnosis module is connected with the address decoding module and used for providing partial pins distributed to the connector direction by the FPGA.
In one embodiment, the FPGA generates a path of CAN bus interface through the CAN controller according to the control of the ISA signal to connect with the connector.
In one embodiment, the FPGA further comprises a CAN driver whose chip select address is generated by the address decode module.
In one embodiment, the addresses and data sent by the ISA are sent to the connector in order by the FPGA.
In one embodiment, the FPGA sends the address signal transmitted from the local ISA bus to the CAN controller, and generates an ALE falling edge to latch the address signal by the CAN controller, and then outputs the instruction to be sent according to the read-write signal, the chip select signal and the CAN controller timing sequence.
In one embodiment, the connector is a COME connector.
The multi-interface CPU module of the embodiment of the invention has convenient operation, can provide a standard ISA bus and can communicate with local ISA bus equipment by adjusting an FPGA program;
the multi-interface CPU module of the embodiment of the invention has multiple functions, supports the 8-bit or 16-bit data width of an ISA bus and supports an IO operation mode or a MEMORY operation mode;
the multi-interface CPU module of the embodiment of the invention has rich interfaces, provides an ISA interface, expands CAN, serial ports, ethernet interfaces, SATA interfaces, USB interfaces, VGA interfaces, GPIO and high-speed PCIE interfaces commonly used in industrial control, and is convenient for communication of other modules. The module contains both low-speed parallel buses and high-speed serial buses, and the abundant interfaces can meet the interface requirements of various occasions.
The invention can solve the problem that the CPU can not directly communicate with the ISA bus in the prior art and the problem that interface resources are not abundant.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic block diagram of a CPU module with multi-interface communication function according to an embodiment of the present invention;
FIG. 2 is a diagram of an interface of an FPGA portion of an ISA bus portion according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic structural diagram of a multi-interface CPU module according to an embodiment of the present invention, as shown in fig. 1, the multi-interface CPU module includes: SOC part, storage part, PCIE part, ISA part and connector.
The SOC part is a CPU core chip of the X86 platform, and interface resources of the CPU core chip comprise at least two PCIE interfaces, two USB interfaces, a LPC interface, a SATA interface, a UART interface, a SPI interface, a VGA interface, a memory control interface (EMCC) and a memory control interface. In one embodiment, the memory control interface 64 bits wide, supporting DDR3L.
As shown in fig. 1, the storage part is composed of a memory chip (memory) and a storage chip (storage), the memory chip is connected with the SOC part through a memory control interface DDR3L, and the storage chip is connected with the SOC part through a set of SATA interfaces.
The PCIE portion includes two ethernet bridge slices, and the two PCIE interfaces are connected to ethernet interfaces (ETH 1 and ETH 2) through one ethernet bridge slice respectively, and the ethernet interfaces are connected to connectors (which may be COME connectors). The ethernet bridge may be 82574 or I210 of Intel corporation, for example, but the invention is not limited thereto.
The ISA part is a core part of the multi-interface CPU module, and is realized by adopting an LPC-to-ISA bridge chip in order to obtain a standard ISA bus. The ISA part comprises an ISA bridge chip, an FPGA and a CAN controller. The ISA bridge chip is connected to the SOC part through an LPC interface, ISA signals obtained by the SIA bridge chip from the SOC part are simultaneously transmitted to the connector and an I/O pin of an FPGA (local ISA bus is connected to the FPGA) through an ISA bus, and the ISA signals are led out to the connector to serve as auxiliary output chip selection signals or input interrupt signals. Standard ISA buses can only access standard ISA devices, and some devices of the local ISA buses may not be directly accessible, for example, when an ISA sub-device does not have the MEMCS16# pin, the ISA main device cannot flexibly perform 8-bit or 16-bit control. In order to assist communication, the invention connects other ISA signals except the data line in the ISA signals to the IO pin of a block of FPGA at the same time, and at the same time, a part of pins of the FPGA are led out to the connector to be used as auxiliary output chip selection signals or input interrupt signals.
In the embodiment of the invention, the ISA bridge chip can be W83626 or ITE8888.
The FPGA is connected to the CAN controller, the CAN controller is connected to the connector through the CAN bus, and the function of the FPGA is mainly to assist ISA bus communication.
The connector is connected to the SOC part through two groups of USB interfaces, two groups of UART interfaces, one group of SPI interfaces and one group of VGA interfaces.
The SOC portion is connected to a BIOS through an SPI interface.
In an embodiment, the SOC part further includes a third PCIE interface, and the SOC part is directly connected to the connector through the third PCIE interface.
As shown in FIG. 2, in one embodiment, the signals transferred between the local ISA bus and the FPGA include: address lines SA [19:0], address lines LA [23:17], data lines DA [7:0], ior# signal, iow# signal, memr# signal, memw# signal, iocs16#, MEMCS16# and interrupt request signal IRQ [15:3]. Due to the programmable function of the FPGA, the function of the IO pin can be customized according to the actual design requirement when the FPGA is connected with the connector.
In one embodiment, as shown in fig. 2, the FPGA includes:
and the address decoding module can output different chip selection signals to different address segments according to the planning requirements of the ISA equipment and enable the chip selection signals to the connector. Specifically, the address decoding module may perform decoding judgment according to the address output by the ISA bus, and output different chip selection signals and enable signals to the connector according to the ISA device planning requirement for different address segments. This function is applicable when multiple devices being accessed have independent chip select signal terminals, so that the corresponding address space can be conveniently adjusted. In addition, if the accessed ISA device does not have the IOCS16# or MEMCS16# pins, the address decoding module can feed back the IOCS16# or MEMCS16# states to the ISA master device according to the agreed address range, and then adjust the data access bit width. In order to access different ISA devices or ISA buses, a bus buffer chip is often required, and the buffer is closed in a non-access state, so that the address decoding module is also responsible for independently outputting an enable signal (den#) to the connector according to a read-write instruction, and the FPGA is internally processed by adopting the and operation of the read-write signal. This allows communication to be achieved for some non-standard ISA devices as well, and is flexible to adjust without changing the hardware of the device.
And the auxiliary diagnosis module is connected with the address decoding module and used for providing partial pins distributed to the connector direction by the FPGA. The device can be connected to a board card of the slave ISA equipment, diagnosis output pins, after some states of the slave ISA equipment are abnormal, the FPGA can quickly acquire related states, and after comprehensive judgment is carried out according to actual requirements, the states can be fed back to the ISA through two modes, one mode is through interruption of the ISA, the other mode is through setting of an internal data register, and the ISA bus is waited to access the data. The way this is done is that the interrupt number can be adjusted and the interrupt logic can be modified. The FPGA in this embodiment may adopt Altera Stratix II series EP2S60F1020I4N, and the present invention is not limited thereto.
The FPGA generates a path of CAN bus interface through the CAN controller according to the control of the ISA signal to be connected with the connector. The FPGA further comprises a CAN driver, and the chip selection address of the CAN driver is generated by the address decoding module. The main flow of the ISA driving the CAN controller through the FPGA is to control the multiplexing switching problem of the address and the data, firstly, the chip selection address of the CAN driver is generated by the decoding part of the FPGA, and the address and the data sent by the ISA are sent to the COME connector by the FPGA in an adjusting sequence. The FPGA sends the address signal transmitted by the ISA bus to the CAN controller (SJA 1000), simultaneously generates an ALE falling edge to enable the CAN controller to latch the address signal, and then outputs the instruction to be sent according to the read-write signal, the chip selection signal and the CAN controller time sequence.
The multi-interface CPU module of the embodiment of the invention has convenient operation, can provide a standard ISA bus and can communicate with local ISA bus equipment by adjusting an FPGA program;
the multi-interface CPU module of the embodiment of the invention has multiple functions, supports the 8-bit or 16-bit data width of the ISA bus, and supports an IO operation mode or a MEMORY operation mode.
The multi-interface CPU module of the embodiment of the invention has rich interfaces, and the board card of the interface not only provides an ISA interface, but also expands CAN, serial ports, ethernet interfaces, sata interfaces, USB interfaces, VGA interfaces, GPIO and high-speed PCIe interfaces commonly used in industrial control, thereby facilitating the communication of other modules. The multi-interface CPU module not only contains a low-speed parallel bus, but also contains a high-speed serial bus, and the abundant interfaces can meet the interface requirements of various occasions.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (5)
1. A multi-interface CPU module, comprising: the system comprises an SOC part, a storage part, a PCIE part, an ISA part and a connector;
the SOC part comprises at least two PCIE interfaces, two USB interfaces, a LPC interface, a SATA interface, two UART interfaces, a SPI interface, a VGA interface, a storage control interface and a memory control interface;
the storage part consists of a memory chip and a storage chip, the memory chip is connected with the SOC part through the memory control interface, and the storage chip is connected with the SOC part through a group of SATA interfaces;
the PCIE part comprises two Ethernet bridge pieces, wherein two PCIE interfaces are respectively connected to the Ethernet interfaces through one Ethernet bridge piece, and the Ethernet interfaces are connected to the connector;
the ISA part comprises an ISA bridge chip, an FPGA and a CAN controller; the ISA bridge chip is connected to the SOC part through the LPC interface, ISA signals obtained by the SIA bridge chip from the SOC part are simultaneously transmitted to the connector and the I/O pins of the FPGA through an ISA bus, and one part of I/O of the FPGA is led out to the connector to serve as auxiliary output chip selection signals or input interrupt signals; the FPGA is connected to the CAN controller, and the CAN controller is connected to the connector through a CAN bus;
the connector is connected to the SOC part through two groups of USB interfaces, two groups of UART interfaces, one group of SPI interfaces and one group of VGA interfaces;
the SOC part is connected to a BIOS through the SPI interface;
the SOC part further includes: the SOC part is connected to the connector through the third PCIE interface;
signals transmitted between the ISA bus and the FPGA locally include: address lines SA [19:0], address lines LA [23:17], data lines DA [7:0], IOR# signal, IOW# signal, MEMR# signal, MEMW# signal, IOCS16#, MEMCS16# and interrupt request signal IRQ [15:3];
the signals transmitted between the FPGA and the connector comprise chip selection OUTPUT CS# [5:0], INPUT signals INPUT [5:0], OUTPUT signals OUTPUT [5:0], OUTPUT enable DEN#, and reset RST# signals;
the FPGA comprises:
the address decoding module outputs different chip selection signals to different address segments according to planning requirements of the ISA equipment and enables the chip selection signals to the connector;
the auxiliary diagnosis module is connected with the address decoding module and used for providing partial pins distributed to the connector direction by the FPGA;
and the FPGA generates a path of CAN bus interface through the CAN controller according to the control of the ISA signal to be connected with the connector.
2. The multi-interface CPU module of claim 1 wherein the FPGA further comprises a CAN driver whose chip select address is generated by the address decode module.
3. The multi-interface CPU module of claim 2 wherein the addresses and data sent by the ISA are sent to the connector in a modified order by the FPGA.
4. The multi-interface CPU module of claim 2 wherein the FPGA transmits the address signal transmitted from the ISA bus locally to the CAN controller while generating an ALE falling edge to cause the CAN controller to latch the address signal, and then outputs the command to be transmitted according to the read/write signal and the chip select signal and the CAN controller timing.
5. The multi-interface CPU module of claim 1 wherein the connector is a COME connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810111319.XA CN108153686B (en) | 2018-02-05 | 2018-02-05 | Multi-interface CPU module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810111319.XA CN108153686B (en) | 2018-02-05 | 2018-02-05 | Multi-interface CPU module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108153686A CN108153686A (en) | 2018-06-12 |
| CN108153686B true CN108153686B (en) | 2023-12-22 |
Family
ID=62459645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810111319.XA Active CN108153686B (en) | 2018-02-05 | 2018-02-05 | Multi-interface CPU module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108153686B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189715B (en) * | 2018-08-16 | 2022-03-15 | 北京算能科技有限公司 | Programmable artificial intelligence accelerator execution unit and artificial intelligence acceleration method |
| CN109213722B (en) * | 2018-09-10 | 2022-07-08 | 郑州云海信息技术有限公司 | Memory control method, device, equipment and medium based on FPGA |
| CN109165185B (en) * | 2018-09-30 | 2020-06-09 | 杭州迪普科技股份有限公司 | PCIe signal conversion method and device based on FPGA |
| CN111832049B (en) * | 2020-07-09 | 2022-03-15 | 郑州信大捷安信息技术股份有限公司 | SPI-based data transmission method and system |
| CN112988659B (en) * | 2021-05-07 | 2021-07-20 | 湖南华自信息技术有限公司 | PCIE bridge chip redundant mainboard, design method and computer storage medium |
| CN115048327B (en) * | 2022-06-14 | 2024-03-22 | 中国电子科技集团公司第五十八研究所 | Bridge chip for converting PCIE into SATA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872314A (en) * | 2009-04-24 | 2010-10-27 | 勒斯塔尔技术有限责任公司 | The dynamic dispatching interruptable controller that is used for multiprocessor |
| CN104579885A (en) * | 2015-02-05 | 2015-04-29 | 青岛四方车辆研究所有限公司 | Protocol converter and conversion method of CPCI bus and ISA bus |
| CN207780763U (en) * | 2018-02-05 | 2018-08-28 | 中国铁道科学研究院 | Multiplex roles CPU module |
-
2018
- 2018-02-05 CN CN201810111319.XA patent/CN108153686B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872314A (en) * | 2009-04-24 | 2010-10-27 | 勒斯塔尔技术有限责任公司 | The dynamic dispatching interruptable controller that is used for multiprocessor |
| CN104579885A (en) * | 2015-02-05 | 2015-04-29 | 青岛四方车辆研究所有限公司 | Protocol converter and conversion method of CPCI bus and ISA bus |
| CN207780763U (en) * | 2018-02-05 | 2018-08-28 | 中国铁道科学研究院 | Multiplex roles CPU module |
Non-Patent Citations (2)
| Title |
|---|
| 基于DSP的PCI总线通用6轴运动控制卡的硬件设计;高云峰, 姜华;组合机床与自动化加工技术(第10期);全文 * |
| 基于FPGA的LPC-ISA总线桥接设计与实现;陈志列;庞观士;刘志永;沈航;;工业控制计算机(第05期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108153686A (en) | 2018-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108153686B (en) | Multi-interface CPU module | |
| US20150347345A1 (en) | Gen3 pci-express riser | |
| US8812758B2 (en) | Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports | |
| EP1021756B1 (en) | Direct memory access (dma) transactions on a low pin count bus | |
| US8738852B2 (en) | Memory controller and a dynamic random access memory interface | |
| US20090292854A1 (en) | Use of bond option to alternate between pci configuration space | |
| US9524262B2 (en) | Connecting expansion slots | |
| CN110968352B (en) | Reset system and server system of PCIE equipment | |
| US10078568B1 (en) | Debugging a computing device | |
| CN114253884B (en) | FPGA-based multi-master-to-multi-slave access arbitration method, system and storage medium | |
| CN106776458B (en) | Communication device and communication method between DSPs (digital Signal processors) based on FPGA (field programmable Gate array) and HPI (high Performance Integrated interface) | |
| KR100684553B1 (en) | Microprocessor coupled to dual port memory | |
| CN207780763U (en) | Multiplex roles CPU module | |
| JPS59220821A (en) | Common bus controller of computer | |
| CN104951268A (en) | Method for implementing extended high-performance graphics card based on CPCI | |
| US9032252B2 (en) | Debug barrier transactions | |
| CN208110441U (en) | A kind of server high reliability clock control system | |
| TW202343237A (en) | Datacenter-ready secure control module and control method | |
| CN208622092U (en) | A kind of high-performance data processing unit based on double Loongson processors | |
| RU194084U1 (en) | Board for building digital systems | |
| AU2016340044A1 (en) | A communications device | |
| CN110765038B (en) | Communication method and device of processor and LPC device and storage medium | |
| CN112783071A (en) | SDIO controller, FPGA board card and SDIO test system | |
| CN101021826A (en) | Bridging device and correlation electronic system and interface control method | |
| RU158939U1 (en) | PERIPHERAL INTERFACE CONTROLLER (KPI-2) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |