CN101021826A

CN101021826A - Bridging device and correlation electronic system and interface control method

Info

Publication number: CN101021826A
Application number: CN 200710088460
Authority: CN
Inventors: 余嘉兴; 陈林鸿
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2007-03-27
Filing date: 2007-03-27
Publication date: 2007-08-22

Abstract

The invention provides a bridging device, which includes a first interface, and the interface includes at least one multiplexing clock signal line outputting a first and second clock signal, to control the access of the first and second device coupling on the bridging device. Among them, the bridging device is based on a mode of operation, which can selectively output the first or second clock signal from the multiplexing clock signal line and finish the access of the first and second device.

Description

Bridge-set and relevant electronic system and interface control method thereof

Technical field

The present invention relates to a kind of bridge-set and relevant interface control method thereof, particularly relate to a kind of bridge-set and control method thereof that can dynamically switch on distinct interface.

Background technology

Serial peripheral interface (serial peripheral interface, SPI) and low pin count (lowpin count, LPC) interface is two kinds of common data transmission interfaces in the design of general chipset (chipset) or bridge-set (bridge).LPC interface or title lpc bus, generally be used for electronic system so that the device of low bandwidth (for example: but boot rom or super input-output unit) is connected to CPU (central processing unit) (CPU), it comprises that seven main control signals are to carry out bidirectional data transfers.These seven main control signals are divided into three control signal LPC_FRAME, LPC_RST, LPC_CLK and four data-signal LPC_AD[3:0].LPC_FRAME is a frame position (frame bit) signal, begins to carry out the access of data in order to enable a LPC device.LPC_RST is that a reset signal, LPC_CLK are a clock signal and a LPC_AD[3:0] in order to multiplexed processing command, address and data.The SPI interface then comprises selects signal SPI_CS, clock signal SPI_CLK, input signal SPI_MOSI and four control signals of output signal SPI_MOSO.Select signal SPI_CS to begin to carry out the access of data in order to enable a SPI device (for example SPI flash memory), clock signal SPI_CLK provides SPI required clock signal, and input signal SPI_MOSI and output signal SPI_MOSO are then in order to carry out the transmission of data.Generally speaking, the program code of the ROM-BIOS of electronic system (BIOS) is to be placed on the LPC ROM (read-only memory), therefore, need at least on the bridge-set corresponding to the corresponding pin number of above-mentioned LPC control signal so that LPC to be provided interface, thereby connect the LPC ROM (read-only memory).Yet in existing application, the program code of BIOS also may be placed in the SPI flash memory, for SPI is provided interface, also needs four pins to connect the SPI flash memory on the bridge-set.Therefore, must support this two kinds of interfaces simultaneously in the General System design.

See also Fig. 1.Fig. 1 shows the synoptic diagram of an existing electronic system.At least comprise a bridge-set 110, a LPC device 120 and a SPI device 130 in the electronic system 100.Wherein, LPC device 120 and SPI device 130 are connected on the bridge-set 110 by LPC interface 140 and SPI interface 150 respectively.As shown in the figure, because both specification difference, will need on the bridge-set two groups independently pin so that LPC interface and SPI interface to be provided, thus, with make the required number of pins of bridge-set with and volume increase, make the complexity that the design of bridge-set becomes.

Summary of the invention

In view of this, one of purpose of the present invention promptly is to provide a kind of bridge-set design of electronic system, and a kind of interface control method is provided, with the purpose that reaches simplified design and reduce number of pins.

Based on above-mentioned purpose, the invention provides a kind of bridge-set, comprise one first interface, first interface comprises at least one multiplexed clock cable, wherein, this bridge-set is according to an operator scheme, optionally at online output one first clock signal of this multiplexed clock signal or a second clock signal, in order to control one first device or one second access of installing that is coupled to this bridge-set respectively.

The present invention more provides a kind of bridge-set, comprises one first interface.First interface comprises the M pin, in order to couple one first device and one second device, wherein, this first device is coupled to this M pin and this second device and is coupled to N pin in this M pin, N＜M, M are the integer greater than 1, and N is the integer greater than 0, and output one first clock signal and a second clock signal on the clock pin in this M pin are in order to control the access of this first device and this second device respectively.Wherein, this bridge-set is optionally exported this first clock signal or this second clock signal according to an operator scheme on this clock pin, so that this first device or this second device are carried out access.

For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.

Description of drawings

Fig. 1 shows the synoptic diagram that an existing electronic system connects.

Fig. 2 shows an electronic system synoptic diagram according to the embodiment of the invention.

Fig. 3 shows a bridge-set block synoptic diagram according to the embodiment of the invention.

Fig. 4 shows a process flow diagram according to the interface control method of the embodiment of the invention.

Fig. 5 shows a demonstration sequential chart according to the embodiment of the invention.

Fig. 6 shows the electronic system synoptic diagram according to another embodiment of the present invention.

The reference numeral explanation

The SPI-serial peripheral interface; The LPC-low pin count; The 100-electronic system; The 110-bridge-set; The 120-LPC device; The 130-SPI device; The 140-LPC interface; The 150-SPI interface;

LPC_CLK, SPI_CLK-clock signal; The 200-electronic system; The 210-bridge-set; 220,230,240-LPC device; The multiplexed interface of 250-; 260,270-SPI device; TPM-trusted platform module architecture module;

SPI_CS0, SPI_CS1, CLK, LPC_RST, AD[3:0], the LPC_FRAME-signal wire; The 310-arbitration modules; The 320-LPC controller; The 330-SPI controller; The 340-clock generating unit; The MODE-operator scheme; The S410-S460-step; The 500-sequential chart.

Embodiment

Embodiments of the invention relate to a bridge-set design, this bridge-set comprises a multiplex interface at least, the interface of two kinds of different sizes is provided in the multiplex interface, multiplex interface comprises at least one multiplexed clock cable (or claiming multiplexed clock pin), exportable one first clock signal (LPC_CLK) of multiplexed clock cable and a second clock signal (SPI_CLK) are in order to control one first device (LPC device) and one second access of installing (SPI device) that is coupled to bridge-set respectively.First device has a LPC interface, and second device has a SPI interface, and first device and second device couple by the multiplex interface of LPC interface and SPI interface and bridge-set respectively.Wherein, bridge-set is according to an operator scheme, optionally at online output first clock signal of multiplexed clock signal or second clock signal, so that first device or second device are carried out access.By some pin in shared two interfaces of part, reach the purpose of the number of pins that reduces the bridge-set use, also simplified the complexity of design.In addition, the mechanism that the present invention also provides dynamic switching to use two kinds of interfaces, the signal that can export according to different operator scheme conversion multiplex interfaces automatically, more flexible in the feasible design.

Fig. 2 shows an electronic system synoptic diagram according to the embodiment of the invention.Comprise a bridge-set 210, LPC device 220,230 and 240 and

SPI device

260 and 270 in the electronic system 200.Bridge-set 210 comprises a multiplex interface 250 at least, and LPC device 220,230 and 240 and

SPI device

260 and 270 all couple by multiplex interface 250 and bridge-set 210.LPC device 220,230 and 240 all has a LPC interface, and

SPI device

260 and 270 all has a SPI interface, and LPC device 220,230 and 240 and

SPI device

260 and 270 couple by the multiplex interface of LPC interface and SPI interface and bridge-set respectively.The LPC device can be the device that any LPC of utilization interface carries out data transmission, for instance, LPC device 220 is a trusted platform module architecture module (Trusted Platform Module, TPM), in order to carry out the checking of encryption and decryption and hardware gold key, can be considered a kind of security arrangement, be the application at a kind of LPC interface.In addition, LPC device 220 also transmits by a SM bus interface (as shown in the figure signal wire CLKRUN, SMBCLK and SMBDAT) and bridge-set 210.Device 230 can be the super I/O device of a LPC, can be a LPC ROM (read-only memory) and install 240, the bios program code of using during in order to the storage start.In addition,

SPI device

260 and 270 can be the device that any SPI of utilization interface carries out data transmission, for instance, and SPI flash memory 1260 as shown in fig. 1 and SPI flash memory 2270.

As shown in Figure 2, comprised following signal wire (pin) in the multiplex interface 250 of bridge-set 210 at least: select signal wire SPI_CS0 and SPI_CS1, multiplexed clock cable CLK (LPC_CLK/SPI_CLK), reset signal line LPC_RST, data signal line AD[3:0] and line trigger signal LPC_FRAME.Wherein, multiplexed clock cable CLK (LPC_CLK/SPI_CLK), reset signal line LPC_RST, data signal line AD[3:0] and line trigger signal LPC_FRAME in order to LPC to be provided interface, to connect LPC device 220-240.In addition, select signal wire SPI_CS0 and SPI_CS1, multiplexed clock cable CLK and data signal line AD[3:0] in any two (for example data signal line AD1 and AD0) in order to SPI to be provided interface, to connect SPI device 260-270.In this embodiment, multiplexed clock cable CLK and data signal line AD1 and AD0 are shared, have therefore reduced the use of three number of pins at least.For instance, if the number of pins at the multiplexed interface of hypothesis is M, in this embodiment, M equals 7, and the needed number of pins of LPC device equals M (7), the required number of pins of SPI device is 4, because of any two data signal lines in its shared four data signal lines, add and share multiplexed clock cable CLK, therefore only used the N pin (3) in the M pin, so, for the support to both interfaces is provided, bridge-set only needs 8 number of pins, compared to existing 11 number of pins that need, has obviously reduced the use of 3 number of pins.

Fig. 3 shows a block synoptic diagram according to the bridge-set 210 of the embodiment of the invention.As shown in Figure 3, an arbitration modules (arbiter) 310, a LPC controller 320, a SPI controller 330 and a clock generation unit 340 have been comprised in the bridge-set 210.Arbitration modules 310 is according to operator scheme MODE, and decision is output first clock signal LPC_CLK or second clock signal SPI_CLK on multiplexed clock cable CLK.Operator scheme MODE is a known parameter, can for example be obtained in the South Bridge chip by the last bed device of bridge-set.For instance, system will notify South Bridge chip to carry out access to the LPC device or to the SPI device.Because for system, that a period of time will be carried out access to that device and be known in advance, therefore arbitration modules 310 can obtain this known operation mode information, and control and adjust in the multiplex interface according to this known operator scheme and to share the online output of signal, so that LPC device or SPI device are carried out access.

For instance, when operator scheme is access to LPC device 230, arbitration modules 310 will utilize clock generating unit 340 to export the first clock signal LPC_CLK that meets the LPC standard on multiplexed clock cable CLK, and the LPC data of selecting LPC controller 320 to produce export data signal line AD[3:0 to] on.Simultaneously, bridge-set 210 outputs one enable signal (for example draws line trigger signal LPC_FRAME to low level " L " or line trigger signal LPC_FRAME is gone up and export one by the pulse signal of low level " L " to high level " H ") on the line trigger signal LPC_FRAME of LPC device 230, to enable LPC device 230, make it begin multiplex interface access LPC data by connecting.Similarly, when operator scheme is access to SPI ROM (read-only memory) 260, arbitration modules 310 will utilize clock generating unit 340 to export the second clock signal SPI_CLK that meets the SPI standard on multiplexed clock cable CLK, and the SPI data of selecting SPI controller 330 to produce export data signal line AD[3:0 to] a wherein data signal line AD1 on, this data signal line AD1 is connected on the input signal cable SPI_MOSI of SPI ROM (read-only memory) 260, is used as its input signal source.At this moment, bridge-set 210 output one enable signals (for example will select signal wire SPI_CS0 to draw and be low level " L ") are selecting on the signal wire SPI_CS0, to enable SPI ROM (read-only memory) 260, make it begin multiplex interface access SPI data by connection.Wherein, the first clock signal LPC_CLK and second clock signal SPI_CLK have different first frequencies and second frequency respectively, and first frequency accords with the LPC standard, and second frequency accords with the SPI standard.

Therefore, according to the embodiment of the invention, by control bridge-set 210 multiplexed clock cable CLK and data signal line AD[3:0] output, can be according to operator scheme, dynamically switch access is between LPC device 230 and SPI flash memory 260.

In the embodiment of Fig. 2, bios program code is to be stored in the LPC ROM (read-only memory) 240.Yet, in another embodiment, bios program code can be seated in

SPI flash memory

260 or 270, therefore do not need to use LPC ROM (read-only memory) (as shown in Figure 6), again according to bridge-set of the present invention and method, number of pins that can be less is carried out access to SPI flash memory and LPC device, and it is easier and more flexible to make on the hardware design.In addition, in other embodiments, also the SPI flash memory among Fig. 2 260 and 270 can be removed, only stay LPC ROM (read-only memory) and LPC device, realize the application mode of pure LPC ROM (read-only memory).

Fig. 4 shows a process flow diagram 400 according to the interface control method of the embodiment of the invention.In this embodiment, comprise a LPC device and a SPI flash memory (for example SPI flash memory 0 260 among Fig. 2) in the supposing the system simultaneously, bios program code is to be seated in the SPI flash memory 260, and the control signal of the selection signal of LPC device and SPI flash memory all be not enabled (that is all being made as high level " H ") when initial.Please be simultaneously with reference to Fig. 2 and Fig. 4.As shown in the figure, at first, as step S410, setting multiplex interface earlier is the SPI interface, with the bios program code of being preset by loading in the SPI flash memory 260.In this step, setting multiplex interface is that the SPI interface promptly is to make signal wire CLK, AD1, AD0 and SPI_CS0 output as follows:

CLK-＞SPI_CLK

AD1-＞SPI_MISI

AD0-＞SPI_MISO

SPI_CS0-＞“L”

Because control signal SPI_CS0 is set as " L ", expression SPI flash memory 260 is enabled, and therefore can carry out the transmission of data by multiplex interface.Then, as step S420, check whether the loading of bios program code is finished.If not, represent that then present operator scheme still is the access to the SPI device, does not therefore change the configuration of shared portion signal wire in the multiplex interface.If the loading of bios program code is finished (step S420 is) afterwards, operator scheme will become the access to the LPC device this moment, so the automatic setting multiplex interface is the LPC interface, to prepare that the LPC device is carried out access.In this step, setting multiplex interface is that the SPI interface promptly is to make signal wire CLK, AD1, AD0, LPC_FRAME and SPI_CS0 output as follows:

SPI_CS0-＞”H”

CLK-＞LPC_CLK

AD1-＞LPC_AD1

AD0-＞LPC_AD0

LPC_FRAME-＞”L”

SPI_CS0 is made as " H " be to make SPI flash memory 260 anergies (disable), make it can't received signal, then LPC_FRAME is made as " L ", expression LPC device is enabled, and therefore can carry out the transmission of data by multiplex interface.So bridge-set begins the LPC device is carried out access, this moment, operator scheme was the access to the LPC device.Then, as step S440, whether the checked operation pattern becomes is carried out access to SPI flash memory 260.If not, represent that then present operator scheme still is the access to the LPC device, does not therefore change the configuration of shared portion signal wire in the multiplex interface.When finding that this moment, operator scheme became access (step S440 is) to SPI flash memory 260, the automatic setting multiplex interface is the SPI pattern, shown in step S450.Then, as step S460, whether inspection is finished the execution of the access of SPI flash memory 260.If not, represent that then present operator scheme still is the access to SPI flash memory 260, does not therefore change the configuration of shared portion signal wire in the multiplex interface.When finding the access of SPI flash memory 260 after complete (step S460 is), operator scheme will become the access to the LPC device this moment, therefore get back to step S430, the automatic setting multiplex interface is the LPC interface, to carry out the LPC device is carried out access.Therefore, by bridge-set design of the present invention, bridge-set can be according to operator scheme, the configuration of switching multiplexing interface shared portion signal wire (pin) dynamically, so that switch on the execution between LPC device and SPI device, thereby can support the data access of LPC interface and two kinds of interfaces of SPI interface simultaneously.

For instance, please refer to Fig. 5.Fig. 5 shows a demonstration sequential chart according to the embodiment of the invention.Indicated the control signal SPI_CS of a SPI device, selection signal LRC_FRAME, a clock signal clk and the data-signal AD[3:0 of a LPC device in the sequential chart 500] the variation situation.As shown in the figure, time t1 is considered as the SPI operating cycle during t2, and time t3 is considered as the LPC operating cycle during t4.When time point t1, control signal SPI_CS is drawn to be low level " L ", the SPI device is enabled, and then clock signal clk will be exported one and have the clock signal 510 of first frequency, and data-signal AD[3:0] output SPI data, so the SPI device can receive this SPI data.Wherein, first frequency is the clock frequency that meets the SPI standard.When time point t2, SPI Data Transfer Done, SPI_CS are pulled back to high level " H ", make the SPI device can't receive data-signal AD[3:0 again] data.

Then, when time point t3, select signal LPC_FRAME to be drawn and be low level " L ", retract high level immediately again, make the LPC device be enabled, then clock signal clk will export one and have the clock signal 520 of second frequency, and data-signal AD[3:0] export the LPC data, so the LPC device can receive this LPC data.Wherein, second frequency is the clock frequency that meets the LPC standard.When time point t4, the LPC Data Transfer Done, the output of clock signal clk is stopped, and makes the LPC device can't receive data-signal AD[3:0 again] data.Hence one can see that, controls the output of these shared pins, can reach the purpose of dynamically supporting the data access of LPC interface and SPI interface simultaneously.Though it should be noted that among the embodiment it is that access with LPC interface and SPI interface describes, yet and non-limiting the present invention only limit to this two kinds of interfaces.In other words, other has the data transmission interface of similar characteristics, and for example the MMC interface also can be complied with the multiplex interface that its characteristic provide the shared portion pin, be aided with interface control method of the present invention again, reach the purpose that reduces number of pins and dynamically switch on the access between distinct interface.

Above-mentioned explanation provides several different embodiment or uses distinct methods of the present invention.Specific device in the example and method the invention is not restricted to this certainly in order to help explaination main spirit of the present invention and purpose.

Therefore; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.

Claims

1. bridge-set comprises:

One multiplexed clock cable;

A plurality of data signal lines; And

One arbitration modules is in order to according to this operator scheme, optionally at online output one first clock signal of this multiplexed clock signal or a second clock signal, in order to control one first device or one second access of installing that is coupled to this bridge-set respectively.

2. bridge-set as claimed in claim 1, wherein, this first device is coupled to described data signal line, and this second device is coupled to a part of data signal line in the described data signal line.

3. bridge-set as claimed in claim 1, wherein, when this operator scheme be to this first the device access the time, this arbitration modules is exported this first clock signal at this multiplexed clock cable, and selects one first data to export described data signal line to.

4. bridge-set as claimed in claim 1, wherein, when this operator scheme be to this second the device access the time, this arbitration modules is exported this second clock signal at this multiplexed clock cable, and selects one second data to export this partial data signal wire of described data signal line to.

5. bridge-set as claimed in claim 1, wherein, this first device has more a line trigger signal, when this operator scheme be to this first the device access the time, this bridge-set is exported an enable signal in this line trigger signal, with enable this first the device.

6. bridge-set as claimed in claim 1, wherein, this second device has one and selects signal wire, and when this operator scheme was access to this second device, this bridge-set was exported an enable signal and is selected signal wire in this, to enable this second device.

7. bridge-set as claimed in claim 1, wherein, this first clock signal has a first frequency and this second clock signal has a second frequency, and this second frequency is different from this first frequency.

8. bridge-set as claimed in claim 1, wherein, this first device is that one to have the LPC device of a low pin count interface and this second device be one to have the SPI device of a serial peripheral interface, and this LPC device and this SPI device couple by this first interface of this LPC interface and this SPI interface and this bridge-set respectively.

9. bridge-set comprises:

One first interface, comprise the M pin, in order to couple one first device and one second device, wherein, this first device is coupled to this M pin and this second device and is coupled to N pin in this M pin, N＜M, M is the integer greater than 1, and N is the integer greater than 0, and exports one first clock signal and a second clock signal on the clock pin in this M pin, in order to control the access of this first device and this second device respectively

Wherein, this bridge-set is optionally exported this first clock signal or this second clock signal according to an operator scheme on this clock pin, so that this first device or this second device are carried out access.

10. bridge-set as claimed in claim 9, wherein, this first device is that one to have the LPC device of a LPC interface and this second device be one to have the SPI device of a SPI interface, and this LPC device and this SPI device couple by this first interface of this LPC interface and this SPI interface and this bridge-set respectively.